1 //===-- SystemZOperators.td - SystemZ-specific operators ------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i64>]>;
14 def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i64>,
16 def SDT_ZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
17 def SDT_ZCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
18 def SDT_ZICmp : SDTypeProfile<0, 3,
21 def SDT_ZBRCCMask : SDTypeProfile<0, 3,
24 SDTCisVT<2, OtherVT>]>;
25 def SDT_ZSelectCCMask : SDTypeProfile<1, 4,
30 def SDT_ZWrapPtr : SDTypeProfile<1, 1,
33 def SDT_ZWrapOffset : SDTypeProfile<1, 2,
37 def SDT_ZAdjDynAlloc : SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>;
38 def SDT_ZGR128Binary32 : SDTypeProfile<1, 2,
39 [SDTCisVT<0, untyped>,
42 def SDT_ZGR128Binary64 : SDTypeProfile<1, 2,
43 [SDTCisVT<0, untyped>,
46 def SDT_ZAtomicLoadBinaryW : SDTypeProfile<1, 5,
53 def SDT_ZAtomicCmpSwapW : SDTypeProfile<1, 6,
61 def SDT_ZMemMemLength : SDTypeProfile<0, 3,
65 def SDT_ZMemMemLoop : SDTypeProfile<0, 4,
70 def SDT_ZString : SDTypeProfile<1, 3,
75 def SDT_ZI32Intrinsic : SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>;
76 def SDT_ZPrefetch : SDTypeProfile<0, 2,
79 def SDT_ZLoadBSwap : SDTypeProfile<1, 2,
82 SDTCisVT<2, OtherVT>]>;
83 def SDT_ZStoreBSwap : SDTypeProfile<0, 3,
86 SDTCisVT<2, OtherVT>]>;
87 def SDT_ZTBegin : SDTypeProfile<0, 2,
90 def SDT_ZInsertVectorElt : SDTypeProfile<1, 3,
94 def SDT_ZExtractVectorElt : SDTypeProfile<1, 2,
97 def SDT_ZReplicate : SDTypeProfile<1, 1,
99 def SDT_ZVecUnaryConv : SDTypeProfile<1, 1,
102 def SDT_ZVecUnary : SDTypeProfile<1, 1,
104 SDTCisSameAs<0, 1>]>;
105 def SDT_ZVecBinary : SDTypeProfile<1, 2,
108 SDTCisSameAs<0, 2>]>;
109 def SDT_ZVecBinaryInt : SDTypeProfile<1, 2,
113 def SDT_ZVecBinaryConv : SDTypeProfile<1, 2,
116 SDTCisSameAs<1, 2>]>;
117 def SDT_ZVecBinaryConvInt : SDTypeProfile<1, 2,
121 def SDT_ZRotateMask : SDTypeProfile<1, 2,
125 def SDT_ZJoinDwords : SDTypeProfile<1, 2,
129 def SDT_ZVecTernary : SDTypeProfile<1, 3,
133 SDTCisSameAs<0, 3>]>;
134 def SDT_ZVecTernaryInt : SDTypeProfile<1, 3,
139 def SDT_ZVecQuaternaryInt : SDTypeProfile<1, 4,
145 def SDT_ZTest : SDTypeProfile<0, 2, [SDTCisVT<1, i64>]>;
147 //===----------------------------------------------------------------------===//
149 //===----------------------------------------------------------------------===//
151 // These are target-independent nodes, but have target-specific formats.
152 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
153 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
154 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd,
155 [SDNPHasChain, SDNPSideEffect, SDNPOptInGlue,
157 def global_offset_table : SDNode<"ISD::GLOBAL_OFFSET_TABLE", SDTPtrLeaf>;
159 // Nodes for SystemZISD::*. See SystemZISelLowering.h for more details.
160 def z_retflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
161 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
162 def z_call : SDNode<"SystemZISD::CALL", SDT_ZCall,
163 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
165 def z_sibcall : SDNode<"SystemZISD::SIBCALL", SDT_ZCall,
166 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
168 def z_tls_gdcall : SDNode<"SystemZISD::TLS_GDCALL", SDT_ZCall,
169 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
171 def z_tls_ldcall : SDNode<"SystemZISD::TLS_LDCALL", SDT_ZCall,
172 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
174 def z_pcrel_wrapper : SDNode<"SystemZISD::PCREL_WRAPPER", SDT_ZWrapPtr, []>;
175 def z_pcrel_offset : SDNode<"SystemZISD::PCREL_OFFSET",
176 SDT_ZWrapOffset, []>;
177 def z_iabs : SDNode<"SystemZISD::IABS", SDTIntUnaryOp, []>;
178 def z_icmp : SDNode<"SystemZISD::ICMP", SDT_ZICmp, [SDNPOutGlue]>;
179 def z_fcmp : SDNode<"SystemZISD::FCMP", SDT_ZCmp, [SDNPOutGlue]>;
180 def z_tm : SDNode<"SystemZISD::TM", SDT_ZICmp, [SDNPOutGlue]>;
181 def z_br_ccmask : SDNode<"SystemZISD::BR_CCMASK", SDT_ZBRCCMask,
182 [SDNPHasChain, SDNPInGlue]>;
183 def z_select_ccmask : SDNode<"SystemZISD::SELECT_CCMASK", SDT_ZSelectCCMask,
185 def z_adjdynalloc : SDNode<"SystemZISD::ADJDYNALLOC", SDT_ZAdjDynAlloc>;
186 def z_popcnt : SDNode<"SystemZISD::POPCNT", SDTIntUnaryOp>;
187 def z_umul_lohi64 : SDNode<"SystemZISD::UMUL_LOHI64", SDT_ZGR128Binary64>;
188 def z_sdivrem32 : SDNode<"SystemZISD::SDIVREM32", SDT_ZGR128Binary32>;
189 def z_sdivrem64 : SDNode<"SystemZISD::SDIVREM64", SDT_ZGR128Binary64>;
190 def z_udivrem32 : SDNode<"SystemZISD::UDIVREM32", SDT_ZGR128Binary32>;
191 def z_udivrem64 : SDNode<"SystemZISD::UDIVREM64", SDT_ZGR128Binary64>;
193 def z_serialize : SDNode<"SystemZISD::SERIALIZE", SDTNone,
194 [SDNPHasChain, SDNPMayStore]>;
195 def z_membarrier : SDNode<"SystemZISD::MEMBARRIER", SDTNone,
196 [SDNPHasChain, SDNPSideEffect]>;
198 def z_loadbswap : SDNode<"SystemZISD::LRV", SDT_ZLoadBSwap,
199 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
200 def z_storebswap : SDNode<"SystemZISD::STRV", SDT_ZStoreBSwap,
201 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
203 def z_tdc : SDNode<"SystemZISD::TDC", SDT_ZTest, [SDNPOutGlue]>;
205 // Defined because the index is an i32 rather than a pointer.
206 def z_vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
207 SDT_ZInsertVectorElt>;
208 def z_vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
209 SDT_ZExtractVectorElt>;
210 def z_byte_mask : SDNode<"SystemZISD::BYTE_MASK", SDT_ZReplicate>;
211 def z_rotate_mask : SDNode<"SystemZISD::ROTATE_MASK", SDT_ZRotateMask>;
212 def z_replicate : SDNode<"SystemZISD::REPLICATE", SDT_ZReplicate>;
213 def z_join_dwords : SDNode<"SystemZISD::JOIN_DWORDS", SDT_ZJoinDwords>;
214 def z_splat : SDNode<"SystemZISD::SPLAT", SDT_ZVecBinaryInt>;
215 def z_merge_high : SDNode<"SystemZISD::MERGE_HIGH", SDT_ZVecBinary>;
216 def z_merge_low : SDNode<"SystemZISD::MERGE_LOW", SDT_ZVecBinary>;
217 def z_shl_double : SDNode<"SystemZISD::SHL_DOUBLE", SDT_ZVecTernaryInt>;
218 def z_permute_dwords : SDNode<"SystemZISD::PERMUTE_DWORDS",
220 def z_permute : SDNode<"SystemZISD::PERMUTE", SDT_ZVecTernary>;
221 def z_pack : SDNode<"SystemZISD::PACK", SDT_ZVecBinaryConv>;
222 def z_packs_cc : SDNode<"SystemZISD::PACKS_CC", SDT_ZVecBinaryConv,
224 def z_packls_cc : SDNode<"SystemZISD::PACKLS_CC", SDT_ZVecBinaryConv,
226 def z_unpack_high : SDNode<"SystemZISD::UNPACK_HIGH", SDT_ZVecUnaryConv>;
227 def z_unpackl_high : SDNode<"SystemZISD::UNPACKL_HIGH", SDT_ZVecUnaryConv>;
228 def z_unpack_low : SDNode<"SystemZISD::UNPACK_LOW", SDT_ZVecUnaryConv>;
229 def z_unpackl_low : SDNode<"SystemZISD::UNPACKL_LOW", SDT_ZVecUnaryConv>;
230 def z_vshl_by_scalar : SDNode<"SystemZISD::VSHL_BY_SCALAR",
232 def z_vsrl_by_scalar : SDNode<"SystemZISD::VSRL_BY_SCALAR",
234 def z_vsra_by_scalar : SDNode<"SystemZISD::VSRA_BY_SCALAR",
236 def z_vsum : SDNode<"SystemZISD::VSUM", SDT_ZVecBinaryConv>;
237 def z_vicmpe : SDNode<"SystemZISD::VICMPE", SDT_ZVecBinary>;
238 def z_vicmph : SDNode<"SystemZISD::VICMPH", SDT_ZVecBinary>;
239 def z_vicmphl : SDNode<"SystemZISD::VICMPHL", SDT_ZVecBinary>;
240 def z_vicmpes : SDNode<"SystemZISD::VICMPES", SDT_ZVecBinary,
242 def z_vicmphs : SDNode<"SystemZISD::VICMPHS", SDT_ZVecBinary,
244 def z_vicmphls : SDNode<"SystemZISD::VICMPHLS", SDT_ZVecBinary,
246 def z_vfcmpe : SDNode<"SystemZISD::VFCMPE", SDT_ZVecBinaryConv>;
247 def z_vfcmph : SDNode<"SystemZISD::VFCMPH", SDT_ZVecBinaryConv>;
248 def z_vfcmphe : SDNode<"SystemZISD::VFCMPHE", SDT_ZVecBinaryConv>;
249 def z_vfcmpes : SDNode<"SystemZISD::VFCMPES", SDT_ZVecBinaryConv,
251 def z_vfcmphs : SDNode<"SystemZISD::VFCMPHS", SDT_ZVecBinaryConv,
253 def z_vfcmphes : SDNode<"SystemZISD::VFCMPHES", SDT_ZVecBinaryConv,
255 def z_vextend : SDNode<"SystemZISD::VEXTEND", SDT_ZVecUnaryConv>;
256 def z_vround : SDNode<"SystemZISD::VROUND", SDT_ZVecUnaryConv>;
257 def z_vtm : SDNode<"SystemZISD::VTM", SDT_ZCmp, [SDNPOutGlue]>;
258 def z_vfae_cc : SDNode<"SystemZISD::VFAE_CC", SDT_ZVecTernaryInt,
260 def z_vfaez_cc : SDNode<"SystemZISD::VFAEZ_CC", SDT_ZVecTernaryInt,
262 def z_vfee_cc : SDNode<"SystemZISD::VFEE_CC", SDT_ZVecBinary,
264 def z_vfeez_cc : SDNode<"SystemZISD::VFEEZ_CC", SDT_ZVecBinary,
266 def z_vfene_cc : SDNode<"SystemZISD::VFENE_CC", SDT_ZVecBinary,
268 def z_vfenez_cc : SDNode<"SystemZISD::VFENEZ_CC", SDT_ZVecBinary,
270 def z_vistr_cc : SDNode<"SystemZISD::VISTR_CC", SDT_ZVecUnary,
272 def z_vstrc_cc : SDNode<"SystemZISD::VSTRC_CC", SDT_ZVecQuaternaryInt,
274 def z_vstrcz_cc : SDNode<"SystemZISD::VSTRCZ_CC",
275 SDT_ZVecQuaternaryInt, [SDNPOutGlue]>;
276 def z_vftci : SDNode<"SystemZISD::VFTCI", SDT_ZVecBinaryConvInt,
279 class AtomicWOp<string name, SDTypeProfile profile = SDT_ZAtomicLoadBinaryW>
280 : SDNode<"SystemZISD::"##name, profile,
281 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
283 def z_atomic_swapw : AtomicWOp<"ATOMIC_SWAPW">;
284 def z_atomic_loadw_add : AtomicWOp<"ATOMIC_LOADW_ADD">;
285 def z_atomic_loadw_sub : AtomicWOp<"ATOMIC_LOADW_SUB">;
286 def z_atomic_loadw_and : AtomicWOp<"ATOMIC_LOADW_AND">;
287 def z_atomic_loadw_or : AtomicWOp<"ATOMIC_LOADW_OR">;
288 def z_atomic_loadw_xor : AtomicWOp<"ATOMIC_LOADW_XOR">;
289 def z_atomic_loadw_nand : AtomicWOp<"ATOMIC_LOADW_NAND">;
290 def z_atomic_loadw_min : AtomicWOp<"ATOMIC_LOADW_MIN">;
291 def z_atomic_loadw_max : AtomicWOp<"ATOMIC_LOADW_MAX">;
292 def z_atomic_loadw_umin : AtomicWOp<"ATOMIC_LOADW_UMIN">;
293 def z_atomic_loadw_umax : AtomicWOp<"ATOMIC_LOADW_UMAX">;
294 def z_atomic_cmp_swapw : AtomicWOp<"ATOMIC_CMP_SWAPW", SDT_ZAtomicCmpSwapW>;
296 def z_mvc : SDNode<"SystemZISD::MVC", SDT_ZMemMemLength,
297 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
298 def z_mvc_loop : SDNode<"SystemZISD::MVC_LOOP", SDT_ZMemMemLoop,
299 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
300 def z_nc : SDNode<"SystemZISD::NC", SDT_ZMemMemLength,
301 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
302 def z_nc_loop : SDNode<"SystemZISD::NC_LOOP", SDT_ZMemMemLoop,
303 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
304 def z_oc : SDNode<"SystemZISD::OC", SDT_ZMemMemLength,
305 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
306 def z_oc_loop : SDNode<"SystemZISD::OC_LOOP", SDT_ZMemMemLoop,
307 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
308 def z_xc : SDNode<"SystemZISD::XC", SDT_ZMemMemLength,
309 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
310 def z_xc_loop : SDNode<"SystemZISD::XC_LOOP", SDT_ZMemMemLoop,
311 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
312 def z_clc : SDNode<"SystemZISD::CLC", SDT_ZMemMemLength,
313 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
314 def z_clc_loop : SDNode<"SystemZISD::CLC_LOOP", SDT_ZMemMemLoop,
315 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
316 def z_strcmp : SDNode<"SystemZISD::STRCMP", SDT_ZString,
317 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
318 def z_stpcpy : SDNode<"SystemZISD::STPCPY", SDT_ZString,
319 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
320 def z_search_string : SDNode<"SystemZISD::SEARCH_STRING", SDT_ZString,
321 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
322 def z_ipm : SDNode<"SystemZISD::IPM", SDT_ZI32Intrinsic,
324 def z_prefetch : SDNode<"SystemZISD::PREFETCH", SDT_ZPrefetch,
325 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
328 def z_tbegin : SDNode<"SystemZISD::TBEGIN", SDT_ZTBegin,
329 [SDNPHasChain, SDNPOutGlue, SDNPMayStore,
331 def z_tbegin_nofloat : SDNode<"SystemZISD::TBEGIN_NOFLOAT", SDT_ZTBegin,
332 [SDNPHasChain, SDNPOutGlue, SDNPMayStore,
334 def z_tend : SDNode<"SystemZISD::TEND", SDTNone,
335 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
337 def z_vshl : SDNode<"ISD::SHL", SDT_ZVecBinary>;
338 def z_vsra : SDNode<"ISD::SRA", SDT_ZVecBinary>;
339 def z_vsrl : SDNode<"ISD::SRL", SDT_ZVecBinary>;
341 //===----------------------------------------------------------------------===//
343 //===----------------------------------------------------------------------===//
345 def z_lrvh : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i16)>;
346 def z_lrv : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i32)>;
347 def z_lrvg : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i64)>;
349 def z_strvh : PatFrag<(ops node:$src, node:$addr),
350 (z_storebswap node:$src, node:$addr, i16)>;
351 def z_strv : PatFrag<(ops node:$src, node:$addr),
352 (z_storebswap node:$src, node:$addr, i32)>;
353 def z_strvg : PatFrag<(ops node:$src, node:$addr),
354 (z_storebswap node:$src, node:$addr, i64)>;
356 // Signed and unsigned comparisons.
357 def z_scmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{
358 unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
359 return Type != SystemZICMP::UnsignedOnly;
361 def z_ucmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{
362 unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
363 return Type != SystemZICMP::SignedOnly;
366 // Register- and memory-based TEST UNDER MASK.
367 def z_tm_reg : PatFrag<(ops node:$a, node:$b), (z_tm node:$a, node:$b, imm)>;
368 def z_tm_mem : PatFrag<(ops node:$a, node:$b), (z_tm node:$a, node:$b, 0)>;
370 // Register sign-extend operations. Sub-32-bit values are represented as i32s.
371 def sext8 : PatFrag<(ops node:$src), (sext_inreg node:$src, i8)>;
372 def sext16 : PatFrag<(ops node:$src), (sext_inreg node:$src, i16)>;
373 def sext32 : PatFrag<(ops node:$src), (sext (i32 node:$src))>;
375 // Match extensions of an i32 to an i64, followed by an in-register sign
376 // extension from a sub-i32 value.
377 def sext8dbl : PatFrag<(ops node:$src), (sext8 (anyext node:$src))>;
378 def sext16dbl : PatFrag<(ops node:$src), (sext16 (anyext node:$src))>;
380 // Register zero-extend operations. Sub-32-bit values are represented as i32s.
381 def zext8 : PatFrag<(ops node:$src), (and node:$src, 0xff)>;
382 def zext16 : PatFrag<(ops node:$src), (and node:$src, 0xffff)>;
383 def zext32 : PatFrag<(ops node:$src), (zext (i32 node:$src))>;
385 // Extending loads in which the extension type can be signed.
386 def asextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
387 unsigned Type = cast<LoadSDNode>(N)->getExtensionType();
388 return Type == ISD::EXTLOAD || Type == ISD::SEXTLOAD;
390 def asextloadi8 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{
391 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
393 def asextloadi16 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{
394 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
396 def asextloadi32 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{
397 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
400 // Extending loads in which the extension type can be unsigned.
401 def azextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
402 unsigned Type = cast<LoadSDNode>(N)->getExtensionType();
403 return Type == ISD::EXTLOAD || Type == ISD::ZEXTLOAD;
405 def azextloadi8 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{
406 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
408 def azextloadi16 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{
409 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
411 def azextloadi32 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{
412 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
415 // Extending loads in which the extension type doesn't matter.
416 def anyextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
417 return cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD;
419 def anyextloadi8 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{
420 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
422 def anyextloadi16 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{
423 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
425 def anyextloadi32 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{
426 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
430 class AlignedLoad<SDPatternOperator load>
431 : PatFrag<(ops node:$addr), (load node:$addr), [{
432 auto *Load = cast<LoadSDNode>(N);
433 return Load->getAlignment() >= Load->getMemoryVT().getStoreSize();
435 def aligned_load : AlignedLoad<load>;
436 def aligned_asextloadi16 : AlignedLoad<asextloadi16>;
437 def aligned_asextloadi32 : AlignedLoad<asextloadi32>;
438 def aligned_azextloadi16 : AlignedLoad<azextloadi16>;
439 def aligned_azextloadi32 : AlignedLoad<azextloadi32>;
442 class AlignedStore<SDPatternOperator store>
443 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{
444 auto *Store = cast<StoreSDNode>(N);
445 return Store->getAlignment() >= Store->getMemoryVT().getStoreSize();
447 def aligned_store : AlignedStore<store>;
448 def aligned_truncstorei16 : AlignedStore<truncstorei16>;
449 def aligned_truncstorei32 : AlignedStore<truncstorei32>;
451 // Non-volatile loads. Used for instructions that might access the storage
452 // location multiple times.
453 class NonvolatileLoad<SDPatternOperator load>
454 : PatFrag<(ops node:$addr), (load node:$addr), [{
455 auto *Load = cast<LoadSDNode>(N);
456 return !Load->isVolatile();
458 def nonvolatile_load : NonvolatileLoad<load>;
459 def nonvolatile_anyextloadi8 : NonvolatileLoad<anyextloadi8>;
460 def nonvolatile_anyextloadi16 : NonvolatileLoad<anyextloadi16>;
461 def nonvolatile_anyextloadi32 : NonvolatileLoad<anyextloadi32>;
463 // Non-volatile stores.
464 class NonvolatileStore<SDPatternOperator store>
465 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{
466 auto *Store = cast<StoreSDNode>(N);
467 return !Store->isVolatile();
469 def nonvolatile_store : NonvolatileStore<store>;
470 def nonvolatile_truncstorei8 : NonvolatileStore<truncstorei8>;
471 def nonvolatile_truncstorei16 : NonvolatileStore<truncstorei16>;
472 def nonvolatile_truncstorei32 : NonvolatileStore<truncstorei32>;
474 // A store of a load that can be implemented using MVC.
475 def mvc_store : PatFrag<(ops node:$value, node:$addr),
476 (unindexedstore node:$value, node:$addr),
477 [{ return storeLoadCanUseMVC(N); }]>;
479 // Binary read-modify-write operations on memory in which the other
480 // operand is also memory and for which block operations like NC can
481 // be used. There are two patterns for each operator, depending on
482 // which operand contains the "other" load.
483 multiclass block_op<SDPatternOperator operator> {
484 def "1" : PatFrag<(ops node:$value, node:$addr),
485 (unindexedstore (operator node:$value,
486 (unindexedload node:$addr)),
488 [{ return storeLoadCanUseBlockBinary(N, 0); }]>;
489 def "2" : PatFrag<(ops node:$value, node:$addr),
490 (unindexedstore (operator (unindexedload node:$addr),
493 [{ return storeLoadCanUseBlockBinary(N, 1); }]>;
495 defm block_and : block_op<and>;
496 defm block_or : block_op<or>;
497 defm block_xor : block_op<xor>;
500 def inserti8 : PatFrag<(ops node:$src1, node:$src2),
501 (or (and node:$src1, -256), node:$src2)>;
502 def insertll : PatFrag<(ops node:$src1, node:$src2),
503 (or (and node:$src1, 0xffffffffffff0000), node:$src2)>;
504 def insertlh : PatFrag<(ops node:$src1, node:$src2),
505 (or (and node:$src1, 0xffffffff0000ffff), node:$src2)>;
506 def inserthl : PatFrag<(ops node:$src1, node:$src2),
507 (or (and node:$src1, 0xffff0000ffffffff), node:$src2)>;
508 def inserthh : PatFrag<(ops node:$src1, node:$src2),
509 (or (and node:$src1, 0x0000ffffffffffff), node:$src2)>;
510 def insertlf : PatFrag<(ops node:$src1, node:$src2),
511 (or (and node:$src1, 0xffffffff00000000), node:$src2)>;
512 def inserthf : PatFrag<(ops node:$src1, node:$src2),
513 (or (and node:$src1, 0x00000000ffffffff), node:$src2)>;
515 // ORs that can be treated as insertions.
516 def or_as_inserti8 : PatFrag<(ops node:$src1, node:$src2),
517 (or node:$src1, node:$src2), [{
518 unsigned BitWidth = N->getValueType(0).getScalarSizeInBits();
519 return CurDAG->MaskedValueIsZero(N->getOperand(0),
520 APInt::getLowBitsSet(BitWidth, 8));
523 // ORs that can be treated as reversed insertions.
524 def or_as_revinserti8 : PatFrag<(ops node:$src1, node:$src2),
525 (or node:$src1, node:$src2), [{
526 unsigned BitWidth = N->getValueType(0).getScalarSizeInBits();
527 return CurDAG->MaskedValueIsZero(N->getOperand(1),
528 APInt::getLowBitsSet(BitWidth, 8));
531 // Negative integer absolute.
532 def z_inegabs : PatFrag<(ops node:$src), (ineg (z_iabs node:$src))>;
534 // Integer absolute, matching the canonical form generated by DAGCombiner.
535 def z_iabs32 : PatFrag<(ops node:$src),
536 (xor (add node:$src, (sra node:$src, (i32 31))),
537 (sra node:$src, (i32 31)))>;
538 def z_iabs64 : PatFrag<(ops node:$src),
539 (xor (add node:$src, (sra node:$src, (i32 63))),
540 (sra node:$src, (i32 63)))>;
541 def z_inegabs32 : PatFrag<(ops node:$src), (ineg (z_iabs32 node:$src))>;
542 def z_inegabs64 : PatFrag<(ops node:$src), (ineg (z_iabs64 node:$src))>;
544 // Integer multiply-and-add
545 def z_muladd : PatFrag<(ops node:$src1, node:$src2, node:$src3),
546 (add (mul node:$src1, node:$src2), node:$src3)>;
548 // Fused multiply-subtract, using the natural operand order.
549 def fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
550 (fma node:$src1, node:$src2, (fneg node:$src3))>;
552 // Fused multiply-add and multiply-subtract, but with the order of the
553 // operands matching SystemZ's MA and MS instructions.
554 def z_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3),
555 (fma node:$src2, node:$src3, node:$src1)>;
556 def z_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
557 (fma node:$src2, node:$src3, (fneg node:$src1))>;
559 // Floating-point negative absolute.
560 def fnabs : PatFrag<(ops node:$ptr), (fneg (fabs node:$ptr))>;
562 // Create a unary operator that loads from memory and then performs
563 // the given operation on it.
564 class loadu<SDPatternOperator operator, SDPatternOperator load = load>
565 : PatFrag<(ops node:$addr), (operator (load node:$addr))>;
567 // Create a store operator that performs the given unary operation
568 // on the value before storing it.
569 class storeu<SDPatternOperator operator, SDPatternOperator store = store>
570 : PatFrag<(ops node:$value, node:$addr),
571 (store (operator node:$value), node:$addr)>;
573 // Create a store operator that performs the given inherent operation
574 // and stores the resulting value.
575 class storei<SDPatternOperator operator, SDPatternOperator store = store>
576 : PatFrag<(ops node:$addr),
577 (store (operator), node:$addr)>;
579 // Vector representation of all-zeros and all-ones.
580 def z_vzero : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 0))))>;
581 def z_vones : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 65535))))>;
583 // Load a scalar and replicate it in all elements of a vector.
584 class z_replicate_load<ValueType scalartype, SDPatternOperator load>
585 : PatFrag<(ops node:$addr),
586 (z_replicate (scalartype (load node:$addr)))>;
587 def z_replicate_loadi8 : z_replicate_load<i32, anyextloadi8>;
588 def z_replicate_loadi16 : z_replicate_load<i32, anyextloadi16>;
589 def z_replicate_loadi32 : z_replicate_load<i32, load>;
590 def z_replicate_loadi64 : z_replicate_load<i64, load>;
591 def z_replicate_loadf32 : z_replicate_load<f32, load>;
592 def z_replicate_loadf64 : z_replicate_load<f64, load>;
594 // Load a scalar and insert it into a single element of a vector.
595 class z_vle<ValueType scalartype, SDPatternOperator load>
596 : PatFrag<(ops node:$vec, node:$addr, node:$index),
597 (z_vector_insert node:$vec, (scalartype (load node:$addr)),
599 def z_vlei8 : z_vle<i32, anyextloadi8>;
600 def z_vlei16 : z_vle<i32, anyextloadi16>;
601 def z_vlei32 : z_vle<i32, load>;
602 def z_vlei64 : z_vle<i64, load>;
603 def z_vlef32 : z_vle<f32, load>;
604 def z_vlef64 : z_vle<f64, load>;
606 // Load a scalar and insert it into the low element of the high i64 of a
608 class z_vllez<ValueType scalartype, SDPatternOperator load, int index>
609 : PatFrag<(ops node:$addr),
610 (z_vector_insert (z_vzero),
611 (scalartype (load node:$addr)), (i32 index))>;
612 def z_vllezi8 : z_vllez<i32, anyextloadi8, 7>;
613 def z_vllezi16 : z_vllez<i32, anyextloadi16, 3>;
614 def z_vllezi32 : z_vllez<i32, load, 1>;
615 def z_vllezi64 : PatFrag<(ops node:$addr),
616 (z_join_dwords (i64 (load node:$addr)), (i64 0))>;
617 // We use high merges to form a v4f32 from four f32s. Propagating zero
618 // into all elements but index 1 gives this expression.
619 def z_vllezf32 : PatFrag<(ops node:$addr),
626 (v4f32 (scalar_to_vector
627 (f32 (load node:$addr)))))))),
628 (v2i64 (z_vzero))))>;
629 def z_vllezf64 : PatFrag<(ops node:$addr),
631 (scalar_to_vector (f64 (load node:$addr))),
634 // Store one element of a vector.
635 class z_vste<ValueType scalartype, SDPatternOperator store>
636 : PatFrag<(ops node:$vec, node:$addr, node:$index),
637 (store (scalartype (z_vector_extract node:$vec, node:$index)),
639 def z_vstei8 : z_vste<i32, truncstorei8>;
640 def z_vstei16 : z_vste<i32, truncstorei16>;
641 def z_vstei32 : z_vste<i32, store>;
642 def z_vstei64 : z_vste<i64, store>;
643 def z_vstef32 : z_vste<f32, store>;
644 def z_vstef64 : z_vste<f64, store>;
646 // Arithmetic negation on vectors.
647 def z_vneg : PatFrag<(ops node:$x), (sub (z_vzero), node:$x)>;
649 // Bitwise negation on vectors.
650 def z_vnot : PatFrag<(ops node:$x), (xor node:$x, (z_vones))>;
652 // Signed "integer greater than zero" on vectors.
653 def z_vicmph_zero : PatFrag<(ops node:$x), (z_vicmph node:$x, (z_vzero))>;
655 // Signed "integer less than zero" on vectors.
656 def z_vicmpl_zero : PatFrag<(ops node:$x), (z_vicmph (z_vzero), node:$x)>;
658 // Integer absolute on vectors.
659 class z_viabs<int shift>
660 : PatFrag<(ops node:$src),
661 (xor (add node:$src, (z_vsra_by_scalar node:$src, (i32 shift))),
662 (z_vsra_by_scalar node:$src, (i32 shift)))>;
663 def z_viabs8 : z_viabs<7>;
664 def z_viabs16 : z_viabs<15>;
665 def z_viabs32 : z_viabs<31>;
666 def z_viabs64 : z_viabs<63>;
668 // Sign-extend the i64 elements of a vector.
669 class z_vse<int shift>
670 : PatFrag<(ops node:$src),
671 (z_vsra_by_scalar (z_vshl_by_scalar node:$src, shift), shift)>;
672 def z_vsei8 : z_vse<56>;
673 def z_vsei16 : z_vse<48>;
674 def z_vsei32 : z_vse<32>;
676 // ...and again with the extensions being done on individual i64 scalars.
677 class z_vse_by_parts<SDPatternOperator operator, int index1, int index2>
678 : PatFrag<(ops node:$src),
680 (operator (z_vector_extract node:$src, index1)),
681 (operator (z_vector_extract node:$src, index2)))>;
682 def z_vsei8_by_parts : z_vse_by_parts<sext8dbl, 7, 15>;
683 def z_vsei16_by_parts : z_vse_by_parts<sext16dbl, 3, 7>;
684 def z_vsei32_by_parts : z_vse_by_parts<sext32, 1, 3>;