1 //===-- SystemZRegisterInfo.h - SystemZ register information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZREGISTERINFO_H
11 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZREGISTERINFO_H
14 #include "llvm/CodeGen/TargetRegisterInfo.h"
16 #define GET_REGINFO_HEADER
17 #include "SystemZGenRegisterInfo.inc"
24 // Return the subreg to use for referring to the even and odd registers
25 // in a GR128 pair. Is32Bit says whether we want a GR32 or GR64.
26 inline unsigned even128(bool Is32bit) {
27 return Is32bit ? subreg_hl32 : subreg_h64;
29 inline unsigned odd128(bool Is32bit) {
30 return Is32bit ? subreg_l32 : subreg_l64;
32 } // end namespace SystemZ
34 struct SystemZRegisterInfo : public SystemZGenRegisterInfo {
36 SystemZRegisterInfo();
38 /// getPointerRegClass - Return the register class to use to hold pointers.
39 /// This is currently only used by LOAD_STACK_GUARD, which requires a non-%r0
40 /// register, hence ADDR64.
41 const TargetRegisterClass *
42 getPointerRegClass(const MachineFunction &MF,
43 unsigned Kind=0) const override {
44 return &SystemZ::ADDR64BitRegClass;
47 /// getCrossCopyRegClass - Returns a legal register class to copy a register
48 /// in the specified class to or from. Returns NULL if it is possible to copy
49 /// between a two registers of the specified class.
50 const TargetRegisterClass *
51 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
53 bool getRegAllocationHints(unsigned VirtReg,
54 ArrayRef<MCPhysReg> Order,
55 SmallVectorImpl<MCPhysReg> &Hints,
56 const MachineFunction &MF,
57 const VirtRegMap *VRM,
58 const LiveRegMatrix *Matrix) const override;
60 // Override TargetRegisterInfo.h.
61 bool requiresRegisterScavenging(const MachineFunction &MF) const override {
64 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
67 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
70 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
71 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
72 CallingConv::ID CC) const override;
73 BitVector getReservedRegs(const MachineFunction &MF) const override;
74 void eliminateFrameIndex(MachineBasicBlock::iterator MI,
75 int SPAdj, unsigned FIOperandNum,
76 RegScavenger *RS) const override;
78 /// SrcRC and DstRC will be morphed into NewRC if this returns true.
79 bool shouldCoalesce(MachineInstr *MI,
80 const TargetRegisterClass *SrcRC,
82 const TargetRegisterClass *DstRC,
84 const TargetRegisterClass *NewRC,
85 LiveIntervals &LIS) const override;
87 unsigned getFrameRegister(const MachineFunction &MF) const override;
90 } // end namespace llvm