1 //==- SystemZRegisterInfo.td - SystemZ register definitions -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 class SystemZReg<string n> : Register<n> {
15 let Namespace = "SystemZ";
18 class SystemZRegWithSubregs<string n, list<Register> subregs>
19 : RegisterWithSubRegs<n, subregs> {
20 let Namespace = "SystemZ";
23 let Namespace = "SystemZ" in {
24 def subreg_l32 : SubRegIndex<32, 0>; // Also acts as subreg_ll32.
25 def subreg_h32 : SubRegIndex<32, 32>; // Also acts as subreg_lh32.
26 def subreg_l64 : SubRegIndex<64, 0>;
27 def subreg_h64 : SubRegIndex<64, 64>;
28 def subreg_r32 : SubRegIndex<32, 32>; // Reinterpret a wider reg as 32 bits.
29 def subreg_r64 : SubRegIndex<64, 64>; // Reinterpret a wider reg as 64 bits.
30 def subreg_hh32 : ComposedSubRegIndex<subreg_h64, subreg_h32>;
31 def subreg_hl32 : ComposedSubRegIndex<subreg_h64, subreg_l32>;
32 def subreg_hr32 : ComposedSubRegIndex<subreg_h64, subreg_r32>;
35 // Define a register class that contains values of types TYPES and an
36 // associated operand called NAME. SIZE is the size and alignment
37 // of the registers and REGLIST is the list of individual registers.
38 multiclass SystemZRegClass<string name, list<ValueType> types, int size,
39 dag regList, bit allocatable = 1> {
40 def AsmOperand : AsmOperandClass {
42 let ParserMethod = "parse"##name;
43 let RenderMethod = "addRegOperands";
45 let isAllocatable = allocatable in
46 def Bit : RegisterClass<"SystemZ", types, size, regList> {
49 def "" : RegisterOperand<!cast<RegisterClass>(name##"Bit")> {
50 let ParserMatchClass = !cast<AsmOperandClass>(name##"AsmOperand");
54 //===----------------------------------------------------------------------===//
55 // General-purpose registers
56 //===----------------------------------------------------------------------===//
58 // Lower 32 bits of one of the 16 64-bit general-purpose registers
59 class GPR32<bits<16> num, string n> : SystemZReg<n> {
63 // One of the 16 64-bit general-purpose registers.
64 class GPR64<bits<16> num, string n, GPR32 low, GPR32 high>
65 : SystemZRegWithSubregs<n, [low, high]> {
67 let SubRegIndices = [subreg_l32, subreg_h32];
70 // 8 even-odd pairs of GPR64s.
71 class GPR128<bits<16> num, string n, GPR64 low, GPR64 high>
72 : SystemZRegWithSubregs<n, [low, high]> {
74 let SubRegIndices = [subreg_l64, subreg_h64];
77 // General-purpose registers
79 def R#I#L : GPR32<I, "r"#I>;
80 def R#I#H : GPR32<I, "r"#I>;
81 def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"L"), !cast<GPR32>("R"#I#"H")>,
85 foreach I = [0, 2, 4, 6, 8, 10, 12, 14] in {
86 def R#I#Q : GPR128<I, "r"#I, !cast<GPR64>("R"#!add(I, 1)#"D"),
87 !cast<GPR64>("R"#I#"D")>;
90 /// Allocate the callee-saved R6-R13 backwards. That way they can be saved
91 /// together with R14 and R15 in one prolog instruction.
92 defm GR32 : SystemZRegClass<"GR32", [i32], 32,
93 (add (sequence "R%uL", 0, 5),
94 (sequence "R%uL", 15, 6))>;
95 defm GRH32 : SystemZRegClass<"GRH32", [i32], 32,
96 (add (sequence "R%uH", 0, 5),
97 (sequence "R%uH", 15, 6))>;
98 defm GR64 : SystemZRegClass<"GR64", [i64], 64,
99 (add (sequence "R%uD", 0, 5),
100 (sequence "R%uD", 15, 6))>;
102 // Combine the low and high GR32s into a single class. This can only be
103 // used for virtual registers if the high-word facility is available.
104 defm GRX32 : SystemZRegClass<"GRX32", [i32], 32,
105 (add (sequence "R%uL", 0, 5),
106 (sequence "R%uH", 0, 5),
107 R15L, R15H, R14L, R14H, R13L, R13H,
108 R12L, R12H, R11L, R11H, R10L, R10H,
109 R9L, R9H, R8L, R8H, R7L, R7H, R6L, R6H)>;
111 // The architecture doesn't really have any i128 support, so model the
112 // register pairs as untyped instead.
113 defm GR128 : SystemZRegClass<"GR128", [untyped], 128,
114 (add R0Q, R2Q, R4Q, R12Q, R10Q, R8Q, R6Q, R14Q)>;
116 // Base and index registers. Everything except R0, which in an address
117 // context evaluates as 0.
118 defm ADDR32 : SystemZRegClass<"ADDR32", [i32], 32, (sub GR32Bit, R0L)>;
119 defm ADDR64 : SystemZRegClass<"ADDR64", [i64], 64, (sub GR64Bit, R0D)>;
121 // Not used directly, but needs to exist for ADDR32 and ADDR64 subregs
123 defm ADDR128 : SystemZRegClass<"ADDR128", [untyped], 128, (sub GR128Bit, R0Q)>;
125 // Any type register. Used for .insn directives when we don't know what the
126 // register types could be.
127 defm AnyReg : SystemZRegClass<"AnyReg",
128 [i64, f64, v8i8, v4i16, v2i32, v2f32], 64,
129 (add (sequence "R%uD", 0, 15),
130 (sequence "F%uD", 0, 15),
131 (sequence "V%u", 0, 15))>;
133 //===----------------------------------------------------------------------===//
134 // Floating-point registers
135 //===----------------------------------------------------------------------===//
137 // Maps FPR register numbers to their DWARF encoding.
138 class DwarfMapping<int id> { int Id = id; }
140 def F0Dwarf : DwarfMapping<16>;
141 def F2Dwarf : DwarfMapping<17>;
142 def F4Dwarf : DwarfMapping<18>;
143 def F6Dwarf : DwarfMapping<19>;
145 def F1Dwarf : DwarfMapping<20>;
146 def F3Dwarf : DwarfMapping<21>;
147 def F5Dwarf : DwarfMapping<22>;
148 def F7Dwarf : DwarfMapping<23>;
150 def F8Dwarf : DwarfMapping<24>;
151 def F10Dwarf : DwarfMapping<25>;
152 def F12Dwarf : DwarfMapping<26>;
153 def F14Dwarf : DwarfMapping<27>;
155 def F9Dwarf : DwarfMapping<28>;
156 def F11Dwarf : DwarfMapping<29>;
157 def F13Dwarf : DwarfMapping<30>;
158 def F15Dwarf : DwarfMapping<31>;
160 def F16Dwarf : DwarfMapping<68>;
161 def F18Dwarf : DwarfMapping<69>;
162 def F20Dwarf : DwarfMapping<70>;
163 def F22Dwarf : DwarfMapping<71>;
165 def F17Dwarf : DwarfMapping<72>;
166 def F19Dwarf : DwarfMapping<73>;
167 def F21Dwarf : DwarfMapping<74>;
168 def F23Dwarf : DwarfMapping<75>;
170 def F24Dwarf : DwarfMapping<76>;
171 def F26Dwarf : DwarfMapping<77>;
172 def F28Dwarf : DwarfMapping<78>;
173 def F30Dwarf : DwarfMapping<79>;
175 def F25Dwarf : DwarfMapping<80>;
176 def F27Dwarf : DwarfMapping<81>;
177 def F29Dwarf : DwarfMapping<82>;
178 def F31Dwarf : DwarfMapping<83>;
180 // Upper 32 bits of one of the floating-point registers
181 class FPR32<bits<16> num, string n> : SystemZReg<n> {
182 let HWEncoding = num;
185 // One of the floating-point registers.
186 class FPR64<bits<16> num, string n, FPR32 high>
187 : SystemZRegWithSubregs<n, [high]> {
188 let HWEncoding = num;
189 let SubRegIndices = [subreg_r32];
192 // 8 pairs of FPR64s, with a one-register gap inbetween.
193 class FPR128<bits<16> num, string n, FPR64 low, FPR64 high>
194 : SystemZRegWithSubregs<n, [low, high]> {
195 let HWEncoding = num;
196 let SubRegIndices = [subreg_l64, subreg_h64];
199 // Floating-point registers. Registers 16-31 require the vector facility.
200 foreach I = 0-15 in {
201 def F#I#S : FPR32<I, "f"#I>;
202 def F#I#D : FPR64<I, "f"#I, !cast<FPR32>("F"#I#"S")>,
203 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
205 foreach I = 16-31 in {
206 def F#I#S : FPR32<I, "v"#I>;
207 def F#I#D : FPR64<I, "v"#I, !cast<FPR32>("F"#I#"S")>,
208 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
211 foreach I = [0, 1, 4, 5, 8, 9, 12, 13] in {
212 def F#I#Q : FPR128<I, "f"#I, !cast<FPR64>("F"#!add(I, 2)#"D"),
213 !cast<FPR64>("F"#I#"D")>;
216 // There's no store-multiple instruction for FPRs, so we're not fussy
217 // about the order in which call-saved registers are allocated.
218 defm FP32 : SystemZRegClass<"FP32", [f32], 32, (sequence "F%uS", 0, 15)>;
219 defm FP64 : SystemZRegClass<"FP64", [f64], 64, (sequence "F%uD", 0, 15)>;
220 defm FP128 : SystemZRegClass<"FP128", [f128], 128,
221 (add F0Q, F1Q, F4Q, F5Q, F8Q, F9Q, F12Q, F13Q)>;
223 //===----------------------------------------------------------------------===//
225 //===----------------------------------------------------------------------===//
227 // A full 128-bit vector register, with an FPR64 as its high part.
228 class VR128<bits<16> num, string n, FPR64 high>
229 : SystemZRegWithSubregs<n, [high]> {
230 let HWEncoding = num;
231 let SubRegIndices = [subreg_r64];
234 // Full vector registers.
235 foreach I = 0-31 in {
236 def V#I : VR128<I, "v"#I, !cast<FPR64>("F"#I#"D")>,
237 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
240 // Class used to store 32-bit values in the first element of a vector
241 // register. f32 scalars are used for the WLEDB and WLDEB instructions.
242 defm VR32 : SystemZRegClass<"VR32", [f32, v4i8, v2i16], 32,
243 (add (sequence "F%uS", 0, 7),
244 (sequence "F%uS", 16, 31),
245 (sequence "F%uS", 8, 15))>;
247 // Class used to store 64-bit values in the upper half of a vector register.
248 // The vector facility also includes scalar f64 instructions that operate
249 // on the full vector register set.
250 defm VR64 : SystemZRegClass<"VR64", [f64, v8i8, v4i16, v2i32, v2f32], 64,
251 (add (sequence "F%uD", 0, 7),
252 (sequence "F%uD", 16, 31),
253 (sequence "F%uD", 8, 15))>;
255 // The subset of vector registers that can be used for floating-point
257 defm VF128 : SystemZRegClass<"VF128",
258 [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
259 (sequence "V%u", 0, 15)>;
261 // All vector registers.
262 defm VR128 : SystemZRegClass<"VR128",
263 [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
264 (add (sequence "V%u", 0, 7),
265 (sequence "V%u", 16, 31),
266 (sequence "V%u", 8, 15))>;
268 // Attaches a ValueType to a register operand, to make the instruction
269 // definitions easier.
270 class TypedReg<ValueType vtin, RegisterOperand opin> {
272 RegisterOperand op = opin;
275 def v32eb : TypedReg<f32, VR32>;
276 def v64g : TypedReg<i64, VR64>;
277 def v64db : TypedReg<f64, VR64>;
278 def v128b : TypedReg<v16i8, VR128>;
279 def v128h : TypedReg<v8i16, VR128>;
280 def v128f : TypedReg<v4i32, VR128>;
281 def v128g : TypedReg<v2i64, VR128>;
282 def v128q : TypedReg<v16i8, VR128>;
283 def v128eb : TypedReg<v4f32, VR128>;
284 def v128db : TypedReg<v2f64, VR128>;
285 def v128any : TypedReg<untyped, VR128>;
287 //===----------------------------------------------------------------------===//
289 //===----------------------------------------------------------------------===//
291 // The 2-bit condition code field of the PSW. Every register named in an
292 // inline asm needs a class associated with it.
293 def CC : SystemZReg<"cc">;
294 let isAllocatable = 0 in
295 def CCRegs : RegisterClass<"SystemZ", [i32], 32, (add CC)>;
298 class ACR32<bits<16> num, string n> : SystemZReg<n> {
299 let HWEncoding = num;
301 foreach I = 0-15 in {
302 def A#I : ACR32<I, "a"#I>, DwarfRegNum<[!add(I, 48)]>;
304 defm AR32 : SystemZRegClass<"AR32", [i32], 32,
305 (add (sequence "A%u", 0, 15)), 0>;