1 //==-- SystemZSchedule.td - SystemZ Scheduling Definitions ----*- tblgen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Scheduler resources
12 // These resources are used to express decoder grouping rules. The number of
13 // decoder slots needed by an instructions is normally one, but there are
15 def NormalGr : SchedWrite;
16 def Cracked : SchedWrite;
17 def GroupAlone : SchedWrite;
18 def GroupAlone2 : SchedWrite;
19 def GroupAlone3 : SchedWrite;
20 def BeginGroup : SchedWrite;
21 def EndGroup : SchedWrite;
23 // A SchedWrite added to other SchedWrites to make LSU latency parameterizable.
24 def LSULatency : SchedWrite;
26 // Operand WriteLatencies.
27 foreach L = 1 - 30 in def "WLat"#L : SchedWrite;
30 def "WLat"#L#"LSU" : WriteSequence<[!cast<SchedWrite>("WLat"#L),
33 // ReadAdvances, used for the register operand next to a memory operand,
34 // modelling that the register operand is needed later than the address
36 def RegReadAdv : SchedRead;
38 foreach Num = ["", "2", "3", "4", "5", "6"] in {
40 def "FXa"#Num : SchedWrite;
41 def "FXb"#Num : SchedWrite;
42 def "FXU"#Num : SchedWrite;
44 def "LSU"#Num : SchedWrite;
45 // Vector sub units (z13 and later)
46 def "VecBF"#Num : SchedWrite;
47 def "VecDF"#Num : SchedWrite;
48 def "VecDFX"#Num : SchedWrite;
49 def "VecMul"#Num : SchedWrite;
50 def "VecStr"#Num : SchedWrite;
51 def "VecXsPm"#Num : SchedWrite;
52 // Floating point unit (zEC12 and earlier)
53 def "FPU"#Num : SchedWrite;
54 def "DFU"#Num : SchedWrite;
57 def VecFPd : SchedWrite; // Blocking BFP div/sqrt unit.
59 def VBU : SchedWrite; // Virtual branching unit
61 def MCD : SchedWrite; // Millicode
63 include "SystemZScheduleZ14.td"
64 include "SystemZScheduleZ13.td"
65 include "SystemZScheduleZEC12.td"
66 include "SystemZScheduleZ196.td"