1 //==-- SystemZSchedule.td - SystemZ Scheduling Definitions ----*- tblgen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Scheduler resources
11 // Resources ending with a '2' use that resource for 2 cycles. An instruction
12 // using two such resources use the mapped unit for 4 cycles, and 2 is added
13 // to the total number of uops of the sched class.
15 // These three resources are used to express decoder grouping rules.
16 // The number of decoder slots needed by an instructions is normally
17 // one. For a cracked instruction (BeginGroup && !EndGroup) it is
18 // two. Expanded instructions (BeginGroup && EndGroup) group alone.
19 def GroupAlone : SchedWrite;
20 def BeginGroup : SchedWrite;
21 def EndGroup : SchedWrite;
23 // Latencies, to make code a bit neater. If more than one resource is
24 // used for an instruction, the greatest latency (not the sum) will be
25 // output by Tablegen. Therefore, in such cases one of these resources
27 def Lat2 : SchedWrite;
28 def Lat3 : SchedWrite;
29 def Lat4 : SchedWrite;
30 def Lat5 : SchedWrite;
31 def Lat6 : SchedWrite;
32 def Lat7 : SchedWrite;
33 def Lat8 : SchedWrite;
34 def Lat9 : SchedWrite;
35 def Lat10 : SchedWrite;
36 def Lat11 : SchedWrite;
37 def Lat12 : SchedWrite;
38 def Lat15 : SchedWrite;
39 def Lat20 : SchedWrite;
40 def Lat30 : SchedWrite;
44 def FXa2 : SchedWrite;
51 // Model a return without latency, otherwise if-converter will model
52 // extra cost and abort (currently there is an assert that checks that
53 // all instructions have at least one uop).
54 def LSU_lat1 : SchedWrite;
56 // Floating point unit (zEC12 and earlier)
58 def FPU2 : SchedWrite;
60 // Vector sub units (z13)
61 def VecBF : SchedWrite;
62 def VecBF2 : SchedWrite;
63 def VecDF : SchedWrite;
64 def VecDF2 : SchedWrite;
65 def VecFPd : SchedWrite; // Blocking BFP div/sqrt unit.
66 def VecMul : SchedWrite;
67 def VecStr : SchedWrite;
68 def VecXsPm : SchedWrite;
70 // Virtual branching unit
74 include "SystemZScheduleZ13.td"
75 include "SystemZScheduleZEC12.td"
76 include "SystemZScheduleZ196.td"