1 //=- SystemZScheduleZ196.td - SystemZ Scheduling Definitions ---*- tblgen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the machine model for Z196 to support instruction
11 // scheduling and other instruction cost heuristics.
13 //===----------------------------------------------------------------------===//
15 def Z196Model : SchedMachineModel {
17 let UnsupportedFeatures = Arch9UnsupportedFeatures.List;
20 let MicroOpBufferSize = 40; // Issue queues
21 let LoadLatency = 1; // Optimistic load latency.
23 let PostRAScheduler = 1;
25 // Extra cycles for a mispredicted branch.
26 let MispredictPenalty = 16;
29 let SchedModel = Z196Model in {
31 // These definitions could be put in a subtarget common include file,
32 // but it seems the include system in Tablegen currently rejects
33 // multiple includes of same file.
34 def : WriteRes<GroupAlone, []> {
39 def : WriteRes<EndGroup, []> {
43 def : WriteRes<Lat2, []> { let Latency = 2; let NumMicroOps = 0;}
44 def : WriteRes<Lat3, []> { let Latency = 3; let NumMicroOps = 0;}
45 def : WriteRes<Lat4, []> { let Latency = 4; let NumMicroOps = 0;}
46 def : WriteRes<Lat5, []> { let Latency = 5; let NumMicroOps = 0;}
47 def : WriteRes<Lat6, []> { let Latency = 6; let NumMicroOps = 0;}
48 def : WriteRes<Lat7, []> { let Latency = 7; let NumMicroOps = 0;}
49 def : WriteRes<Lat8, []> { let Latency = 8; let NumMicroOps = 0;}
50 def : WriteRes<Lat9, []> { let Latency = 9; let NumMicroOps = 0;}
51 def : WriteRes<Lat10, []> { let Latency = 10; let NumMicroOps = 0;}
52 def : WriteRes<Lat11, []> { let Latency = 11; let NumMicroOps = 0;}
53 def : WriteRes<Lat12, []> { let Latency = 12; let NumMicroOps = 0;}
54 def : WriteRes<Lat15, []> { let Latency = 15; let NumMicroOps = 0;}
55 def : WriteRes<Lat20, []> { let Latency = 20; let NumMicroOps = 0;}
56 def : WriteRes<Lat30, []> { let Latency = 30; let NumMicroOps = 0;}
59 def Z196_FXUnit : ProcResource<2>;
60 def Z196_LSUnit : ProcResource<2>;
61 def Z196_FPUnit : ProcResource<1>;
63 // Subtarget specific definitions of scheduling resources.
64 def : WriteRes<FXU, [Z196_FXUnit]> { let Latency = 1; }
65 def : WriteRes<LSU, [Z196_LSUnit]> { let Latency = 4; }
66 def : WriteRes<LSU_lat1, [Z196_LSUnit]> { let Latency = 1; }
67 def : WriteRes<FPU, [Z196_FPUnit]> { let Latency = 8; }
68 def : WriteRes<FPU2, [Z196_FPUnit, Z196_FPUnit]> { let Latency = 9; }
70 // -------------------------- INSTRUCTIONS ---------------------------------- //
72 // InstRW constructs have been used in order to preserve the
73 // readability of the InstrInfo files.
75 // For each instruction, as matched by a regexp, provide a list of
76 // resources that it needs. These will be combined into a SchedClass.
78 //===----------------------------------------------------------------------===//
80 //===----------------------------------------------------------------------===//
82 def : InstRW<[FXU], (instregex "ADJDYNALLOC$")>; // Pseudo -> LA / LAY
84 //===----------------------------------------------------------------------===//
85 // Branch instructions
86 //===----------------------------------------------------------------------===//
89 def : InstRW<[LSU, EndGroup], (instregex "(Call)?BRC(L)?(Asm.*)?$")>;
90 def : InstRW<[LSU, EndGroup], (instregex "(Call)?J(G)?(Asm.*)?$")>;
91 def : InstRW<[LSU, EndGroup], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
92 def : InstRW<[LSU, EndGroup], (instregex "(Call)?B(R)?(Asm.*)?$")>;
93 def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BRCT(G|H)?$")>;
94 def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BCT(G)?(R)?$")>;
95 def : InstRW<[FXU, FXU, FXU, LSU, Lat7, GroupAlone],
96 (instregex "B(R)?X(H|L).*$")>;
99 def : InstRW<[FXU, LSU, Lat5, GroupAlone],
100 (instregex "C(L)?(G)?(I|R)J(Asm.*)?$")>;
101 def : InstRW<[FXU, LSU, Lat5, GroupAlone],
102 (instregex "C(L)?(G)?(I|R)B(Call|Return|Asm.*)?$")>;
104 //===----------------------------------------------------------------------===//
106 //===----------------------------------------------------------------------===//
109 def : InstRW<[LSU, EndGroup], (instregex "(Cond)?Trap$")>;
112 def : InstRW<[FXU], (instregex "C(G)?(I|R)T(Asm.*)?$")>;
113 def : InstRW<[FXU], (instregex "CL(G)?RT(Asm.*)?$")>;
114 def : InstRW<[FXU], (instregex "CL(F|G)IT(Asm.*)?$")>;
116 //===----------------------------------------------------------------------===//
117 // Call and return instructions
118 //===----------------------------------------------------------------------===//
121 def : InstRW<[LSU, FXU, FXU, Lat6, GroupAlone], (instregex "(Call)?BRAS$")>;
122 def : InstRW<[LSU, FXU, FXU, Lat6, GroupAlone], (instregex "(Call)?BRASL$")>;
123 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "(Call)?BAS(R)?$")>;
124 def : InstRW<[LSU, FXU, FXU, Lat6, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;
127 def : InstRW<[LSU_lat1, EndGroup], (instregex "Return$")>;
128 def : InstRW<[LSU_lat1, EndGroup], (instregex "CondReturn$")>;
130 //===----------------------------------------------------------------------===//
131 // Select instructions
132 //===----------------------------------------------------------------------===//
135 def : InstRW<[FXU], (instregex "Select(32|64|32Mux)$")>;
138 def : InstRW<[FXU], (instregex "CondStore16(Inv)?$")>;
139 def : InstRW<[FXU], (instregex "CondStore16Mux(Inv)?$")>;
140 def : InstRW<[FXU], (instregex "CondStore32(Inv)?$")>;
141 def : InstRW<[FXU], (instregex "CondStore64(Inv)?$")>;
142 def : InstRW<[FXU], (instregex "CondStore8(Inv)?$")>;
143 def : InstRW<[FXU], (instregex "CondStore8Mux(Inv)?$")>;
145 //===----------------------------------------------------------------------===//
147 //===----------------------------------------------------------------------===//
150 def : InstRW<[FXU, LSU, Lat5], (instregex "MV(G|H)?HI$")>;
151 def : InstRW<[FXU, LSU, Lat5], (instregex "MVI(Y)?$")>;
154 def : InstRW<[LSU, LSU, LSU, FXU, Lat8, GroupAlone], (instregex "MVC$")>;
156 // Pseudo -> reg move
157 def : InstRW<[FXU], (instregex "COPY(_TO_REGCLASS)?$")>;
158 def : InstRW<[FXU], (instregex "EXTRACT_SUBREG$")>;
159 def : InstRW<[FXU], (instregex "INSERT_SUBREG$")>;
160 def : InstRW<[FXU], (instregex "REG_SEQUENCE$")>;
161 def : InstRW<[FXU], (instregex "SUBREG_TO_REG$")>;
164 def : InstRW<[LSU], (instregex "L(Y|FH|RL|Mux)?$")>;
165 def : InstRW<[LSU], (instregex "LG(RL)?$")>;
166 def : InstRW<[LSU], (instregex "L128$")>;
168 def : InstRW<[FXU], (instregex "LLIH(F|H|L)$")>;
169 def : InstRW<[FXU], (instregex "LLIL(F|H|L)$")>;
171 def : InstRW<[FXU], (instregex "LG(F|H)I$")>;
172 def : InstRW<[FXU], (instregex "LHI(Mux)?$")>;
173 def : InstRW<[FXU], (instregex "LR(Mux)?$")>;
176 def : InstRW<[FXU, LSU, Lat5], (instregex "LT(G)?$")>;
177 def : InstRW<[FXU], (instregex "LT(G)?R$")>;
180 def : InstRW<[FXU, LSU, Lat5], (instregex "STG(RL)?$")>;
181 def : InstRW<[FXU, LSU, Lat5], (instregex "ST128$")>;
182 def : InstRW<[FXU, LSU, Lat5], (instregex "ST(Y|FH|RL|Mux)?$")>;
185 def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVST$")>;
187 //===----------------------------------------------------------------------===//
188 // Conditional move instructions
189 //===----------------------------------------------------------------------===//
191 def : InstRW<[FXU, Lat2, EndGroup], (instregex "LOC(G)?R(Asm.*)?$")>;
192 def : InstRW<[FXU, LSU, Lat6, EndGroup], (instregex "LOC(G)?(Asm.*)?$")>;
193 def : InstRW<[FXU, LSU, Lat5, EndGroup], (instregex "STOC(G)?(Asm.*)?$")>;
195 //===----------------------------------------------------------------------===//
197 //===----------------------------------------------------------------------===//
198 def : InstRW<[FXU], (instregex "L(B|H|G)R$")>;
199 def : InstRW<[FXU], (instregex "LG(B|H|F)R$")>;
201 def : InstRW<[FXU, LSU, Lat5], (instregex "LTGF$")>;
202 def : InstRW<[FXU], (instregex "LTGFR$")>;
204 def : InstRW<[FXU, LSU, Lat5], (instregex "LB(H|Mux)?$")>;
205 def : InstRW<[FXU, LSU, Lat5], (instregex "LH(Y)?$")>;
206 def : InstRW<[FXU, LSU, Lat5], (instregex "LH(H|Mux|RL)$")>;
207 def : InstRW<[FXU, LSU, Lat5], (instregex "LG(B|H|F)$")>;
208 def : InstRW<[FXU, LSU, Lat5], (instregex "LG(H|F)RL$")>;
210 //===----------------------------------------------------------------------===//
212 //===----------------------------------------------------------------------===//
214 def : InstRW<[FXU], (instregex "LLCR(Mux)?$")>;
215 def : InstRW<[FXU], (instregex "LLHR(Mux)?$")>;
216 def : InstRW<[FXU], (instregex "LLG(C|F|H|T)R$")>;
217 def : InstRW<[LSU], (instregex "LLC(Mux)?$")>;
218 def : InstRW<[LSU], (instregex "LLH(Mux)?$")>;
219 def : InstRW<[FXU, LSU, Lat5], (instregex "LL(C|H)H$")>;
220 def : InstRW<[LSU], (instregex "LLHRL$")>;
221 def : InstRW<[LSU], (instregex "LLG(C|F|H|T|FRL|HRL)$")>;
223 //===----------------------------------------------------------------------===//
225 //===----------------------------------------------------------------------===//
227 def : InstRW<[FXU, LSU, Lat5], (instregex "STC(H|Y|Mux)?$")>;
228 def : InstRW<[FXU, LSU, Lat5], (instregex "STH(H|Y|RL|Mux)?$")>;
230 //===----------------------------------------------------------------------===//
231 // Multi-register moves
232 //===----------------------------------------------------------------------===//
234 // Load multiple (estimated average of 5 ops)
235 def : InstRW<[LSU, LSU, LSU, LSU, LSU, Lat10, GroupAlone],
236 (instregex "LM(H|Y|G)?$")>;
238 // Store multiple (estimated average of 3 ops)
239 def : InstRW<[LSU, LSU, FXU, FXU, FXU, Lat10, GroupAlone],
240 (instregex "STM(H|Y|G)?$")>;
242 //===----------------------------------------------------------------------===//
244 //===----------------------------------------------------------------------===//
246 def : InstRW<[FXU], (instregex "LRV(G)?R$")>;
247 def : InstRW<[FXU, LSU, Lat5], (instregex "LRV(G|H)?$")>;
248 def : InstRW<[FXU, LSU, Lat5], (instregex "STRV(G|H)?$")>;
250 //===----------------------------------------------------------------------===//
251 // Load address instructions
252 //===----------------------------------------------------------------------===//
254 def : InstRW<[FXU], (instregex "LA(Y|RL)?$")>;
256 // Load the Global Offset Table address
257 def : InstRW<[FXU], (instregex "GOT$")>;
259 //===----------------------------------------------------------------------===//
260 // Absolute and Negation
261 //===----------------------------------------------------------------------===//
263 def : InstRW<[FXU, Lat2], (instregex "LP(G)?R$")>;
264 def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "L(N|P)GFR$")>;
265 def : InstRW<[FXU, Lat2], (instregex "LN(R|GR)$")>;
266 def : InstRW<[FXU], (instregex "LC(R|GR)$")>;
267 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LCGFR$")>;
269 //===----------------------------------------------------------------------===//
271 //===----------------------------------------------------------------------===//
273 def : InstRW<[FXU, LSU, Lat5], (instregex "IC(Y)?$")>;
274 def : InstRW<[FXU, LSU, Lat5], (instregex "IC32(Y)?$")>;
275 def : InstRW<[FXU, LSU, Lat5], (instregex "ICM(H|Y)?$")>;
276 def : InstRW<[FXU], (instregex "II(F|H|L)Mux$")>;
277 def : InstRW<[FXU], (instregex "IIHF(64)?$")>;
278 def : InstRW<[FXU], (instregex "IIHH(64)?$")>;
279 def : InstRW<[FXU], (instregex "IIHL(64)?$")>;
280 def : InstRW<[FXU], (instregex "IILF(64)?$")>;
281 def : InstRW<[FXU], (instregex "IILH(64)?$")>;
282 def : InstRW<[FXU], (instregex "IILL(64)?$")>;
284 //===----------------------------------------------------------------------===//
286 //===----------------------------------------------------------------------===//
288 def : InstRW<[FXU, LSU, Lat5], (instregex "A(Y|SI)?$")>;
289 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "AH(Y)?$")>;
290 def : InstRW<[FXU], (instregex "AIH$")>;
291 def : InstRW<[FXU], (instregex "AFI(Mux)?$")>;
292 def : InstRW<[FXU], (instregex "AGFI$")>;
293 def : InstRW<[FXU], (instregex "AGHI(K)?$")>;
294 def : InstRW<[FXU], (instregex "AGR(K)?$")>;
295 def : InstRW<[FXU], (instregex "AHI(K)?$")>;
296 def : InstRW<[FXU], (instregex "AHIMux(K)?$")>;
297 def : InstRW<[FXU, LSU, Lat5], (instregex "AL(Y)?$")>;
298 def : InstRW<[FXU], (instregex "AL(FI|HSIK)$")>;
299 def : InstRW<[FXU, LSU, Lat5], (instregex "ALG(F)?$")>;
300 def : InstRW<[FXU], (instregex "ALGHSIK$")>;
301 def : InstRW<[FXU], (instregex "ALGF(I|R)$")>;
302 def : InstRW<[FXU], (instregex "ALGR(K)?$")>;
303 def : InstRW<[FXU], (instregex "ALR(K)?$")>;
304 def : InstRW<[FXU], (instregex "AR(K)?$")>;
305 def : InstRW<[FXU, LSU, Lat5], (instregex "AG(SI)?$")>;
307 // Logical addition with carry
308 def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "ALC(G)?$")>;
309 def : InstRW<[FXU, Lat3, GroupAlone], (instregex "ALC(G)?R$")>;
311 // Add with sign extension (32 -> 64)
312 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "AGF$")>;
313 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "AGFR$")>;
315 //===----------------------------------------------------------------------===//
317 //===----------------------------------------------------------------------===//
319 def : InstRW<[FXU, LSU, Lat5], (instregex "S(G|Y)?$")>;
320 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "SH(Y)?$")>;
321 def : InstRW<[FXU], (instregex "SGR(K)?$")>;
322 def : InstRW<[FXU], (instregex "SLFI$")>;
323 def : InstRW<[FXU, LSU, Lat5], (instregex "SL(G|GF|Y)?$")>;
324 def : InstRW<[FXU], (instregex "SLGF(I|R)$")>;
325 def : InstRW<[FXU], (instregex "SLGR(K)?$")>;
326 def : InstRW<[FXU], (instregex "SLR(K)?$")>;
327 def : InstRW<[FXU], (instregex "SR(K)?$")>;
329 // Subtraction with borrow
330 def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "SLB(G)?$")>;
331 def : InstRW<[FXU, Lat3, GroupAlone], (instregex "SLB(G)?R$")>;
333 // Subtraction with sign extension (32 -> 64)
334 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "SGF$")>;
335 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "SGFR$")>;
337 //===----------------------------------------------------------------------===//
339 //===----------------------------------------------------------------------===//
341 def : InstRW<[FXU, LSU, Lat5], (instregex "N(G|Y)?$")>;
342 def : InstRW<[FXU], (instregex "NGR(K)?$")>;
343 def : InstRW<[FXU], (instregex "NI(FMux|HMux|LMux)$")>;
344 def : InstRW<[FXU, LSU, Lat5], (instregex "NI(Y)?$")>;
345 def : InstRW<[FXU], (instregex "NIHF(64)?$")>;
346 def : InstRW<[FXU], (instregex "NIHH(64)?$")>;
347 def : InstRW<[FXU], (instregex "NIHL(64)?$")>;
348 def : InstRW<[FXU], (instregex "NILF(64)?$")>;
349 def : InstRW<[FXU], (instregex "NILH(64)?$")>;
350 def : InstRW<[FXU], (instregex "NILL(64)?$")>;
351 def : InstRW<[FXU], (instregex "NR(K)?$")>;
352 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "NC$")>;
354 //===----------------------------------------------------------------------===//
356 //===----------------------------------------------------------------------===//
358 def : InstRW<[FXU, LSU, Lat5], (instregex "O(G|Y)?$")>;
359 def : InstRW<[FXU], (instregex "OGR(K)?$")>;
360 def : InstRW<[FXU, LSU, Lat5], (instregex "OI(Y)?$")>;
361 def : InstRW<[FXU], (instregex "OI(FMux|HMux|LMux)$")>;
362 def : InstRW<[FXU], (instregex "OIHF(64)?$")>;
363 def : InstRW<[FXU], (instregex "OIHH(64)?$")>;
364 def : InstRW<[FXU], (instregex "OIHL(64)?$")>;
365 def : InstRW<[FXU], (instregex "OILF(64)?$")>;
366 def : InstRW<[FXU], (instregex "OILH(64)?$")>;
367 def : InstRW<[FXU], (instregex "OILL(64)?$")>;
368 def : InstRW<[FXU], (instregex "OR(K)?$")>;
369 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "OC$")>;
371 //===----------------------------------------------------------------------===//
373 //===----------------------------------------------------------------------===//
375 def : InstRW<[FXU, LSU, Lat5], (instregex "X(G|Y)?$")>;
376 def : InstRW<[FXU, LSU, Lat5], (instregex "XI(Y)?$")>;
377 def : InstRW<[FXU], (instregex "XIFMux$")>;
378 def : InstRW<[FXU], (instregex "XGR(K)?$")>;
379 def : InstRW<[FXU], (instregex "XIHF(64)?$")>;
380 def : InstRW<[FXU], (instregex "XILF(64)?$")>;
381 def : InstRW<[FXU], (instregex "XR(K)?$")>;
382 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "XC$")>;
384 //===----------------------------------------------------------------------===//
386 //===----------------------------------------------------------------------===//
388 def : InstRW<[FXU, LSU, Lat10], (instregex "MS(GF|Y)?$")>;
389 def : InstRW<[FXU, Lat6], (instregex "MS(R|FI)$")>;
390 def : InstRW<[FXU, LSU, Lat12], (instregex "MSG$")>;
391 def : InstRW<[FXU, Lat8], (instregex "MSGR$")>;
392 def : InstRW<[FXU, Lat6], (instregex "MSGF(I|R)$")>;
393 def : InstRW<[FXU, LSU, Lat15, GroupAlone], (instregex "MLG$")>;
394 def : InstRW<[FXU, Lat9, GroupAlone], (instregex "MLGR$")>;
395 def : InstRW<[FXU, Lat5], (instregex "MGHI$")>;
396 def : InstRW<[FXU, Lat5], (instregex "MHI$")>;
397 def : InstRW<[FXU, LSU, Lat9], (instregex "MH(Y)?$")>;
399 //===----------------------------------------------------------------------===//
400 // Division and remainder
401 //===----------------------------------------------------------------------===//
403 def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
404 (instregex "DSG(F)?R$")>;
405 def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, Lat30, GroupAlone],
406 (instregex "DSG(F)?$")>;
407 def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
408 (instregex "DL(G)?R$")>;
409 def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
410 (instregex "DL(G)?$")>;
412 //===----------------------------------------------------------------------===//
414 //===----------------------------------------------------------------------===//
416 def : InstRW<[FXU], (instregex "SLL(G|K)?$")>;
417 def : InstRW<[FXU], (instregex "SRL(G|K)?$")>;
418 def : InstRW<[FXU], (instregex "SRA(G|K)?$")>;
419 def : InstRW<[FXU, Lat2], (instregex "SLA(K)?$")>;
422 def : InstRW<[FXU, LSU, Lat6], (instregex "RLL(G)?$")>;
425 def : InstRW<[FXU], (instregex "RISBG(32)?$")>;
426 def : InstRW<[FXU], (instregex "RISBH(G|H|L)$")>;
427 def : InstRW<[FXU], (instregex "RISBL(G|H|L)$")>;
428 def : InstRW<[FXU], (instregex "RISBMux$")>;
431 def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "R(N|O|X)SBG$")>;
433 //===----------------------------------------------------------------------===//
435 //===----------------------------------------------------------------------===//
437 def : InstRW<[FXU, LSU, Lat5], (instregex "C(G|Y|Mux|RL)?$")>;
438 def : InstRW<[FXU], (instregex "C(F|H)I(Mux)?$")>;
439 def : InstRW<[FXU], (instregex "CG(F|H)I$")>;
440 def : InstRW<[FXU, LSU, Lat5], (instregex "CG(HSI|RL)$")>;
441 def : InstRW<[FXU], (instregex "C(G)?R$")>;
442 def : InstRW<[FXU], (instregex "CIH$")>;
443 def : InstRW<[FXU, LSU, Lat5], (instregex "CH(F|SI)$")>;
444 def : InstRW<[FXU, LSU, Lat5], (instregex "CL(Y|Mux|FHSI)?$")>;
445 def : InstRW<[FXU], (instregex "CLFI(Mux)?$")>;
446 def : InstRW<[FXU, LSU, Lat5], (instregex "CLG(HRL|HSI)?$")>;
447 def : InstRW<[FXU, LSU, Lat5], (instregex "CLGF(RL)?$")>;
448 def : InstRW<[FXU], (instregex "CLGF(I|R)$")>;
449 def : InstRW<[FXU], (instregex "CLGR$")>;
450 def : InstRW<[FXU, LSU, Lat5], (instregex "CLGRL$")>;
451 def : InstRW<[FXU, LSU, Lat5], (instregex "CLH(F|RL|HSI)$")>;
452 def : InstRW<[FXU], (instregex "CLIH$")>;
453 def : InstRW<[FXU, LSU, Lat5], (instregex "CLI(Y)?$")>;
454 def : InstRW<[FXU], (instregex "CLR$")>;
455 def : InstRW<[FXU, LSU, Lat5], (instregex "CLRL$")>;
458 def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CH(Y|RL)?$")>;
459 def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CGH(RL)?$")>;
460 def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CHHSI$")>;
462 // Compare with sign extension (32 -> 64)
463 def : InstRW<[FXU, FXU, LSU, Lat6, Lat2, GroupAlone], (instregex "CGF(RL)?$")>;
464 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "CGFR$")>;
466 // Compare logical character
467 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "CLC$")>;
469 def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CLST$")>;
472 def : InstRW<[FXU, LSU, Lat5], (instregex "TM(Y)?$")>;
473 def : InstRW<[FXU], (instregex "TM(H|L)Mux$")>;
474 def : InstRW<[FXU], (instregex "TMHH(64)?$")>;
475 def : InstRW<[FXU], (instregex "TMHL(64)?$")>;
476 def : InstRW<[FXU], (instregex "TMLH(64)?$")>;
477 def : InstRW<[FXU], (instregex "TMLL(64)?$")>;
479 //===----------------------------------------------------------------------===//
481 //===----------------------------------------------------------------------===//
483 def : InstRW<[LSU, GroupAlone], (instregex "PFD(RL)?$")>;
485 //===----------------------------------------------------------------------===//
487 //===----------------------------------------------------------------------===//
489 def : InstRW<[LSU, EndGroup], (instregex "Serialize$")>;
491 def : InstRW<[FXU, LSU, Lat5], (instregex "LAA(G)?$")>;
492 def : InstRW<[FXU, LSU, Lat5], (instregex "LAAL(G)?$")>;
493 def : InstRW<[FXU, LSU, Lat5], (instregex "LAN(G)?$")>;
494 def : InstRW<[FXU, LSU, Lat5], (instregex "LAO(G)?$")>;
495 def : InstRW<[FXU, LSU, Lat5], (instregex "LAX(G)?$")>;
498 def : InstRW<[FXU, LSU, Lat5, EndGroup], (instregex "TS$")>;
501 def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
503 // Compare double and swap
504 def : InstRW<[FXU, FXU, FXU, FXU, FXU, LSU, Lat10, GroupAlone],
505 (instregex "CDS(Y)?$")>;
506 def : InstRW<[FXU, FXU, FXU, FXU, FXU, FXU, LSU, LSU, Lat12, GroupAlone],
507 (instregex "CDSG$")>;
509 // Compare and swap and store
510 def : InstRW<[FXU, Lat30, GroupAlone], (instregex "CSST$")>;
512 // Perform locked operation
513 def : InstRW<[LSU, Lat30, GroupAlone], (instregex "PLO$")>;
515 // Load/store pair from/to quadword
516 def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPQ$")>;
517 def : InstRW<[FXU, FXU, LSU, LSU, Lat6, GroupAlone], (instregex "STPQ$")>;
519 // Load pair disjoint
520 def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPD(G)?$")>;
522 //===----------------------------------------------------------------------===//
524 //===----------------------------------------------------------------------===//
526 // Extract/set/copy access register
527 def : InstRW<[LSU], (instregex "(EAR|SAR|CPYA)$")>;
529 // Load address extended
530 def : InstRW<[LSU, FXU, Lat5, GroupAlone], (instregex "LAE(Y)?$")>;
532 // Load/store access multiple (not modeled precisely)
533 def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(L|ST)AM(Y)?$")>;
535 //===----------------------------------------------------------------------===//
536 // Program mask and addressing mode
537 //===----------------------------------------------------------------------===//
539 // Insert Program Mask
540 def : InstRW<[FXU, Lat3, EndGroup], (instregex "IPM$")>;
543 def : InstRW<[LSU, EndGroup], (instregex "SPM$")>;
546 def : InstRW<[FXU, FXU, LSU, Lat8, GroupAlone], (instregex "BAL(R)?$")>;
548 // Test addressing mode
549 def : InstRW<[FXU], (instregex "TAM$")>;
551 // Set addressing mode
552 def : InstRW<[LSU, EndGroup], (instregex "SAM(24|31|64)$")>;
554 // Branch (and save) and set mode.
555 def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BSM$")>;
556 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "BASSM$")>;
558 //===----------------------------------------------------------------------===//
559 // Miscellaneous Instructions.
560 //===----------------------------------------------------------------------===//
563 def : InstRW<[FXU, Lat7, GroupAlone], (instregex "FLOGR$")>;
566 def : InstRW<[FXU, Lat3], (instregex "POPCNT$")>;
569 def : InstRW<[FXU], (instregex "AEXT128_64$")>;
570 def : InstRW<[FXU], (instregex "ZEXT128_(32|64)$")>;
572 // String instructions
573 def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>;
576 def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
579 def : InstRW<[FXU, Lat5, LSU], (instregex "ECTG$")>;
582 def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
585 def : InstRW<[FXU, Lat30], (instregex "PR$")>;
588 def : InstRW<[FXU, LSU, Lat15], (instregex "STCK$")>;
589 def : InstRW<[FXU, LSU, Lat12], (instregex "STCKF$")>;
590 def : InstRW<[LSU, FXU, Lat5], (instregex "STCKE$")>;
591 def : InstRW<[FXU, LSU, Lat5], (instregex "STFLE$")>;
592 def : InstRW<[FXU, Lat30], (instregex "SVC$")>;
594 // Store real address
595 def : InstRW<[FXU, LSU, Lat5], (instregex "STRAG$")>;
597 //===----------------------------------------------------------------------===//
598 // .insn directive instructions
599 //===----------------------------------------------------------------------===//
601 // An "empty" sched-class will be assigned instead of the "invalid sched-class".
602 // getNumDecoderSlots() will then return 1 instead of 0.
603 def : InstRW<[], (instregex "Insn.*")>;
606 // ----------------------------- Floating point ----------------------------- //
608 //===----------------------------------------------------------------------===//
609 // FP: Select instructions
610 //===----------------------------------------------------------------------===//
612 def : InstRW<[FXU], (instregex "SelectF(32|64|128)$")>;
613 def : InstRW<[FXU], (instregex "CondStoreF32(Inv)?$")>;
614 def : InstRW<[FXU], (instregex "CondStoreF64(Inv)?$")>;
616 //===----------------------------------------------------------------------===//
617 // FP: Move instructions
618 //===----------------------------------------------------------------------===//
621 def : InstRW<[FXU], (instregex "LZ(DR|ER)$")>;
622 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LZXR$")>;
625 def : InstRW<[FXU], (instregex "LER$")>;
626 def : InstRW<[FXU], (instregex "LD(R|R32|GR)$")>;
627 def : InstRW<[FXU, Lat3], (instregex "LGDR$")>;
628 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LXR$")>;
631 def : InstRW<[FPU], (instregex "LT(D|E)BR$")>;
632 def : InstRW<[FPU], (instregex "LTEBRCompare(_VecPseudo)?$")>;
633 def : InstRW<[FPU], (instregex "LTDBRCompare(_VecPseudo)?$")>;
634 def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "LTXBR$")>;
635 def : InstRW<[FPU2, FPU2, Lat9, GroupAlone],
636 (instregex "LTXBRCompare(_VecPseudo)?$")>;
639 def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRd(d|s)$")>;
640 def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRs(d|s)$")>;
642 //===----------------------------------------------------------------------===//
643 // FP: Load instructions
644 //===----------------------------------------------------------------------===//
646 def : InstRW<[LSU], (instregex "LE(Y)?$")>;
647 def : InstRW<[LSU], (instregex "LD(Y|E32)?$")>;
648 def : InstRW<[LSU], (instregex "LX$")>;
650 //===----------------------------------------------------------------------===//
651 // FP: Store instructions
652 //===----------------------------------------------------------------------===//
654 def : InstRW<[FXU, LSU, Lat7], (instregex "STD(Y)?$")>;
655 def : InstRW<[FXU, LSU, Lat7], (instregex "STE(Y)?$")>;
656 def : InstRW<[FXU, LSU, Lat5], (instregex "STX$")>;
658 //===----------------------------------------------------------------------===//
659 // FP: Conversion instructions
660 //===----------------------------------------------------------------------===//
663 def : InstRW<[FPU], (instregex "LEDBR(A)?$")>;
664 def : InstRW<[FPU, FPU, Lat20], (instregex "LEXBR(A)?$")>;
665 def : InstRW<[FPU, FPU, Lat20], (instregex "LDXBR(A)?$")>;
668 def : InstRW<[FPU, LSU, Lat12], (instregex "LDEB$")>;
669 def : InstRW<[FPU], (instregex "LDEBR$")>;
670 def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "LX(D|E)B$")>;
671 def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "LX(D|E)BR$")>;
673 // Convert from fixed / logical
674 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CE(F|G)BR(A)?$")>;
675 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CD(F|G)BR(A)?$")>;
676 def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CX(F|G)BR(A)?$")>;
677 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CEL(F|G)BR$")>;
678 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CDL(F|G)BR$")>;
679 def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CXL(F|G)BR$")>;
681 // Convert to fixed / logical
682 def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CF(E|D)BR(A)?$")>;
683 def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CG(E|D)BR(A)?$")>;
684 def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "C(F|G)XBR(A)?$")>;
685 def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLF(E|D)BR$")>;
686 def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLG(E|D)BR$")>;
687 def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "CL(F|G)XBR$")>;
689 //===----------------------------------------------------------------------===//
690 // FP: Unary arithmetic
691 //===----------------------------------------------------------------------===//
693 // Load Complement / Negative / Positive
694 def : InstRW<[FPU], (instregex "L(C|N|P)DBR$")>;
695 def : InstRW<[FPU], (instregex "L(C|N|P)EBR$")>;
696 def : InstRW<[FXU], (instregex "LCDFR(_32)?$")>;
697 def : InstRW<[FXU], (instregex "LNDFR(_32)?$")>;
698 def : InstRW<[FXU], (instregex "LPDFR(_32)?$")>;
699 def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "L(C|N|P)XBR$")>;
702 def : InstRW<[FPU, LSU, Lat30], (instregex "SQ(E|D)B$")>;
703 def : InstRW<[FPU, Lat30], (instregex "SQ(E|D)BR$")>;
704 def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "SQXBR$")>;
707 def : InstRW<[FPU], (instregex "FIEBR(A)?$")>;
708 def : InstRW<[FPU], (instregex "FIDBR(A)?$")>;
709 def : InstRW<[FPU2, FPU2, Lat15, GroupAlone], (instregex "FIXBR(A)?$")>;
711 //===----------------------------------------------------------------------===//
712 // FP: Binary arithmetic
713 //===----------------------------------------------------------------------===//
716 def : InstRW<[FPU, LSU, Lat12], (instregex "A(E|D)B$")>;
717 def : InstRW<[FPU], (instregex "A(E|D)BR$")>;
718 def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "AXBR$")>;
721 def : InstRW<[FPU, LSU, Lat12], (instregex "S(E|D)B$")>;
722 def : InstRW<[FPU], (instregex "S(E|D)BR$")>;
723 def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "SXBR$")>;
726 def : InstRW<[FPU, LSU, Lat12], (instregex "M(D|DE|EE)B$")>;
727 def : InstRW<[FPU], (instregex "M(D|DE|EE)BR$")>;
728 def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "MXDB$")>;
729 def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "MXDBR$")>;
730 def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "MXBR$")>;
732 // Multiply and add / subtract
733 def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)EB$")>;
734 def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)EBR$")>;
735 def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)DB$")>;
736 def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)DBR$")>;
739 def : InstRW<[FPU, LSU, Lat30], (instregex "D(E|D)B$")>;
740 def : InstRW<[FPU, Lat30], (instregex "D(E|D)BR$")>;
741 def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "DXBR$")>;
743 //===----------------------------------------------------------------------===//
745 //===----------------------------------------------------------------------===//
748 def : InstRW<[FPU, LSU, Lat12], (instregex "C(E|D)B$")>;
749 def : InstRW<[FPU], (instregex "C(E|D)BR$")>;
750 def : InstRW<[FPU, FPU, Lat30], (instregex "CXBR$")>;
753 def : InstRW<[FPU, LSU, Lat15], (instregex "TC(E|D)B$")>;
754 def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "TCXB$")>;
756 //===----------------------------------------------------------------------===//
757 // FP: Floating-point control register instructions
758 //===----------------------------------------------------------------------===//
760 def : InstRW<[FXU, LSU, Lat4, GroupAlone], (instregex "EFPC$")>;
761 def : InstRW<[LSU, Lat3, GroupAlone], (instregex "SFPC$")>;
762 def : InstRW<[LSU, LSU, Lat6, GroupAlone], (instregex "LFPC$")>;
763 def : InstRW<[LSU, Lat3, GroupAlone], (instregex "STFPC$")>;
764 def : InstRW<[FXU, Lat30, GroupAlone], (instregex "SFASR$")>;
765 def : InstRW<[FXU, LSU, Lat30, GroupAlone], (instregex "LFAS$")>;
766 def : InstRW<[FXU, Lat2, GroupAlone], (instregex "SRNM(B|T)?$")>;