1 //=- SystemZScheduleZEC12.td - SystemZ Scheduling Definitions --*- tblgen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the machine model for ZEC12 to support instruction
11 // scheduling and other instruction cost heuristics.
13 //===----------------------------------------------------------------------===//
15 def ZEC12Model : SchedMachineModel {
17 let UnsupportedFeatures = Arch10UnsupportedFeatures.List;
20 let MicroOpBufferSize = 40; // Issue queues
21 let LoadLatency = 1; // Optimistic load latency.
23 let PostRAScheduler = 1;
25 // Extra cycles for a mispredicted branch.
26 let MispredictPenalty = 16;
29 let SchedModel = ZEC12Model in {
31 // These definitions could be put in a subtarget common include file,
32 // but it seems the include system in Tablegen currently rejects
33 // multiple includes of same file.
34 def : WriteRes<GroupAlone, []> {
39 def : WriteRes<EndGroup, []> {
43 def : WriteRes<Lat2, []> { let Latency = 2; let NumMicroOps = 0;}
44 def : WriteRes<Lat3, []> { let Latency = 3; let NumMicroOps = 0;}
45 def : WriteRes<Lat4, []> { let Latency = 4; let NumMicroOps = 0;}
46 def : WriteRes<Lat5, []> { let Latency = 5; let NumMicroOps = 0;}
47 def : WriteRes<Lat6, []> { let Latency = 6; let NumMicroOps = 0;}
48 def : WriteRes<Lat7, []> { let Latency = 7; let NumMicroOps = 0;}
49 def : WriteRes<Lat8, []> { let Latency = 8; let NumMicroOps = 0;}
50 def : WriteRes<Lat9, []> { let Latency = 9; let NumMicroOps = 0;}
51 def : WriteRes<Lat10, []> { let Latency = 10; let NumMicroOps = 0;}
52 def : WriteRes<Lat11, []> { let Latency = 11; let NumMicroOps = 0;}
53 def : WriteRes<Lat12, []> { let Latency = 12; let NumMicroOps = 0;}
54 def : WriteRes<Lat15, []> { let Latency = 15; let NumMicroOps = 0;}
55 def : WriteRes<Lat20, []> { let Latency = 20; let NumMicroOps = 0;}
56 def : WriteRes<Lat30, []> { let Latency = 30; let NumMicroOps = 0;}
59 def ZEC12_FXUnit : ProcResource<2>;
60 def ZEC12_LSUnit : ProcResource<2>;
61 def ZEC12_FPUnit : ProcResource<1>;
62 def ZEC12_VBUnit : ProcResource<1>;
64 // Subtarget specific definitions of scheduling resources.
65 def : WriteRes<FXU, [ZEC12_FXUnit]> { let Latency = 1; }
66 def : WriteRes<LSU, [ZEC12_LSUnit]> { let Latency = 4; }
67 def : WriteRes<LSU_lat1, [ZEC12_LSUnit]> { let Latency = 1; }
68 def : WriteRes<FPU, [ZEC12_FPUnit]> { let Latency = 8; }
69 def : WriteRes<FPU2, [ZEC12_FPUnit, ZEC12_FPUnit]> { let Latency = 9; }
70 def : WriteRes<VBU, [ZEC12_VBUnit]>; // Virtual Branching Unit
72 // -------------------------- INSTRUCTIONS ---------------------------------- //
74 // InstRW constructs have been used in order to preserve the
75 // readability of the InstrInfo files.
77 // For each instruction, as matched by a regexp, provide a list of
78 // resources that it needs. These will be combined into a SchedClass.
80 //===----------------------------------------------------------------------===//
82 //===----------------------------------------------------------------------===//
84 def : InstRW<[FXU], (instregex "ADJDYNALLOC$")>; // Pseudo -> LA / LAY
86 //===----------------------------------------------------------------------===//
87 // Branch instructions
88 //===----------------------------------------------------------------------===//
91 def : InstRW<[VBU], (instregex "(Call)?BRC(L)?(Asm.*)?$")>;
92 def : InstRW<[VBU], (instregex "(Call)?J(G)?(Asm.*)?$")>;
93 def : InstRW<[LSU, Lat4], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
94 def : InstRW<[LSU, Lat4], (instregex "(Call)?B(R)?(Asm.*)?$")>;
95 def : InstRW<[FXU, EndGroup], (instregex "BRCT(G)?$")>;
96 def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BRCTH$")>;
97 def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BCT(G)?(R)?$")>;
98 def : InstRW<[FXU, FXU, FXU, LSU, Lat7, GroupAlone],
99 (instregex "B(R)?X(H|L).*$")>;
101 // Compare and branch
102 def : InstRW<[FXU], (instregex "C(L)?(G)?(I|R)J(Asm.*)?$")>;
103 def : InstRW<[FXU, LSU, Lat5, GroupAlone],
104 (instregex "C(L)?(G)?(I|R)B(Call|Return|Asm.*)?$")>;
106 //===----------------------------------------------------------------------===//
108 //===----------------------------------------------------------------------===//
111 def : InstRW<[VBU], (instregex "(Cond)?Trap$")>;
114 def : InstRW<[FXU], (instregex "C(G)?(I|R)T(Asm.*)?$")>;
115 def : InstRW<[FXU], (instregex "CL(G)?RT(Asm.*)?$")>;
116 def : InstRW<[FXU], (instregex "CL(F|G)IT(Asm.*)?$")>;
117 def : InstRW<[FXU, LSU, Lat5], (instregex "CL(G)?T(Asm.*)?$")>;
119 //===----------------------------------------------------------------------===//
120 // Call and return instructions
121 //===----------------------------------------------------------------------===//
124 def : InstRW<[VBU, FXU, FXU, Lat3, GroupAlone], (instregex "(Call)?BRAS$")>;
125 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "(Call)?BRASL$")>;
126 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "(Call)?BAS(R)?$")>;
127 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;
130 def : InstRW<[LSU_lat1, EndGroup], (instregex "Return$")>;
131 def : InstRW<[LSU_lat1], (instregex "CondReturn$")>;
133 //===----------------------------------------------------------------------===//
134 // Select instructions
135 //===----------------------------------------------------------------------===//
138 def : InstRW<[FXU], (instregex "Select(32|64|32Mux)$")>;
141 def : InstRW<[FXU], (instregex "CondStore16(Inv)?$")>;
142 def : InstRW<[FXU], (instregex "CondStore16Mux(Inv)?$")>;
143 def : InstRW<[FXU], (instregex "CondStore32(Inv)?$")>;
144 def : InstRW<[FXU], (instregex "CondStore64(Inv)?$")>;
145 def : InstRW<[FXU], (instregex "CondStore8(Inv)?$")>;
146 def : InstRW<[FXU], (instregex "CondStore8Mux(Inv)?$")>;
148 //===----------------------------------------------------------------------===//
150 //===----------------------------------------------------------------------===//
153 def : InstRW<[FXU, LSU, Lat5], (instregex "MV(G|H)?HI$")>;
154 def : InstRW<[FXU, LSU, Lat5], (instregex "MVI(Y)?$")>;
157 def : InstRW<[LSU, LSU, LSU, FXU, Lat8, GroupAlone], (instregex "MVC$")>;
159 // Pseudo -> reg move
160 def : InstRW<[FXU], (instregex "COPY(_TO_REGCLASS)?$")>;
161 def : InstRW<[FXU], (instregex "EXTRACT_SUBREG$")>;
162 def : InstRW<[FXU], (instregex "INSERT_SUBREG$")>;
163 def : InstRW<[FXU], (instregex "REG_SEQUENCE$")>;
164 def : InstRW<[FXU], (instregex "SUBREG_TO_REG$")>;
167 def : InstRW<[LSU], (instregex "L(Y|FH|RL|Mux)?$")>;
168 def : InstRW<[LSU], (instregex "LG(RL)?$")>;
169 def : InstRW<[LSU], (instregex "L128$")>;
171 def : InstRW<[FXU], (instregex "LLIH(F|H|L)$")>;
172 def : InstRW<[FXU], (instregex "LLIL(F|H|L)$")>;
174 def : InstRW<[FXU], (instregex "LG(F|H)I$")>;
175 def : InstRW<[FXU], (instregex "LHI(Mux)?$")>;
176 def : InstRW<[FXU], (instregex "LR(Mux)?$")>;
179 def : InstRW<[FXU, LSU, Lat5], (instregex "L(FH|G)?AT$")>;
182 def : InstRW<[FXU, LSU, Lat5], (instregex "LT(G)?$")>;
183 def : InstRW<[FXU], (instregex "LT(G)?R$")>;
186 def : InstRW<[FXU, LSU, Lat5], (instregex "STG(RL)?$")>;
187 def : InstRW<[FXU, LSU, Lat5], (instregex "ST128$")>;
188 def : InstRW<[FXU, LSU, Lat5], (instregex "ST(Y|FH|RL|Mux)?$")>;
191 def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVST$")>;
193 //===----------------------------------------------------------------------===//
194 // Conditional move instructions
195 //===----------------------------------------------------------------------===//
197 def : InstRW<[FXU, Lat2], (instregex "LOC(G)?R(Asm.*)?$")>;
198 def : InstRW<[FXU, LSU, Lat6], (instregex "LOC(G)?(Asm.*)?$")>;
199 def : InstRW<[FXU, LSU, Lat5], (instregex "STOC(G)?(Asm.*)?$")>;
201 //===----------------------------------------------------------------------===//
203 //===----------------------------------------------------------------------===//
205 def : InstRW<[FXU], (instregex "L(B|H|G)R$")>;
206 def : InstRW<[FXU], (instregex "LG(B|H|F)R$")>;
208 def : InstRW<[FXU, LSU, Lat5], (instregex "LTGF$")>;
209 def : InstRW<[FXU], (instregex "LTGFR$")>;
211 def : InstRW<[FXU, LSU, Lat5], (instregex "LB(H|Mux)?$")>;
212 def : InstRW<[FXU, LSU, Lat5], (instregex "LH(Y)?$")>;
213 def : InstRW<[FXU, LSU, Lat5], (instregex "LH(H|Mux|RL)$")>;
214 def : InstRW<[FXU, LSU, Lat5], (instregex "LG(B|H|F)$")>;
215 def : InstRW<[FXU, LSU, Lat5], (instregex "LG(H|F)RL$")>;
217 //===----------------------------------------------------------------------===//
219 //===----------------------------------------------------------------------===//
221 def : InstRW<[FXU], (instregex "LLCR(Mux)?$")>;
222 def : InstRW<[FXU], (instregex "LLHR(Mux)?$")>;
223 def : InstRW<[FXU], (instregex "LLG(C|H|F|T)R$")>;
224 def : InstRW<[LSU], (instregex "LLC(Mux)?$")>;
225 def : InstRW<[LSU], (instregex "LLH(Mux)?$")>;
226 def : InstRW<[FXU, LSU, Lat5], (instregex "LL(C|H)H$")>;
227 def : InstRW<[LSU], (instregex "LLHRL$")>;
228 def : InstRW<[LSU], (instregex "LLG(C|H|F|T|HRL|FRL)$")>;
231 def : InstRW<[FXU, LSU, Lat5], (instregex "LLG(F|T)?AT$")>;
233 //===----------------------------------------------------------------------===//
235 //===----------------------------------------------------------------------===//
237 def : InstRW<[FXU, LSU, Lat5], (instregex "STC(H|Y|Mux)?$")>;
238 def : InstRW<[FXU, LSU, Lat5], (instregex "STH(H|Y|RL|Mux)?$")>;
240 //===----------------------------------------------------------------------===//
241 // Multi-register moves
242 //===----------------------------------------------------------------------===//
244 // Load multiple (estimated average of 5 ops)
245 def : InstRW<[LSU, LSU, LSU, LSU, LSU, Lat10, GroupAlone],
246 (instregex "LM(H|Y|G)?$")>;
248 // Store multiple (estimated average of 3 ops)
249 def : InstRW<[LSU, LSU, FXU, FXU, FXU, Lat10, GroupAlone],
250 (instregex "STM(H|Y|G)?$")>;
252 //===----------------------------------------------------------------------===//
254 //===----------------------------------------------------------------------===//
256 def : InstRW<[FXU], (instregex "LRV(G)?R$")>;
257 def : InstRW<[FXU, LSU, Lat5], (instregex "LRV(G|H)?$")>;
258 def : InstRW<[FXU, LSU, Lat5], (instregex "STRV(G|H)?$")>;
260 //===----------------------------------------------------------------------===//
261 // Load address instructions
262 //===----------------------------------------------------------------------===//
264 def : InstRW<[FXU], (instregex "LA(Y|RL)?$")>;
266 // Load the Global Offset Table address
267 def : InstRW<[FXU], (instregex "GOT$")>;
269 //===----------------------------------------------------------------------===//
270 // Absolute and Negation
271 //===----------------------------------------------------------------------===//
273 def : InstRW<[FXU, Lat2], (instregex "LP(G)?R$")>;
274 def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "L(N|P)GFR$")>;
275 def : InstRW<[FXU, Lat2], (instregex "LN(R|GR)$")>;
276 def : InstRW<[FXU], (instregex "LC(R|GR)$")>;
277 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LCGFR$")>;
279 //===----------------------------------------------------------------------===//
281 //===----------------------------------------------------------------------===//
283 def : InstRW<[FXU, LSU, Lat5], (instregex "IC(Y)?$")>;
284 def : InstRW<[FXU, LSU, Lat5], (instregex "IC32(Y)?$")>;
285 def : InstRW<[FXU, LSU, Lat5], (instregex "ICM(H|Y)?$")>;
286 def : InstRW<[FXU], (instregex "II(F|H|L)Mux$")>;
287 def : InstRW<[FXU], (instregex "IIHF(64)?$")>;
288 def : InstRW<[FXU], (instregex "IIHH(64)?$")>;
289 def : InstRW<[FXU], (instregex "IIHL(64)?$")>;
290 def : InstRW<[FXU], (instregex "IILF(64)?$")>;
291 def : InstRW<[FXU], (instregex "IILH(64)?$")>;
292 def : InstRW<[FXU], (instregex "IILL(64)?$")>;
294 //===----------------------------------------------------------------------===//
296 //===----------------------------------------------------------------------===//
298 def : InstRW<[FXU, LSU, Lat5], (instregex "A(Y|SI)?$")>;
299 def : InstRW<[FXU, LSU, Lat6], (instregex "AH(Y)?$")>;
300 def : InstRW<[FXU], (instregex "AIH$")>;
301 def : InstRW<[FXU], (instregex "AFI(Mux)?$")>;
302 def : InstRW<[FXU], (instregex "AGFI$")>;
303 def : InstRW<[FXU], (instregex "AGHI(K)?$")>;
304 def : InstRW<[FXU], (instregex "AGR(K)?$")>;
305 def : InstRW<[FXU], (instregex "AHI(K)?$")>;
306 def : InstRW<[FXU], (instregex "AHIMux(K)?$")>;
307 def : InstRW<[FXU, LSU, Lat5], (instregex "AL(Y)?$")>;
308 def : InstRW<[FXU], (instregex "AL(FI|HSIK)$")>;
309 def : InstRW<[FXU, LSU, Lat5], (instregex "ALG(F)?$")>;
310 def : InstRW<[FXU], (instregex "ALGHSIK$")>;
311 def : InstRW<[FXU], (instregex "ALGF(I|R)$")>;
312 def : InstRW<[FXU], (instregex "ALGR(K)?$")>;
313 def : InstRW<[FXU], (instregex "ALR(K)?$")>;
314 def : InstRW<[FXU], (instregex "AR(K)?$")>;
315 def : InstRW<[FXU, LSU, Lat5], (instregex "AG(SI)?$")>;
317 // Logical addition with carry
318 def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "ALC(G)?$")>;
319 def : InstRW<[FXU, Lat3, GroupAlone], (instregex "ALC(G)?R$")>;
321 // Add with sign extension (32 -> 64)
322 def : InstRW<[FXU, LSU, Lat6], (instregex "AGF$")>;
323 def : InstRW<[FXU, Lat2], (instregex "AGFR$")>;
325 //===----------------------------------------------------------------------===//
327 //===----------------------------------------------------------------------===//
329 def : InstRW<[FXU, LSU, Lat5], (instregex "S(G|Y)?$")>;
330 def : InstRW<[FXU, LSU, Lat6], (instregex "SH(Y)?$")>;
331 def : InstRW<[FXU], (instregex "SGR(K)?$")>;
332 def : InstRW<[FXU], (instregex "SLFI$")>;
333 def : InstRW<[FXU, LSU, Lat5], (instregex "SL(G|GF|Y)?$")>;
334 def : InstRW<[FXU], (instregex "SLGF(I|R)$")>;
335 def : InstRW<[FXU], (instregex "SLGR(K)?$")>;
336 def : InstRW<[FXU], (instregex "SLR(K)?$")>;
337 def : InstRW<[FXU], (instregex "SR(K)?$")>;
339 // Subtraction with borrow
340 def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "SLB(G)?$")>;
341 def : InstRW<[FXU, Lat3, GroupAlone], (instregex "SLB(G)?R$")>;
343 // Subtraction with sign extension (32 -> 64)
344 def : InstRW<[FXU, LSU, Lat6], (instregex "SGF$")>;
345 def : InstRW<[FXU, Lat2], (instregex "SGFR$")>;
347 //===----------------------------------------------------------------------===//
349 //===----------------------------------------------------------------------===//
351 def : InstRW<[FXU, LSU, Lat5], (instregex "N(G|Y)?$")>;
352 def : InstRW<[FXU], (instregex "NGR(K)?$")>;
353 def : InstRW<[FXU], (instregex "NI(FMux|HMux|LMux)$")>;
354 def : InstRW<[FXU, LSU, Lat5], (instregex "NI(Y)?$")>;
355 def : InstRW<[FXU], (instregex "NIHF(64)?$")>;
356 def : InstRW<[FXU], (instregex "NIHH(64)?$")>;
357 def : InstRW<[FXU], (instregex "NIHL(64)?$")>;
358 def : InstRW<[FXU], (instregex "NILF(64)?$")>;
359 def : InstRW<[FXU], (instregex "NILH(64)?$")>;
360 def : InstRW<[FXU], (instregex "NILL(64)?$")>;
361 def : InstRW<[FXU], (instregex "NR(K)?$")>;
362 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "NC$")>;
364 //===----------------------------------------------------------------------===//
366 //===----------------------------------------------------------------------===//
368 def : InstRW<[FXU, LSU, Lat5], (instregex "O(G|Y)?$")>;
369 def : InstRW<[FXU], (instregex "OGR(K)?$")>;
370 def : InstRW<[FXU, LSU, Lat5], (instregex "OI(Y)?$")>;
371 def : InstRW<[FXU], (instregex "OI(FMux|HMux|LMux)$")>;
372 def : InstRW<[FXU], (instregex "OIHF(64)?$")>;
373 def : InstRW<[FXU], (instregex "OIHH(64)?$")>;
374 def : InstRW<[FXU], (instregex "OIHL(64)?$")>;
375 def : InstRW<[FXU], (instregex "OILF(64)?$")>;
376 def : InstRW<[FXU], (instregex "OILH(64)?$")>;
377 def : InstRW<[FXU], (instregex "OILL(64)?$")>;
378 def : InstRW<[FXU], (instregex "OR(K)?$")>;
379 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "OC$")>;
381 //===----------------------------------------------------------------------===//
383 //===----------------------------------------------------------------------===//
385 def : InstRW<[FXU, LSU, Lat5], (instregex "X(G|Y)?$")>;
386 def : InstRW<[FXU, LSU, Lat5], (instregex "XI(Y)?$")>;
387 def : InstRW<[FXU], (instregex "XIFMux$")>;
388 def : InstRW<[FXU], (instregex "XGR(K)?$")>;
389 def : InstRW<[FXU], (instregex "XIHF(64)?$")>;
390 def : InstRW<[FXU], (instregex "XILF(64)?$")>;
391 def : InstRW<[FXU], (instregex "XR(K)?$")>;
392 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "XC$")>;
394 //===----------------------------------------------------------------------===//
396 //===----------------------------------------------------------------------===//
398 def : InstRW<[FXU, LSU, Lat10], (instregex "MS(GF|Y)?$")>;
399 def : InstRW<[FXU, Lat6], (instregex "MS(R|FI)$")>;
400 def : InstRW<[FXU, LSU, Lat12], (instregex "MSG$")>;
401 def : InstRW<[FXU, Lat8], (instregex "MSGR$")>;
402 def : InstRW<[FXU, Lat6], (instregex "MSGF(I|R)$")>;
403 def : InstRW<[FXU, LSU, Lat15, GroupAlone], (instregex "MLG$")>;
404 def : InstRW<[FXU, Lat9, GroupAlone], (instregex "MLGR$")>;
405 def : InstRW<[FXU, Lat5], (instregex "MGHI$")>;
406 def : InstRW<[FXU, Lat5], (instregex "MHI$")>;
407 def : InstRW<[FXU, LSU, Lat9], (instregex "MH(Y)?$")>;
409 //===----------------------------------------------------------------------===//
410 // Division and remainder
411 //===----------------------------------------------------------------------===//
413 def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
414 (instregex "DSG(F)?R$")>;
415 def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, Lat30, GroupAlone],
416 (instregex "DSG(F)?$")>;
417 def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
418 (instregex "DL(G)?R$")>;
419 def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
420 (instregex "DL(G)?$")>;
422 //===----------------------------------------------------------------------===//
424 //===----------------------------------------------------------------------===//
426 def : InstRW<[FXU], (instregex "SLL(G|K)?$")>;
427 def : InstRW<[FXU], (instregex "SRL(G|K)?$")>;
428 def : InstRW<[FXU], (instregex "SRA(G|K)?$")>;
429 def : InstRW<[FXU], (instregex "SLA(K)?$")>;
432 def : InstRW<[FXU, LSU, Lat6], (instregex "RLL(G)?$")>;
435 def : InstRW<[FXU], (instregex "RISBG(N|32)?$")>;
436 def : InstRW<[FXU], (instregex "RISBH(G|H|L)$")>;
437 def : InstRW<[FXU], (instregex "RISBL(G|H|L)$")>;
438 def : InstRW<[FXU], (instregex "RISBMux$")>;
441 def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "R(N|O|X)SBG$")>;
443 //===----------------------------------------------------------------------===//
445 //===----------------------------------------------------------------------===//
447 def : InstRW<[FXU, LSU, Lat5], (instregex "C(G|Y|Mux|RL)?$")>;
448 def : InstRW<[FXU], (instregex "C(F|H)I(Mux)?$")>;
449 def : InstRW<[FXU], (instregex "CG(F|H)I$")>;
450 def : InstRW<[FXU, LSU, Lat5], (instregex "CG(HSI|RL)$")>;
451 def : InstRW<[FXU], (instregex "C(G)?R$")>;
452 def : InstRW<[FXU], (instregex "CIH$")>;
453 def : InstRW<[FXU, LSU, Lat5], (instregex "CH(F|SI)$")>;
454 def : InstRW<[FXU, LSU, Lat5], (instregex "CL(Y|Mux|FHSI)?$")>;
455 def : InstRW<[FXU], (instregex "CLFI(Mux)?$")>;
456 def : InstRW<[FXU, LSU, Lat5], (instregex "CLG(HRL|HSI)?$")>;
457 def : InstRW<[FXU, LSU, Lat5], (instregex "CLGF(RL)?$")>;
458 def : InstRW<[FXU], (instregex "CLGF(I|R)$")>;
459 def : InstRW<[FXU], (instregex "CLGR$")>;
460 def : InstRW<[FXU, LSU, Lat5], (instregex "CLGRL$")>;
461 def : InstRW<[FXU, LSU, Lat5], (instregex "CLH(F|RL|HSI)$")>;
462 def : InstRW<[FXU], (instregex "CLIH$")>;
463 def : InstRW<[FXU, LSU, Lat5], (instregex "CLI(Y)?$")>;
464 def : InstRW<[FXU], (instregex "CLR$")>;
465 def : InstRW<[FXU, LSU, Lat5], (instregex "CLRL$")>;
468 def : InstRW<[FXU, LSU, Lat6], (instregex "CH(Y|RL)?$")>;
469 def : InstRW<[FXU, LSU, Lat6], (instregex "CGH(RL)?$")>;
470 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "CHHSI$")>;
472 // Compare with sign extension (32 -> 64)
473 def : InstRW<[FXU, LSU, Lat6], (instregex "CGF(RL)?$")>;
474 def : InstRW<[FXU, Lat2], (instregex "CGFR$")>;
476 // Compare logical character
477 def : InstRW<[FXU, LSU, LSU, Lat9, GroupAlone], (instregex "CLC$")>;
479 def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CLST$")>;
482 def : InstRW<[FXU, LSU, Lat5], (instregex "TM(Y)?$")>;
483 def : InstRW<[FXU], (instregex "TM(H|L)Mux$")>;
484 def : InstRW<[FXU], (instregex "TMHH(64)?$")>;
485 def : InstRW<[FXU], (instregex "TMHL(64)?$")>;
486 def : InstRW<[FXU], (instregex "TMLH(64)?$")>;
487 def : InstRW<[FXU], (instregex "TMLL(64)?$")>;
489 //===----------------------------------------------------------------------===//
490 // Prefetch and execution hint
491 //===----------------------------------------------------------------------===//
493 def : InstRW<[LSU], (instregex "PFD(RL)?$")>;
494 def : InstRW<[LSU], (instregex "BP(R)?P$")>;
495 def : InstRW<[FXU], (instregex "NIAI$")>;
497 //===----------------------------------------------------------------------===//
499 //===----------------------------------------------------------------------===//
501 def : InstRW<[LSU, EndGroup], (instregex "Serialize$")>;
503 def : InstRW<[FXU, LSU, Lat5], (instregex "LAA(G)?$")>;
504 def : InstRW<[FXU, LSU, Lat5], (instregex "LAAL(G)?$")>;
505 def : InstRW<[FXU, LSU, Lat5], (instregex "LAN(G)?$")>;
506 def : InstRW<[FXU, LSU, Lat5], (instregex "LAO(G)?$")>;
507 def : InstRW<[FXU, LSU, Lat5], (instregex "LAX(G)?$")>;
510 def : InstRW<[FXU, LSU, Lat5, EndGroup], (instregex "TS$")>;
513 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
515 // Compare double and swap
516 def : InstRW<[FXU, FXU, FXU, FXU, FXU, LSU, Lat10, GroupAlone],
517 (instregex "CDS(Y)?$")>;
518 def : InstRW<[FXU, FXU, FXU, FXU, FXU, FXU, LSU, LSU, Lat12, GroupAlone],
519 (instregex "CDSG$")>;
521 // Compare and swap and store
522 def : InstRW<[FXU, Lat30, GroupAlone], (instregex "CSST$")>;
524 // Perform locked operation
525 def : InstRW<[LSU, Lat30, GroupAlone], (instregex "PLO$")>;
527 // Load/store pair from/to quadword
528 def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPQ$")>;
529 def : InstRW<[FXU, FXU, LSU, LSU, Lat6, GroupAlone], (instregex "STPQ$")>;
531 // Load pair disjoint
532 def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPD(G)?$")>;
534 //===----------------------------------------------------------------------===//
536 //===----------------------------------------------------------------------===//
538 // Extract/set/copy access register
539 def : InstRW<[LSU], (instregex "(EAR|SAR|CPYA)$")>;
541 // Load address extended
542 def : InstRW<[LSU, FXU, Lat5, GroupAlone], (instregex "LAE(Y)?$")>;
544 // Load/store access multiple (not modeled precisely)
545 def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(L|ST)AM(Y)?$")>;
547 //===----------------------------------------------------------------------===//
548 // Program mask and addressing mode
549 //===----------------------------------------------------------------------===//
551 // Insert Program Mask
552 def : InstRW<[FXU, Lat3, EndGroup], (instregex "IPM$")>;
555 def : InstRW<[LSU, EndGroup], (instregex "SPM$")>;
558 def : InstRW<[FXU, FXU, LSU, Lat8, GroupAlone], (instregex "BAL(R)?$")>;
560 // Test addressing mode
561 def : InstRW<[FXU], (instregex "TAM$")>;
563 // Set addressing mode
564 def : InstRW<[LSU, EndGroup], (instregex "SAM(24|31|64)$")>;
566 // Branch (and save) and set mode.
567 def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BSM$")>;
568 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "BASSM$")>;
570 //===----------------------------------------------------------------------===//
571 // Transactional execution
572 //===----------------------------------------------------------------------===//
575 def : InstRW<[LSU, LSU, FXU, FXU, FXU, FXU, FXU, Lat15, GroupAlone],
576 (instregex "TBEGIN(C|_nofloat)?$")>;
579 def : InstRW<[LSU, GroupAlone], (instregex "TEND$")>;
582 def : InstRW<[LSU, GroupAlone], (instregex "TABORT$")>;
584 // Extract Transaction Nesting Depth
585 def : InstRW<[FXU], (instregex "ETND$")>;
587 // Nontransactional store
588 def : InstRW<[FXU, LSU, Lat5], (instregex "NTSTG$")>;
590 //===----------------------------------------------------------------------===//
592 //===----------------------------------------------------------------------===//
594 def : InstRW<[FXU], (instregex "PPA$")>;
596 //===----------------------------------------------------------------------===//
597 // Miscellaneous Instructions.
598 //===----------------------------------------------------------------------===//
601 def : InstRW<[FXU, Lat7, GroupAlone], (instregex "FLOGR$")>;
604 def : InstRW<[FXU, Lat3], (instregex "POPCNT$")>;
607 def : InstRW<[FXU], (instregex "AEXT128_64$")>;
608 def : InstRW<[FXU], (instregex "ZEXT128_(32|64)$")>;
610 // String instructions
611 def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>;
614 def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
617 def : InstRW<[FXU, Lat5, LSU], (instregex "ECTG$")>;
620 def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
623 def : InstRW<[FXU, Lat30], (instregex "PR$")>;
626 def : InstRW<[FXU, LSU, LSU, Lat9, GroupAlone], (instregex "STCK(F)?$")>;
627 def : InstRW<[LSU, LSU, LSU, LSU, FXU, FXU, Lat20, GroupAlone],
628 (instregex "STCKE$")>;
629 def : InstRW<[FXU, LSU, Lat5], (instregex "STFLE$")>;
630 def : InstRW<[FXU, Lat30], (instregex "SVC$")>;
632 // Store real address
633 def : InstRW<[FXU, LSU, Lat5], (instregex "STRAG$")>;
635 //===----------------------------------------------------------------------===//
636 // .insn directive instructions
637 //===----------------------------------------------------------------------===//
639 // An "empty" sched-class will be assigned instead of the "invalid sched-class".
640 // getNumDecoderSlots() will then return 1 instead of 0.
641 def : InstRW<[], (instregex "Insn.*")>;
644 // ----------------------------- Floating point ----------------------------- //
646 //===----------------------------------------------------------------------===//
647 // FP: Select instructions
648 //===----------------------------------------------------------------------===//
650 def : InstRW<[FXU], (instregex "SelectF(32|64|128)$")>;
651 def : InstRW<[FXU], (instregex "CondStoreF32(Inv)?$")>;
652 def : InstRW<[FXU], (instregex "CondStoreF64(Inv)?$")>;
654 //===----------------------------------------------------------------------===//
655 // FP: Move instructions
656 //===----------------------------------------------------------------------===//
659 def : InstRW<[FXU], (instregex "LZ(DR|ER)$")>;
660 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LZXR$")>;
663 def : InstRW<[FXU], (instregex "LER$")>;
664 def : InstRW<[FXU], (instregex "LD(R|R32|GR)$")>;
665 def : InstRW<[FXU, Lat3], (instregex "LGDR$")>;
666 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LXR$")>;
669 def : InstRW<[FPU], (instregex "LT(D|E)BR$")>;
670 def : InstRW<[FPU], (instregex "LTEBRCompare(_VecPseudo)?$")>;
671 def : InstRW<[FPU], (instregex "LTDBRCompare(_VecPseudo)?$")>;
672 def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "LTXBR$")>;
673 def : InstRW<[FPU2, FPU2, Lat9, GroupAlone],
674 (instregex "LTXBRCompare(_VecPseudo)?$")>;
677 def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRd(d|s)$")>;
678 def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRs(d|s)$")>;
680 //===----------------------------------------------------------------------===//
681 // FP: Load instructions
682 //===----------------------------------------------------------------------===//
684 def : InstRW<[LSU], (instregex "LE(Y)?$")>;
685 def : InstRW<[LSU], (instregex "LD(Y|E32)?$")>;
686 def : InstRW<[LSU], (instregex "LX$")>;
688 //===----------------------------------------------------------------------===//
689 // FP: Store instructions
690 //===----------------------------------------------------------------------===//
692 def : InstRW<[FXU, LSU, Lat7], (instregex "STD(Y)?$")>;
693 def : InstRW<[FXU, LSU, Lat7], (instregex "STE(Y)?$")>;
694 def : InstRW<[FXU, LSU, Lat5], (instregex "STX$")>;
696 //===----------------------------------------------------------------------===//
697 // FP: Conversion instructions
698 //===----------------------------------------------------------------------===//
701 def : InstRW<[FPU], (instregex "LEDBR(A)?$")>;
702 def : InstRW<[FPU, FPU, Lat20], (instregex "LEXBR(A)?$")>;
703 def : InstRW<[FPU, FPU, Lat20], (instregex "LDXBR(A)?$")>;
706 def : InstRW<[FPU, LSU, Lat12], (instregex "LDEB$")>;
707 def : InstRW<[FPU], (instregex "LDEBR$")>;
708 def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "LX(D|E)B$")>;
709 def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "LX(D|E)BR$")>;
711 // Convert from fixed / logical
712 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CE(F|G)BR(A?)$")>;
713 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CD(F|G)BR(A?)$")>;
714 def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CX(F|G)BR(A?)$")>;
715 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CEL(F|G)BR$")>;
716 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CDL(F|G)BR$")>;
717 def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CXL(F|G)BR$")>;
719 // Convert to fixed / logical
720 def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CF(E|D)BR(A?)$")>;
721 def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CG(E|D)BR(A?)$")>;
722 def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "C(F|G)XBR(A?)$")>;
723 def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLF(E|D)BR$")>;
724 def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLG(E|D)BR$")>;
725 def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "CL(F|G)XBR$")>;
727 //===----------------------------------------------------------------------===//
728 // FP: Unary arithmetic
729 //===----------------------------------------------------------------------===//
731 // Load Complement / Negative / Positive
732 def : InstRW<[FPU], (instregex "L(C|N|P)DBR$")>;
733 def : InstRW<[FPU], (instregex "L(C|N|P)EBR$")>;
734 def : InstRW<[FXU], (instregex "LCDFR(_32)?$")>;
735 def : InstRW<[FXU], (instregex "LNDFR(_32)?$")>;
736 def : InstRW<[FXU], (instregex "LPDFR(_32)?$")>;
737 def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "L(C|N|P)XBR$")>;
740 def : InstRW<[FPU, LSU, Lat30], (instregex "SQ(E|D)B$")>;
741 def : InstRW<[FPU, Lat30], (instregex "SQ(E|D)BR$")>;
742 def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "SQXBR$")>;
745 def : InstRW<[FPU], (instregex "FIEBR(A)?$")>;
746 def : InstRW<[FPU], (instregex "FIDBR(A)?$")>;
747 def : InstRW<[FPU2, FPU2, Lat15, GroupAlone], (instregex "FIXBR(A)?$")>;
749 //===----------------------------------------------------------------------===//
750 // FP: Binary arithmetic
751 //===----------------------------------------------------------------------===//
754 def : InstRW<[FPU, LSU, Lat12], (instregex "A(E|D)B$")>;
755 def : InstRW<[FPU], (instregex "A(E|D)BR$")>;
756 def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "AXBR$")>;
759 def : InstRW<[FPU, LSU, Lat12], (instregex "S(E|D)B$")>;
760 def : InstRW<[FPU], (instregex "S(E|D)BR$")>;
761 def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "SXBR$")>;
764 def : InstRW<[FPU, LSU, Lat12], (instregex "M(D|DE|EE)B$")>;
765 def : InstRW<[FPU], (instregex "M(D|DE|EE)BR$")>;
766 def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "MXDB$")>;
767 def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "MXDBR$")>;
768 def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "MXBR$")>;
770 // Multiply and add / subtract
771 def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)EB$")>;
772 def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)EBR$")>;
773 def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)DB$")>;
774 def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)DBR$")>;
777 def : InstRW<[FPU, LSU, Lat30], (instregex "D(E|D)B$")>;
778 def : InstRW<[FPU, Lat30], (instregex "D(E|D)BR$")>;
779 def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "DXBR$")>;
781 //===----------------------------------------------------------------------===//
783 //===----------------------------------------------------------------------===//
786 def : InstRW<[FPU, LSU, Lat12], (instregex "C(E|D)B$")>;
787 def : InstRW<[FPU], (instregex "C(E|D)BR$")>;
788 def : InstRW<[FPU, FPU, Lat30], (instregex "CXBR$")>;
791 def : InstRW<[FPU, LSU, Lat15], (instregex "TC(E|D)B$")>;
792 def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "TCXB$")>;
794 //===----------------------------------------------------------------------===//
795 // FP: Floating-point control register instructions
796 //===----------------------------------------------------------------------===//
798 def : InstRW<[FXU, LSU, Lat4, GroupAlone], (instregex "EFPC$")>;
799 def : InstRW<[LSU, Lat3, GroupAlone], (instregex "SFPC$")>;
800 def : InstRW<[LSU, LSU, Lat6, GroupAlone], (instregex "LFPC$")>;
801 def : InstRW<[LSU, Lat3, GroupAlone], (instregex "STFPC$")>;
802 def : InstRW<[FXU, Lat30, GroupAlone], (instregex "SFASR$")>;
803 def : InstRW<[FXU, LSU, Lat30, GroupAlone], (instregex "LFAS$")>;
804 def : InstRW<[FXU, Lat2, GroupAlone], (instregex "SRNM(B|T)?$")>;