1 //==- WebAssemblyDisassembler.cpp - Disassembler for WebAssembly -*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file is part of the WebAssembly Disassembler.
13 /// It contains code to translate the data produced by the decoder into
16 //===----------------------------------------------------------------------===//
18 #include "WebAssembly.h"
19 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCSymbol.h"
26 #include "llvm/Support/Endian.h"
27 #include "llvm/Support/TargetRegistry.h"
30 #define DEBUG_TYPE "wasm-disassembler"
33 class WebAssemblyDisassembler final : public MCDisassembler {
34 std::unique_ptr<const MCInstrInfo> MCII;
36 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
37 ArrayRef<uint8_t> Bytes, uint64_t Address,
39 raw_ostream &CStream) const override;
42 WebAssemblyDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
43 std::unique_ptr<const MCInstrInfo> MCII)
44 : MCDisassembler(STI, Ctx), MCII(std::move(MCII)) {}
46 } // end anonymous namespace
48 static MCDisassembler *createWebAssemblyDisassembler(const Target &T,
49 const MCSubtargetInfo &STI,
51 std::unique_ptr<const MCInstrInfo> MCII(T.createMCInstrInfo());
52 return new WebAssemblyDisassembler(STI, Ctx, std::move(MCII));
55 extern "C" void LLVMInitializeWebAssemblyDisassembler() {
56 // Register the disassembler for each target.
57 TargetRegistry::RegisterMCDisassembler(getTheWebAssemblyTarget32(),
58 createWebAssemblyDisassembler);
59 TargetRegistry::RegisterMCDisassembler(getTheWebAssemblyTarget64(),
60 createWebAssemblyDisassembler);
63 MCDisassembler::DecodeStatus WebAssemblyDisassembler::getInstruction(
64 MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t /*Address*/,
65 raw_ostream &OS, raw_ostream &CS) const {
70 if (Pos + sizeof(uint64_t) > Bytes.size())
71 return MCDisassembler::Fail;
72 uint64_t Opcode = support::endian::read64le(Bytes.data() + Pos);
73 Pos += sizeof(uint64_t);
75 if (Opcode >= WebAssembly::INSTRUCTION_LIST_END)
76 return MCDisassembler::Fail;
79 const MCInstrDesc &Desc = MCII->get(Opcode);
80 unsigned NumFixedOperands = Desc.NumOperands;
82 // If it's variadic, read the number of extra operands.
83 unsigned NumExtraOperands = 0;
84 if (Desc.isVariadic()) {
85 if (Pos + sizeof(uint64_t) > Bytes.size())
86 return MCDisassembler::Fail;
87 NumExtraOperands = support::endian::read64le(Bytes.data() + Pos);
88 Pos += sizeof(uint64_t);
91 // Read the fixed operands. These are described by the MCInstrDesc.
92 for (unsigned i = 0; i < NumFixedOperands; ++i) {
93 const MCOperandInfo &Info = Desc.OpInfo[i];
94 switch (Info.OperandType) {
95 case MCOI::OPERAND_IMMEDIATE:
96 case WebAssembly::OPERAND_LOCAL:
97 case WebAssembly::OPERAND_P2ALIGN:
98 case WebAssembly::OPERAND_BASIC_BLOCK: {
99 if (Pos + sizeof(uint64_t) > Bytes.size())
100 return MCDisassembler::Fail;
101 uint64_t Imm = support::endian::read64le(Bytes.data() + Pos);
102 Pos += sizeof(uint64_t);
103 MI.addOperand(MCOperand::createImm(Imm));
106 case MCOI::OPERAND_REGISTER: {
107 if (Pos + sizeof(uint64_t) > Bytes.size())
108 return MCDisassembler::Fail;
109 uint64_t Reg = support::endian::read64le(Bytes.data() + Pos);
110 Pos += sizeof(uint64_t);
111 MI.addOperand(MCOperand::createReg(Reg));
114 case WebAssembly::OPERAND_F32IMM:
115 case WebAssembly::OPERAND_F64IMM: {
116 // TODO: MC converts all floating point immediate operands to double.
117 // This is fine for numeric values, but may cause NaNs to change bits.
118 if (Pos + sizeof(uint64_t) > Bytes.size())
119 return MCDisassembler::Fail;
120 uint64_t Bits = support::endian::read64le(Bytes.data() + Pos);
121 Pos += sizeof(uint64_t);
123 memcpy(&Imm, &Bits, sizeof(Imm));
124 MI.addOperand(MCOperand::createFPImm(Imm));
128 llvm_unreachable("unimplemented operand kind");
132 // Read the extra operands.
133 assert(NumExtraOperands == 0 || Desc.isVariadic());
134 for (unsigned i = 0; i < NumExtraOperands; ++i) {
135 if (Pos + sizeof(uint64_t) > Bytes.size())
136 return MCDisassembler::Fail;
137 if (Desc.TSFlags & WebAssemblyII::VariableOpIsImmediate) {
138 // Decode extra immediate operands.
139 uint64_t Imm = support::endian::read64le(Bytes.data() + Pos);
140 MI.addOperand(MCOperand::createImm(Imm));
142 // Decode extra register operands.
143 uint64_t Reg = support::endian::read64le(Bytes.data() + Pos);
144 MI.addOperand(MCOperand::createReg(Reg));
146 Pos += sizeof(uint64_t);
150 return MCDisassembler::Success;