1 //- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This is a target description file for the WebAssembly architecture,
12 /// which is also known as "wasm".
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Target-independent interfaces which we are implementing
18 //===----------------------------------------------------------------------===//
20 include "llvm/Target/Target.td"
22 //===----------------------------------------------------------------------===//
23 // WebAssembly Subtarget features.
24 //===----------------------------------------------------------------------===//
26 def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "true",
27 "Enable 128-bit SIMD">;
28 def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true",
30 def FeatureNontrappingFPToInt :
31 SubtargetFeature<"nontrapping-fptoint",
32 "HasNontrappingFPToInt", "true",
33 "Enable non-trapping float-to-int conversion operators">;
36 SubtargetFeature<"sign-ext",
38 "Enable sign extension operators">;
40 def FeatureExceptionHandling :
41 SubtargetFeature<"exception-handling", "HasExceptionHandling", "true",
42 "Enable Wasm exception handling">;
44 //===----------------------------------------------------------------------===//
46 //===----------------------------------------------------------------------===//
48 //===----------------------------------------------------------------------===//
49 // Register File Description
50 //===----------------------------------------------------------------------===//
52 include "WebAssemblyRegisterInfo.td"
54 //===----------------------------------------------------------------------===//
55 // Instruction Descriptions
56 //===----------------------------------------------------------------------===//
58 include "WebAssemblyInstrInfo.td"
60 def WebAssemblyInstrInfo : InstrInfo;
62 //===----------------------------------------------------------------------===//
63 // WebAssembly Processors supported.
64 //===----------------------------------------------------------------------===//
66 // Minimal Viable Product.
67 def : ProcessorModel<"mvp", NoSchedModel, []>;
69 // Generic processor: latest stable version.
70 def : ProcessorModel<"generic", NoSchedModel, []>;
72 // Latest and greatest experimental version of WebAssembly. Bugs included!
73 def : ProcessorModel<"bleeding-edge", NoSchedModel,
74 [FeatureSIMD128, FeatureAtomics]>;
76 //===----------------------------------------------------------------------===//
78 //===----------------------------------------------------------------------===//
80 def WebAssemblyAsmParser : AsmParser {
81 // The physical register names are not in the binary format or asm text
82 let ShouldEmitMatchRegisterName = 0;
85 def WebAssemblyAsmWriter : AsmWriter {
86 string AsmWriterClassName = "InstPrinter";
87 int PassSubtarget = 0;
89 bit isMCAsmWriter = 1;
92 def WebAssembly : Target {
93 let InstructionSet = WebAssemblyInstrInfo;
94 let AssemblyParsers = [WebAssemblyAsmParser];
95 let AssemblyWriters = [WebAssemblyAsmWriter];