1 //=- WebAssemblyISelLowering.cpp - WebAssembly DAG Lowering Implementation -==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file implements the WebAssemblyTargetLowering class.
13 //===----------------------------------------------------------------------===//
15 #include "WebAssemblyISelLowering.h"
16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17 #include "WebAssemblyMachineFunctionInfo.h"
18 #include "WebAssemblySubtarget.h"
19 #include "WebAssemblyTargetMachine.h"
20 #include "llvm/CodeGen/Analysis.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/IR/DiagnosticInfo.h"
27 #include "llvm/IR/DiagnosticPrinter.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
36 #define DEBUG_TYPE "wasm-lower"
38 WebAssemblyTargetLowering::WebAssemblyTargetLowering(
39 const TargetMachine &TM, const WebAssemblySubtarget &STI)
40 : TargetLowering(TM), Subtarget(&STI) {
41 auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32;
43 // Booleans always contain 0 or 1.
44 setBooleanContents(ZeroOrOneBooleanContent);
45 // WebAssembly does not produce floating-point exceptions on normal floating
47 setHasFloatingPointExceptions(false);
48 // We don't know the microarchitecture here, so just reduce register pressure.
49 setSchedulingPreference(Sched::RegPressure);
50 // Tell ISel that we have a stack pointer.
51 setStackPointerRegisterToSaveRestore(
52 Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32);
53 // Set up the register classes.
54 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass);
55 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass);
56 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass);
57 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass);
58 if (Subtarget->hasSIMD128()) {
59 addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass);
60 addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass);
61 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass);
62 addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass);
64 // Compute derived properties from the register classes.
65 computeRegisterProperties(Subtarget->getRegisterInfo());
67 setOperationAction(ISD::GlobalAddress, MVTPtr, Custom);
68 setOperationAction(ISD::ExternalSymbol, MVTPtr, Custom);
69 setOperationAction(ISD::JumpTable, MVTPtr, Custom);
70 setOperationAction(ISD::BlockAddress, MVTPtr, Custom);
71 setOperationAction(ISD::BRIND, MVT::Other, Custom);
73 // Take the default expansion for va_arg, va_copy, and va_end. There is no
74 // default action for va_start, so we do that custom.
75 setOperationAction(ISD::VASTART, MVT::Other, Custom);
76 setOperationAction(ISD::VAARG, MVT::Other, Expand);
77 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
78 setOperationAction(ISD::VAEND, MVT::Other, Expand);
80 for (auto T : {MVT::f32, MVT::f64}) {
81 // Don't expand the floating-point types to constant pools.
82 setOperationAction(ISD::ConstantFP, T, Legal);
83 // Expand floating-point comparisons.
84 for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE,
85 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE})
86 setCondCodeAction(CC, T, Expand);
87 // Expand floating-point library function operators.
88 for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM,
90 setOperationAction(Op, T, Expand);
91 // Note supported floating-point library function operators that otherwise
94 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT})
95 setOperationAction(Op, T, Legal);
96 // Support minnan and maxnan, which otherwise default to expand.
97 setOperationAction(ISD::FMINNAN, T, Legal);
98 setOperationAction(ISD::FMAXNAN, T, Legal);
99 // WebAssembly currently has no builtin f16 support.
100 setOperationAction(ISD::FP16_TO_FP, T, Expand);
101 setOperationAction(ISD::FP_TO_FP16, T, Expand);
102 setLoadExtAction(ISD::EXTLOAD, T, MVT::f16, Expand);
103 setTruncStoreAction(T, MVT::f16, Expand);
106 for (auto T : {MVT::i32, MVT::i64}) {
107 // Expand unavailable integer operations.
109 {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI,
110 ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS,
111 ISD::SRA_PARTS, ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC,
113 setOperationAction(Op, T, Expand);
117 // As a special case, these operators use the type to mean the type to
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
120 if (!Subtarget->hasAtomics()) {
121 // The Atomics feature includes signext intructions.
122 for (auto T : {MVT::i8, MVT::i16, MVT::i32})
123 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
126 // Dynamic stack allocation: use the default expansion.
127 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
128 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
129 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVTPtr, Expand);
131 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
132 setOperationAction(ISD::CopyToReg, MVT::Other, Custom);
134 // Expand these forms; we pattern-match the forms that we can handle in isel.
135 for (auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64})
136 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
137 setOperationAction(Op, T, Expand);
139 // We have custom switch handling.
140 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
142 // WebAssembly doesn't have:
143 // - Floating-point extending loads.
144 // - Floating-point truncating stores.
145 // - i1 extending loads.
146 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
147 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
148 for (auto T : MVT::integer_valuetypes())
149 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
150 setLoadExtAction(Ext, T, MVT::i1, Promote);
152 // Trap lowers to wasm unreachable
153 setOperationAction(ISD::TRAP, MVT::Other, Legal);
155 setMaxAtomicSizeInBitsSupported(64);
158 FastISel *WebAssemblyTargetLowering::createFastISel(
159 FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const {
160 return WebAssembly::createFastISel(FuncInfo, LibInfo);
163 bool WebAssemblyTargetLowering::isOffsetFoldingLegal(
164 const GlobalAddressSDNode * /*GA*/) const {
165 // All offsets can be folded.
169 MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout & /*DL*/,
171 unsigned BitWidth = NextPowerOf2(VT.getSizeInBits() - 1);
172 if (BitWidth > 1 && BitWidth < 8) BitWidth = 8;
175 // The shift will be lowered to a libcall, and compiler-rt libcalls expect
176 // the count to be an i32.
178 assert(BitWidth >= Log2_32_Ceil(VT.getSizeInBits()) &&
179 "32-bit shift counts ought to be enough for anyone");
182 MVT Result = MVT::getIntegerVT(BitWidth);
183 assert(Result != MVT::INVALID_SIMPLE_VALUE_TYPE &&
184 "Unable to represent scalar shift amount type");
188 // Lower an fp-to-int conversion operator from the LLVM opcode, which has an
189 // undefined result on invalid/overflow, to the WebAssembly opcode, which
190 // traps on invalid/overflow.
191 static MachineBasicBlock *
195 MachineBasicBlock *BB,
196 const TargetInstrInfo &TII,
200 unsigned LoweredOpcode
202 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
204 unsigned OutReg = MI.getOperand(0).getReg();
205 unsigned InReg = MI.getOperand(1).getReg();
207 unsigned Abs = Float64 ? WebAssembly::ABS_F64 : WebAssembly::ABS_F32;
208 unsigned FConst = Float64 ? WebAssembly::CONST_F64 : WebAssembly::CONST_F32;
209 unsigned LT = Float64 ? WebAssembly::LT_F64 : WebAssembly::LT_F32;
210 unsigned GE = Float64 ? WebAssembly::GE_F64 : WebAssembly::GE_F32;
211 unsigned IConst = Int64 ? WebAssembly::CONST_I64 : WebAssembly::CONST_I32;
212 unsigned Eqz = WebAssembly::EQZ_I32;
213 unsigned And = WebAssembly::AND_I32;
214 int64_t Limit = Int64 ? INT64_MIN : INT32_MIN;
215 int64_t Substitute = IsUnsigned ? 0 : Limit;
216 double CmpVal = IsUnsigned ? -(double)Limit * 2.0 : -(double)Limit;
217 auto &Context = BB->getParent()->getFunction().getContext();
218 Type *Ty = Float64 ? Type::getDoubleTy(Context) : Type::getFloatTy(Context);
220 const BasicBlock *LLVM_BB = BB->getBasicBlock();
221 MachineFunction *F = BB->getParent();
222 MachineBasicBlock *TrueMBB = F->CreateMachineBasicBlock(LLVM_BB);
223 MachineBasicBlock *FalseMBB = F->CreateMachineBasicBlock(LLVM_BB);
224 MachineBasicBlock *DoneMBB = F->CreateMachineBasicBlock(LLVM_BB);
226 MachineFunction::iterator It = ++BB->getIterator();
227 F->insert(It, FalseMBB);
228 F->insert(It, TrueMBB);
229 F->insert(It, DoneMBB);
231 // Transfer the remainder of BB and its successor edges to DoneMBB.
232 DoneMBB->splice(DoneMBB->begin(), BB,
233 std::next(MachineBasicBlock::iterator(MI)),
235 DoneMBB->transferSuccessorsAndUpdatePHIs(BB);
237 BB->addSuccessor(TrueMBB);
238 BB->addSuccessor(FalseMBB);
239 TrueMBB->addSuccessor(DoneMBB);
240 FalseMBB->addSuccessor(DoneMBB);
242 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg;
243 Tmp0 = MRI.createVirtualRegister(MRI.getRegClass(InReg));
244 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg));
245 CmpReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
246 EqzReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
247 FalseReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg));
248 TrueReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg));
250 MI.eraseFromParent();
251 // For signed numbers, we can do a single comparison to determine whether
252 // fabs(x) is within range.
256 BuildMI(BB, DL, TII.get(Abs), Tmp0)
259 BuildMI(BB, DL, TII.get(FConst), Tmp1)
260 .addFPImm(cast<ConstantFP>(ConstantFP::get(Ty, CmpVal)));
261 BuildMI(BB, DL, TII.get(LT), CmpReg)
265 // For unsigned numbers, we have to do a separate comparison with zero.
267 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg));
268 unsigned SecondCmpReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
269 unsigned AndReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
270 BuildMI(BB, DL, TII.get(FConst), Tmp1)
271 .addFPImm(cast<ConstantFP>(ConstantFP::get(Ty, 0.0)));
272 BuildMI(BB, DL, TII.get(GE), SecondCmpReg)
275 BuildMI(BB, DL, TII.get(And), AndReg)
277 .addReg(SecondCmpReg);
281 BuildMI(BB, DL, TII.get(Eqz), EqzReg)
284 // Create the CFG diamond to select between doing the conversion or using
285 // the substitute value.
286 BuildMI(BB, DL, TII.get(WebAssembly::BR_IF))
289 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg)
291 BuildMI(FalseMBB, DL, TII.get(WebAssembly::BR))
293 BuildMI(TrueMBB, DL, TII.get(IConst), TrueReg)
295 BuildMI(*DoneMBB, DoneMBB->begin(), DL, TII.get(TargetOpcode::PHI), OutReg)
305 WebAssemblyTargetLowering::EmitInstrWithCustomInserter(
307 MachineBasicBlock *BB
309 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
310 DebugLoc DL = MI.getDebugLoc();
312 switch (MI.getOpcode()) {
313 default: llvm_unreachable("Unexpected instr type to insert");
314 case WebAssembly::FP_TO_SINT_I32_F32:
315 return LowerFPToInt(MI, DL, BB, TII, false, false, false,
316 WebAssembly::I32_TRUNC_S_F32);
317 case WebAssembly::FP_TO_UINT_I32_F32:
318 return LowerFPToInt(MI, DL, BB, TII, true, false, false,
319 WebAssembly::I32_TRUNC_U_F32);
320 case WebAssembly::FP_TO_SINT_I64_F32:
321 return LowerFPToInt(MI, DL, BB, TII, false, true, false,
322 WebAssembly::I64_TRUNC_S_F32);
323 case WebAssembly::FP_TO_UINT_I64_F32:
324 return LowerFPToInt(MI, DL, BB, TII, true, true, false,
325 WebAssembly::I64_TRUNC_U_F32);
326 case WebAssembly::FP_TO_SINT_I32_F64:
327 return LowerFPToInt(MI, DL, BB, TII, false, false, true,
328 WebAssembly::I32_TRUNC_S_F64);
329 case WebAssembly::FP_TO_UINT_I32_F64:
330 return LowerFPToInt(MI, DL, BB, TII, true, false, true,
331 WebAssembly::I32_TRUNC_U_F64);
332 case WebAssembly::FP_TO_SINT_I64_F64:
333 return LowerFPToInt(MI, DL, BB, TII, false, true, true,
334 WebAssembly::I64_TRUNC_S_F64);
335 case WebAssembly::FP_TO_UINT_I64_F64:
336 return LowerFPToInt(MI, DL, BB, TII, true, true, true,
337 WebAssembly::I64_TRUNC_U_F64);
338 llvm_unreachable("Unexpected instruction to emit with custom inserter");
342 const char *WebAssemblyTargetLowering::getTargetNodeName(
343 unsigned Opcode) const {
344 switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
345 case WebAssemblyISD::FIRST_NUMBER:
347 #define HANDLE_NODETYPE(NODE) \
348 case WebAssemblyISD::NODE: \
349 return "WebAssemblyISD::" #NODE;
350 #include "WebAssemblyISD.def"
351 #undef HANDLE_NODETYPE
356 std::pair<unsigned, const TargetRegisterClass *>
357 WebAssemblyTargetLowering::getRegForInlineAsmConstraint(
358 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
359 // First, see if this is a constraint that directly corresponds to a
360 // WebAssembly register class.
361 if (Constraint.size() == 1) {
362 switch (Constraint[0]) {
364 assert(VT != MVT::iPTR && "Pointer MVT not expected here");
365 if (Subtarget->hasSIMD128() && VT.isVector()) {
366 if (VT.getSizeInBits() == 128)
367 return std::make_pair(0U, &WebAssembly::V128RegClass);
369 if (VT.isInteger() && !VT.isVector()) {
370 if (VT.getSizeInBits() <= 32)
371 return std::make_pair(0U, &WebAssembly::I32RegClass);
372 if (VT.getSizeInBits() <= 64)
373 return std::make_pair(0U, &WebAssembly::I64RegClass);
381 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
384 bool WebAssemblyTargetLowering::isCheapToSpeculateCttz() const {
385 // Assume ctz is a relatively cheap operation.
389 bool WebAssemblyTargetLowering::isCheapToSpeculateCtlz() const {
390 // Assume clz is a relatively cheap operation.
394 bool WebAssemblyTargetLowering::isLegalAddressingMode(const DataLayout &DL,
398 Instruction *I) const {
399 // WebAssembly offsets are added as unsigned without wrapping. The
400 // isLegalAddressingMode gives us no way to determine if wrapping could be
401 // happening, so we approximate this by accepting only non-negative offsets.
402 if (AM.BaseOffs < 0) return false;
404 // WebAssembly has no scale register operands.
405 if (AM.Scale != 0) return false;
407 // Everything else is legal.
411 bool WebAssemblyTargetLowering::allowsMisalignedMemoryAccesses(
412 EVT /*VT*/, unsigned /*AddrSpace*/, unsigned /*Align*/, bool *Fast) const {
413 // WebAssembly supports unaligned accesses, though it should be declared
414 // with the p2align attribute on loads and stores which do so, and there
415 // may be a performance impact. We tell LLVM they're "fast" because
416 // for the kinds of things that LLVM uses this for (merging adjacent stores
417 // of constants, etc.), WebAssembly implementations will either want the
418 // unaligned access or they'll split anyway.
419 if (Fast) *Fast = true;
423 bool WebAssemblyTargetLowering::isIntDivCheap(EVT VT,
424 AttributeList Attr) const {
425 // The current thinking is that wasm engines will perform this optimization,
426 // so we can save on code size.
430 //===----------------------------------------------------------------------===//
431 // WebAssembly Lowering private implementation.
432 //===----------------------------------------------------------------------===//
434 //===----------------------------------------------------------------------===//
436 //===----------------------------------------------------------------------===//
438 static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *msg) {
439 MachineFunction &MF = DAG.getMachineFunction();
440 DAG.getContext()->diagnose(
441 DiagnosticInfoUnsupported(MF.getFunction(), msg, DL.getDebugLoc()));
444 // Test whether the given calling convention is supported.
445 static bool CallingConvSupported(CallingConv::ID CallConv) {
446 // We currently support the language-independent target-independent
447 // conventions. We don't yet have a way to annotate calls with properties like
448 // "cold", and we don't have any call-clobbered registers, so these are mostly
449 // all handled the same.
450 return CallConv == CallingConv::C || CallConv == CallingConv::Fast ||
451 CallConv == CallingConv::Cold ||
452 CallConv == CallingConv::PreserveMost ||
453 CallConv == CallingConv::PreserveAll ||
454 CallConv == CallingConv::CXX_FAST_TLS;
457 SDValue WebAssemblyTargetLowering::LowerCall(
458 CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const {
459 SelectionDAG &DAG = CLI.DAG;
461 SDValue Chain = CLI.Chain;
462 SDValue Callee = CLI.Callee;
463 MachineFunction &MF = DAG.getMachineFunction();
464 auto Layout = MF.getDataLayout();
466 CallingConv::ID CallConv = CLI.CallConv;
467 if (!CallingConvSupported(CallConv))
469 "WebAssembly doesn't support language-specific or target-specific "
470 "calling conventions yet");
471 if (CLI.IsPatchPoint)
472 fail(DL, DAG, "WebAssembly doesn't support patch point yet");
474 // WebAssembly doesn't currently support explicit tail calls. If they are
475 // required, fail. Otherwise, just disable them.
476 if ((CallConv == CallingConv::Fast && CLI.IsTailCall &&
477 MF.getTarget().Options.GuaranteedTailCallOpt) ||
478 (CLI.CS && CLI.CS.isMustTailCall()))
479 fail(DL, DAG, "WebAssembly doesn't support tail call yet");
480 CLI.IsTailCall = false;
482 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
484 fail(DL, DAG, "WebAssembly doesn't support more than 1 returned value yet");
486 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
487 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
488 for (unsigned i = 0; i < Outs.size(); ++i) {
489 const ISD::OutputArg &Out = Outs[i];
490 SDValue &OutVal = OutVals[i];
491 if (Out.Flags.isNest())
492 fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
493 if (Out.Flags.isInAlloca())
494 fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
495 if (Out.Flags.isInConsecutiveRegs())
496 fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
497 if (Out.Flags.isInConsecutiveRegsLast())
498 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
499 if (Out.Flags.isByVal() && Out.Flags.getByValSize() != 0) {
500 auto &MFI = MF.getFrameInfo();
501 int FI = MFI.CreateStackObject(Out.Flags.getByValSize(),
502 Out.Flags.getByValAlign(),
505 DAG.getConstant(Out.Flags.getByValSize(), DL, MVT::i32);
506 SDValue FINode = DAG.getFrameIndex(FI, getPointerTy(Layout));
507 Chain = DAG.getMemcpy(
508 Chain, DL, FINode, OutVal, SizeNode, Out.Flags.getByValAlign(),
509 /*isVolatile*/ false, /*AlwaysInline=*/false,
510 /*isTailCall*/ false, MachinePointerInfo(), MachinePointerInfo());
515 bool IsVarArg = CLI.IsVarArg;
516 unsigned NumFixedArgs = CLI.NumFixedArgs;
518 auto PtrVT = getPointerTy(Layout);
520 // Analyze operands of the call, assigning locations to each operand.
521 SmallVector<CCValAssign, 16> ArgLocs;
522 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
525 // Outgoing non-fixed arguments are placed in a buffer. First
526 // compute their offsets and the total amount of buffer space needed.
528 make_range(OutVals.begin() + NumFixedArgs, OutVals.end())) {
529 EVT VT = Arg.getValueType();
530 assert(VT != MVT::iPTR && "Legalized args should be concrete");
531 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
532 unsigned Offset = CCInfo.AllocateStack(Layout.getTypeAllocSize(Ty),
533 Layout.getABITypeAlignment(Ty));
534 CCInfo.addLoc(CCValAssign::getMem(ArgLocs.size(), VT.getSimpleVT(),
535 Offset, VT.getSimpleVT(),
540 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
543 if (IsVarArg && NumBytes) {
544 // For non-fixed arguments, next emit stores to store the argument values
545 // to the stack buffer at the offsets computed above.
546 int FI = MF.getFrameInfo().CreateStackObject(NumBytes,
547 Layout.getStackAlignment(),
550 SmallVector<SDValue, 8> Chains;
552 make_range(OutVals.begin() + NumFixedArgs, OutVals.end())) {
553 assert(ArgLocs[ValNo].getValNo() == ValNo &&
554 "ArgLocs should remain in order and only hold varargs args");
555 unsigned Offset = ArgLocs[ValNo++].getLocMemOffset();
556 FINode = DAG.getFrameIndex(FI, getPointerTy(Layout));
557 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, FINode,
558 DAG.getConstant(Offset, DL, PtrVT));
559 Chains.push_back(DAG.getStore(
561 MachinePointerInfo::getFixedStack(MF, FI, Offset), 0));
564 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
565 } else if (IsVarArg) {
566 FINode = DAG.getIntPtrConstant(0, DL);
569 // Compute the operands for the CALLn node.
570 SmallVector<SDValue, 16> Ops;
571 Ops.push_back(Chain);
572 Ops.push_back(Callee);
574 // Add all fixed arguments. Note that for non-varargs calls, NumFixedArgs
576 Ops.append(OutVals.begin(),
577 IsVarArg ? OutVals.begin() + NumFixedArgs : OutVals.end());
578 // Add a pointer to the vararg buffer.
579 if (IsVarArg) Ops.push_back(FINode);
581 SmallVector<EVT, 8> InTys;
582 for (const auto &In : Ins) {
583 assert(!In.Flags.isByVal() && "byval is not valid for return values");
584 assert(!In.Flags.isNest() && "nest is not valid for return values");
585 if (In.Flags.isInAlloca())
586 fail(DL, DAG, "WebAssembly hasn't implemented inalloca return values");
587 if (In.Flags.isInConsecutiveRegs())
588 fail(DL, DAG, "WebAssembly hasn't implemented cons regs return values");
589 if (In.Flags.isInConsecutiveRegsLast())
591 "WebAssembly hasn't implemented cons regs last return values");
592 // Ignore In.getOrigAlign() because all our arguments are passed in
594 InTys.push_back(In.VT);
596 InTys.push_back(MVT::Other);
597 SDVTList InTyList = DAG.getVTList(InTys);
599 DAG.getNode(Ins.empty() ? WebAssemblyISD::CALL0 : WebAssemblyISD::CALL1,
604 InVals.push_back(Res);
605 Chain = Res.getValue(1);
611 bool WebAssemblyTargetLowering::CanLowerReturn(
612 CallingConv::ID /*CallConv*/, MachineFunction & /*MF*/, bool /*IsVarArg*/,
613 const SmallVectorImpl<ISD::OutputArg> &Outs,
614 LLVMContext & /*Context*/) const {
615 // WebAssembly can't currently handle returning tuples.
616 return Outs.size() <= 1;
619 SDValue WebAssemblyTargetLowering::LowerReturn(
620 SDValue Chain, CallingConv::ID CallConv, bool /*IsVarArg*/,
621 const SmallVectorImpl<ISD::OutputArg> &Outs,
622 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
623 SelectionDAG &DAG) const {
624 assert(Outs.size() <= 1 && "WebAssembly can only return up to one value");
625 if (!CallingConvSupported(CallConv))
626 fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
628 SmallVector<SDValue, 4> RetOps(1, Chain);
629 RetOps.append(OutVals.begin(), OutVals.end());
630 Chain = DAG.getNode(WebAssemblyISD::RETURN, DL, MVT::Other, RetOps);
632 // Record the number and types of the return values.
633 for (const ISD::OutputArg &Out : Outs) {
634 assert(!Out.Flags.isByVal() && "byval is not valid for return values");
635 assert(!Out.Flags.isNest() && "nest is not valid for return values");
636 assert(Out.IsFixed && "non-fixed return value is not valid");
637 if (Out.Flags.isInAlloca())
638 fail(DL, DAG, "WebAssembly hasn't implemented inalloca results");
639 if (Out.Flags.isInConsecutiveRegs())
640 fail(DL, DAG, "WebAssembly hasn't implemented cons regs results");
641 if (Out.Flags.isInConsecutiveRegsLast())
642 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last results");
648 SDValue WebAssemblyTargetLowering::LowerFormalArguments(
649 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
650 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
651 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
652 if (!CallingConvSupported(CallConv))
653 fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
655 MachineFunction &MF = DAG.getMachineFunction();
656 auto *MFI = MF.getInfo<WebAssemblyFunctionInfo>();
658 // Set up the incoming ARGUMENTS value, which serves to represent the liveness
659 // of the incoming values before they're represented by virtual registers.
660 MF.getRegInfo().addLiveIn(WebAssembly::ARGUMENTS);
662 for (const ISD::InputArg &In : Ins) {
663 if (In.Flags.isInAlloca())
664 fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
665 if (In.Flags.isNest())
666 fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
667 if (In.Flags.isInConsecutiveRegs())
668 fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
669 if (In.Flags.isInConsecutiveRegsLast())
670 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
671 // Ignore In.getOrigAlign() because all our arguments are passed in
675 ? DAG.getNode(WebAssemblyISD::ARGUMENT, DL, In.VT,
676 DAG.getTargetConstant(InVals.size(), DL, MVT::i32))
677 : DAG.getUNDEF(In.VT));
679 // Record the number and types of arguments.
680 MFI->addParam(In.VT);
683 // Varargs are copied into a buffer allocated by the caller, and a pointer to
684 // the buffer is passed as an argument.
686 MVT PtrVT = getPointerTy(MF.getDataLayout());
687 unsigned VarargVreg =
688 MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrVT));
689 MFI->setVarargBufferVreg(VarargVreg);
690 Chain = DAG.getCopyToReg(
691 Chain, DL, VarargVreg,
692 DAG.getNode(WebAssemblyISD::ARGUMENT, DL, PtrVT,
693 DAG.getTargetConstant(Ins.size(), DL, MVT::i32)));
694 MFI->addParam(PtrVT);
697 // Record the number and types of results.
698 SmallVector<MVT, 4> Params;
699 SmallVector<MVT, 4> Results;
700 ComputeSignatureVTs(MF.getFunction(), DAG.getTarget(), Params, Results);
701 for (MVT VT : Results)
707 //===----------------------------------------------------------------------===//
708 // Custom lowering hooks.
709 //===----------------------------------------------------------------------===//
711 SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,
712 SelectionDAG &DAG) const {
714 switch (Op.getOpcode()) {
716 llvm_unreachable("unimplemented operation lowering");
718 case ISD::FrameIndex:
719 return LowerFrameIndex(Op, DAG);
720 case ISD::GlobalAddress:
721 return LowerGlobalAddress(Op, DAG);
722 case ISD::ExternalSymbol:
723 return LowerExternalSymbol(Op, DAG);
725 return LowerJumpTable(Op, DAG);
727 return LowerBR_JT(Op, DAG);
729 return LowerVASTART(Op, DAG);
730 case ISD::BlockAddress:
732 fail(DL, DAG, "WebAssembly hasn't implemented computed gotos");
734 case ISD::RETURNADDR: // Probably nothing meaningful can be returned here.
735 fail(DL, DAG, "WebAssembly hasn't implemented __builtin_return_address");
738 return LowerFRAMEADDR(Op, DAG);
740 return LowerCopyToReg(Op, DAG);
744 SDValue WebAssemblyTargetLowering::LowerCopyToReg(SDValue Op,
745 SelectionDAG &DAG) const {
746 SDValue Src = Op.getOperand(2);
747 if (isa<FrameIndexSDNode>(Src.getNode())) {
748 // CopyToReg nodes don't support FrameIndex operands. Other targets select
749 // the FI to some LEA-like instruction, but since we don't have that, we
750 // need to insert some kind of instruction that can take an FI operand and
751 // produces a value usable by CopyToReg (i.e. in a vreg). So insert a dummy
752 // copy_local between Op and its FI operand.
753 SDValue Chain = Op.getOperand(0);
755 unsigned Reg = cast<RegisterSDNode>(Op.getOperand(1))->getReg();
756 EVT VT = Src.getValueType();
758 DAG.getMachineNode(VT == MVT::i32 ? WebAssembly::COPY_I32
759 : WebAssembly::COPY_I64,
762 return Op.getNode()->getNumValues() == 1
763 ? DAG.getCopyToReg(Chain, DL, Reg, Copy)
764 : DAG.getCopyToReg(Chain, DL, Reg, Copy, Op.getNumOperands() == 4
771 SDValue WebAssemblyTargetLowering::LowerFrameIndex(SDValue Op,
772 SelectionDAG &DAG) const {
773 int FI = cast<FrameIndexSDNode>(Op)->getIndex();
774 return DAG.getTargetFrameIndex(FI, Op.getValueType());
777 SDValue WebAssemblyTargetLowering::LowerFRAMEADDR(SDValue Op,
778 SelectionDAG &DAG) const {
779 // Non-zero depths are not supported by WebAssembly currently. Use the
780 // legalizer's default expansion, which is to return 0 (what this function is
781 // documented to do).
782 if (Op.getConstantOperandVal(0) > 0)
785 DAG.getMachineFunction().getFrameInfo().setFrameAddressIsTaken(true);
786 EVT VT = Op.getValueType();
788 Subtarget->getRegisterInfo()->getFrameRegister(DAG.getMachineFunction());
789 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), FP, VT);
792 SDValue WebAssemblyTargetLowering::LowerGlobalAddress(SDValue Op,
793 SelectionDAG &DAG) const {
795 const auto *GA = cast<GlobalAddressSDNode>(Op);
796 EVT VT = Op.getValueType();
797 assert(GA->getTargetFlags() == 0 &&
798 "Unexpected target flags on generic GlobalAddressSDNode");
799 if (GA->getAddressSpace() != 0)
800 fail(DL, DAG, "WebAssembly only expects the 0 address space");
802 WebAssemblyISD::Wrapper, DL, VT,
803 DAG.getTargetGlobalAddress(GA->getGlobal(), DL, VT, GA->getOffset()));
806 SDValue WebAssemblyTargetLowering::LowerExternalSymbol(
807 SDValue Op, SelectionDAG &DAG) const {
809 const auto *ES = cast<ExternalSymbolSDNode>(Op);
810 EVT VT = Op.getValueType();
811 assert(ES->getTargetFlags() == 0 &&
812 "Unexpected target flags on generic ExternalSymbolSDNode");
813 // Set the TargetFlags to 0x1 which indicates that this is a "function"
814 // symbol rather than a data symbol. We do this unconditionally even though
815 // we don't know anything about the symbol other than its name, because all
816 // external symbols used in target-independent SelectionDAG code are for
818 return DAG.getNode(WebAssemblyISD::Wrapper, DL, VT,
819 DAG.getTargetExternalSymbol(ES->getSymbol(), VT,
820 /*TargetFlags=*/0x1));
823 SDValue WebAssemblyTargetLowering::LowerJumpTable(SDValue Op,
824 SelectionDAG &DAG) const {
825 // There's no need for a Wrapper node because we always incorporate a jump
826 // table operand into a BR_TABLE instruction, rather than ever
827 // materializing it in a register.
828 const JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
829 return DAG.getTargetJumpTable(JT->getIndex(), Op.getValueType(),
830 JT->getTargetFlags());
833 SDValue WebAssemblyTargetLowering::LowerBR_JT(SDValue Op,
834 SelectionDAG &DAG) const {
836 SDValue Chain = Op.getOperand(0);
837 const auto *JT = cast<JumpTableSDNode>(Op.getOperand(1));
838 SDValue Index = Op.getOperand(2);
839 assert(JT->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
841 SmallVector<SDValue, 8> Ops;
842 Ops.push_back(Chain);
843 Ops.push_back(Index);
845 MachineJumpTableInfo *MJTI = DAG.getMachineFunction().getJumpTableInfo();
846 const auto &MBBs = MJTI->getJumpTables()[JT->getIndex()].MBBs;
848 // Add an operand for each case.
849 for (auto MBB : MBBs) Ops.push_back(DAG.getBasicBlock(MBB));
851 // TODO: For now, we just pick something arbitrary for a default case for now.
852 // We really want to sniff out the guard and put in the real default case (and
853 // delete the guard).
854 Ops.push_back(DAG.getBasicBlock(MBBs[0]));
856 return DAG.getNode(WebAssemblyISD::BR_TABLE, DL, MVT::Other, Ops);
859 SDValue WebAssemblyTargetLowering::LowerVASTART(SDValue Op,
860 SelectionDAG &DAG) const {
862 EVT PtrVT = getPointerTy(DAG.getMachineFunction().getDataLayout());
864 auto *MFI = DAG.getMachineFunction().getInfo<WebAssemblyFunctionInfo>();
865 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
867 SDValue ArgN = DAG.getCopyFromReg(DAG.getEntryNode(), DL,
868 MFI->getVarargBufferVreg(), PtrVT);
869 return DAG.getStore(Op.getOperand(0), DL, ArgN, Op.getOperand(1),
870 MachinePointerInfo(SV), 0);
873 //===----------------------------------------------------------------------===//
874 // WebAssembly Optimization Hooks
875 //===----------------------------------------------------------------------===//