1 // WebAssemblyInstrAtomics.td-WebAssembly Atomic codegen support-*- tablegen -*-
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// WebAssembly Atomic operand code-gen constructs.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
19 multiclass ATOMIC_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
20 list<dag> pattern_r, string asmstr_r = "",
21 string asmstr_s = "", bits<32> inst = -1> {
22 defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s,
24 Requires<[HasAtomics]>;
27 defm ATOMIC_LOAD_I32 : WebAssemblyLoad<I32, "i32.atomic.load", 0xfe10>;
28 defm ATOMIC_LOAD_I64 : WebAssemblyLoad<I64, "i64.atomic.load", 0xfe11>;
30 // Select loads with no constant offset.
31 let Predicates = [HasAtomics] in {
32 def : LoadPatNoOffset<i32, atomic_load_32, ATOMIC_LOAD_I32>;
33 def : LoadPatNoOffset<i64, atomic_load_64, ATOMIC_LOAD_I64>;
35 // Select loads with a constant offset.
37 // Pattern with address + immediate offset
38 def : LoadPatImmOff<i32, atomic_load_32, regPlusImm, ATOMIC_LOAD_I32>;
39 def : LoadPatImmOff<i64, atomic_load_64, regPlusImm, ATOMIC_LOAD_I64>;
40 def : LoadPatImmOff<i32, atomic_load_32, or_is_add, ATOMIC_LOAD_I32>;
41 def : LoadPatImmOff<i64, atomic_load_64, or_is_add, ATOMIC_LOAD_I64>;
43 def : LoadPatGlobalAddr<i32, atomic_load_32, ATOMIC_LOAD_I32>;
44 def : LoadPatGlobalAddr<i64, atomic_load_64, ATOMIC_LOAD_I64>;
46 def : LoadPatExternalSym<i32, atomic_load_32, ATOMIC_LOAD_I32>;
47 def : LoadPatExternalSym<i64, atomic_load_64, ATOMIC_LOAD_I64>;
49 // Select loads with just a constant offset.
50 def : LoadPatOffsetOnly<i32, atomic_load_32, ATOMIC_LOAD_I32>;
51 def : LoadPatOffsetOnly<i64, atomic_load_64, ATOMIC_LOAD_I64>;
53 def : LoadPatGlobalAddrOffOnly<i32, atomic_load_32, ATOMIC_LOAD_I32>;
54 def : LoadPatGlobalAddrOffOnly<i64, atomic_load_64, ATOMIC_LOAD_I64>;
56 def : LoadPatExternSymOffOnly<i32, atomic_load_32, ATOMIC_LOAD_I32>;
57 def : LoadPatExternSymOffOnly<i64, atomic_load_64, ATOMIC_LOAD_I64>;
59 } // Predicates = [HasAtomics]
61 // Extending loads. Note that there are only zero-extending atomic loads, no
62 // sign-extending loads.
63 defm ATOMIC_LOAD8_U_I32 : WebAssemblyLoad<I32, "i32.atomic.load8_u", 0xfe12>;
64 defm ATOMIC_LOAD16_U_I32 : WebAssemblyLoad<I32, "i32.atomic.load16_u", 0xfe13>;
65 defm ATOMIC_LOAD8_U_I64 : WebAssemblyLoad<I64, "i64.atomic.load8_u", 0xfe14>;
66 defm ATOMIC_LOAD16_U_I64 : WebAssemblyLoad<I64, "i64.atomic.load16_u", 0xfe15>;
67 defm ATOMIC_LOAD32_U_I64 : WebAssemblyLoad<I64, "i64.atomic.load32_u", 0xfe16>;
69 // Fragments for extending loads. These are different from regular loads because
70 // the SDNodes are derived from AtomicSDNode rather than LoadSDNode and
71 // therefore don't have the extension type field. So instead of matching that,
72 // we match the patterns that the type legalizer expands them to.
74 // We directly match zext patterns and select the zext atomic loads.
75 // i32 (zext (i8 (atomic_load_8))) gets legalized to
76 // i32 (and (i32 (atomic_load_8)), 255)
77 // These can be selected to a single zero-extending atomic load instruction.
79 PatFrag<(ops node:$addr), (and (i32 (atomic_load_8 node:$addr)), 255)>;
80 def zext_aload_16_32 :
81 PatFrag<(ops node:$addr), (and (i32 (atomic_load_16 node:$addr)), 65535)>;
82 // Unlike regular loads, extension to i64 is handled differently than i32.
83 // i64 (zext (i8 (atomic_load_8))) gets legalized to
84 // i64 (and (i64 (anyext (i32 (atomic_load_8)))), 255)
86 PatFrag<(ops node:$addr),
87 (and (i64 (anyext (i32 (atomic_load_8 node:$addr)))), 255)>;
88 def zext_aload_16_64 :
89 PatFrag<(ops node:$addr),
90 (and (i64 (anyext (i32 (atomic_load_16 node:$addr)))), 65535)>;
91 def zext_aload_32_64 :
92 PatFrag<(ops node:$addr),
93 (zext (i32 (atomic_load node:$addr)))>;
95 // We don't have single sext atomic load instructions. So for sext loads, we
96 // match bare subword loads (for 32-bit results) and anyext loads (for 64-bit
97 // results) and select a zext load; the next instruction will be sext_inreg
98 // which is selected by itself.
100 PatFrag<(ops node:$addr), (anyext (i32 (atomic_load_8 node:$addr)))>;
101 def sext_aload_16_64 :
102 PatFrag<(ops node:$addr), (anyext (i32 (atomic_load_16 node:$addr)))>;
104 let Predicates = [HasAtomics] in {
105 // Select zero-extending loads with no constant offset.
106 def : LoadPatNoOffset<i32, zext_aload_8_32, ATOMIC_LOAD8_U_I32>;
107 def : LoadPatNoOffset<i32, zext_aload_16_32, ATOMIC_LOAD16_U_I32>;
108 def : LoadPatNoOffset<i64, zext_aload_8_64, ATOMIC_LOAD8_U_I64>;
109 def : LoadPatNoOffset<i64, zext_aload_16_64, ATOMIC_LOAD16_U_I64>;
110 def : LoadPatNoOffset<i64, zext_aload_32_64, ATOMIC_LOAD32_U_I64>;
112 // Select sign-extending loads with no constant offset
113 def : LoadPatNoOffset<i32, atomic_load_8, ATOMIC_LOAD8_U_I32>;
114 def : LoadPatNoOffset<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>;
115 def : LoadPatNoOffset<i64, sext_aload_8_64, ATOMIC_LOAD8_U_I64>;
116 def : LoadPatNoOffset<i64, sext_aload_16_64, ATOMIC_LOAD16_U_I64>;
117 // 32->64 sext load gets selected as i32.atomic.load, i64.extend_i32_s
119 // Zero-extending loads with constant offset
120 def : LoadPatImmOff<i32, zext_aload_8_32, regPlusImm, ATOMIC_LOAD8_U_I32>;
121 def : LoadPatImmOff<i32, zext_aload_16_32, regPlusImm, ATOMIC_LOAD16_U_I32>;
122 def : LoadPatImmOff<i32, zext_aload_8_32, or_is_add, ATOMIC_LOAD8_U_I32>;
123 def : LoadPatImmOff<i32, zext_aload_16_32, or_is_add, ATOMIC_LOAD16_U_I32>;
124 def : LoadPatImmOff<i64, zext_aload_8_64, regPlusImm, ATOMIC_LOAD8_U_I64>;
125 def : LoadPatImmOff<i64, zext_aload_16_64, regPlusImm, ATOMIC_LOAD16_U_I64>;
126 def : LoadPatImmOff<i64, zext_aload_32_64, regPlusImm, ATOMIC_LOAD32_U_I64>;
127 def : LoadPatImmOff<i64, zext_aload_8_64, or_is_add, ATOMIC_LOAD8_U_I64>;
128 def : LoadPatImmOff<i64, zext_aload_16_64, or_is_add, ATOMIC_LOAD16_U_I64>;
129 def : LoadPatImmOff<i64, zext_aload_32_64, or_is_add, ATOMIC_LOAD32_U_I64>;
131 // Sign-extending loads with constant offset
132 def : LoadPatImmOff<i32, atomic_load_8, regPlusImm, ATOMIC_LOAD8_U_I32>;
133 def : LoadPatImmOff<i32, atomic_load_16, regPlusImm, ATOMIC_LOAD16_U_I32>;
134 def : LoadPatImmOff<i32, atomic_load_8, or_is_add, ATOMIC_LOAD8_U_I32>;
135 def : LoadPatImmOff<i32, atomic_load_16, or_is_add, ATOMIC_LOAD16_U_I32>;
136 def : LoadPatImmOff<i64, sext_aload_8_64, regPlusImm, ATOMIC_LOAD8_U_I64>;
137 def : LoadPatImmOff<i64, sext_aload_16_64, regPlusImm, ATOMIC_LOAD16_U_I64>;
138 def : LoadPatImmOff<i64, sext_aload_8_64, or_is_add, ATOMIC_LOAD8_U_I64>;
139 def : LoadPatImmOff<i64, sext_aload_16_64, or_is_add, ATOMIC_LOAD16_U_I64>;
140 // No 32->64 patterns, just use i32.atomic.load and i64.extend_s/i64
142 def : LoadPatGlobalAddr<i32, zext_aload_8_32, ATOMIC_LOAD8_U_I32>;
143 def : LoadPatGlobalAddr<i32, zext_aload_16_32, ATOMIC_LOAD16_U_I32>;
144 def : LoadPatGlobalAddr<i64, zext_aload_8_64, ATOMIC_LOAD8_U_I64>;
145 def : LoadPatGlobalAddr<i64, zext_aload_16_64, ATOMIC_LOAD16_U_I64>;
146 def : LoadPatGlobalAddr<i64, zext_aload_32_64, ATOMIC_LOAD32_U_I64>;
147 def : LoadPatGlobalAddr<i32, atomic_load_8, ATOMIC_LOAD8_U_I32>;
148 def : LoadPatGlobalAddr<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>;
149 def : LoadPatGlobalAddr<i64, sext_aload_8_64, ATOMIC_LOAD8_U_I64>;
150 def : LoadPatGlobalAddr<i64, sext_aload_16_64, ATOMIC_LOAD16_U_I64>;
152 def : LoadPatExternalSym<i32, zext_aload_8_32, ATOMIC_LOAD8_U_I32>;
153 def : LoadPatExternalSym<i32, zext_aload_16_32, ATOMIC_LOAD16_U_I32>;
154 def : LoadPatExternalSym<i64, zext_aload_8_64, ATOMIC_LOAD8_U_I64>;
155 def : LoadPatExternalSym<i64, zext_aload_16_64, ATOMIC_LOAD16_U_I64>;
156 def : LoadPatExternalSym<i64, zext_aload_32_64, ATOMIC_LOAD32_U_I64>;
157 def : LoadPatExternalSym<i32, atomic_load_8, ATOMIC_LOAD8_U_I32>;
158 def : LoadPatExternalSym<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>;
159 def : LoadPatExternalSym<i64, sext_aload_8_64, ATOMIC_LOAD8_U_I64>;
160 def : LoadPatExternalSym<i64, sext_aload_16_64, ATOMIC_LOAD16_U_I64>;
162 // Extending loads with just a constant offset
163 def : LoadPatOffsetOnly<i32, zext_aload_8_32, ATOMIC_LOAD8_U_I32>;
164 def : LoadPatOffsetOnly<i32, zext_aload_16_32, ATOMIC_LOAD16_U_I32>;
165 def : LoadPatOffsetOnly<i64, zext_aload_8_64, ATOMIC_LOAD8_U_I64>;
166 def : LoadPatOffsetOnly<i64, zext_aload_16_64, ATOMIC_LOAD16_U_I64>;
167 def : LoadPatOffsetOnly<i64, zext_aload_32_64, ATOMIC_LOAD32_U_I64>;
168 def : LoadPatOffsetOnly<i32, atomic_load_8, ATOMIC_LOAD8_U_I32>;
169 def : LoadPatOffsetOnly<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>;
170 def : LoadPatOffsetOnly<i64, sext_aload_8_64, ATOMIC_LOAD8_U_I64>;
171 def : LoadPatOffsetOnly<i64, sext_aload_16_64, ATOMIC_LOAD16_U_I64>;
173 def : LoadPatGlobalAddrOffOnly<i32, zext_aload_8_32, ATOMIC_LOAD8_U_I32>;
174 def : LoadPatGlobalAddrOffOnly<i32, zext_aload_16_32, ATOMIC_LOAD16_U_I32>;
175 def : LoadPatGlobalAddrOffOnly<i64, zext_aload_8_64, ATOMIC_LOAD8_U_I64>;
176 def : LoadPatGlobalAddrOffOnly<i64, zext_aload_16_64, ATOMIC_LOAD16_U_I64>;
177 def : LoadPatGlobalAddrOffOnly<i64, zext_aload_32_64, ATOMIC_LOAD32_U_I64>;
178 def : LoadPatGlobalAddrOffOnly<i32, atomic_load_8, ATOMIC_LOAD8_U_I32>;
179 def : LoadPatGlobalAddrOffOnly<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>;
180 def : LoadPatGlobalAddrOffOnly<i64, sext_aload_8_64, ATOMIC_LOAD8_U_I64>;
181 def : LoadPatGlobalAddrOffOnly<i64, sext_aload_16_64, ATOMIC_LOAD16_U_I64>;
183 def : LoadPatExternSymOffOnly<i32, zext_aload_8_32, ATOMIC_LOAD8_U_I32>;
184 def : LoadPatExternSymOffOnly<i32, zext_aload_16_32, ATOMIC_LOAD16_U_I32>;
185 def : LoadPatExternSymOffOnly<i64, zext_aload_8_64, ATOMIC_LOAD8_U_I64>;
186 def : LoadPatExternSymOffOnly<i64, zext_aload_16_64, ATOMIC_LOAD16_U_I64>;
187 def : LoadPatExternSymOffOnly<i64, zext_aload_32_64, ATOMIC_LOAD32_U_I64>;
188 def : LoadPatExternSymOffOnly<i32, atomic_load_8, ATOMIC_LOAD8_U_I32>;
189 def : LoadPatExternSymOffOnly<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>;
190 def : LoadPatExternSymOffOnly<i64, sext_aload_8_64, ATOMIC_LOAD8_U_I64>;
191 def : LoadPatExternSymOffOnly<i64, sext_aload_16_64, ATOMIC_LOAD16_U_I64>;
193 } // Predicates = [HasAtomics]
195 //===----------------------------------------------------------------------===//
197 //===----------------------------------------------------------------------===//
199 defm ATOMIC_STORE_I32 : WebAssemblyStore<I32, "i32.atomic.store", 0xfe17>;
200 defm ATOMIC_STORE_I64 : WebAssemblyStore<I64, "i64.atomic.store", 0xfe18>;
202 // We need an 'atomic' version of store patterns because store and atomic_store
203 // nodes have different operand orders:
204 // store: (store $val, $ptr)
205 // atomic_store: (store $ptr, $val)
207 let Predicates = [HasAtomics] in {
209 // Select stores with no constant offset.
210 class AStorePatNoOffset<ValueType ty, PatFrag kind, NI inst> :
211 Pat<(kind I32:$addr, ty:$val), (inst 0, 0, I32:$addr, ty:$val)>;
212 def : AStorePatNoOffset<i32, atomic_store_32, ATOMIC_STORE_I32>;
213 def : AStorePatNoOffset<i64, atomic_store_64, ATOMIC_STORE_I64>;
215 // Select stores with a constant offset.
217 // Pattern with address + immediate offset
218 class AStorePatImmOff<ValueType ty, PatFrag kind, PatFrag operand, NI inst> :
219 Pat<(kind (operand I32:$addr, imm:$off), ty:$val),
220 (inst 0, imm:$off, I32:$addr, ty:$val)>;
221 def : AStorePatImmOff<i32, atomic_store_32, regPlusImm, ATOMIC_STORE_I32>;
222 def : AStorePatImmOff<i64, atomic_store_64, regPlusImm, ATOMIC_STORE_I64>;
223 def : AStorePatImmOff<i32, atomic_store_32, or_is_add, ATOMIC_STORE_I32>;
224 def : AStorePatImmOff<i64, atomic_store_64, or_is_add, ATOMIC_STORE_I64>;
226 class AStorePatGlobalAddr<ValueType ty, PatFrag kind, NI inst> :
227 Pat<(kind (regPlusGA I32:$addr, (WebAssemblywrapper tglobaladdr:$off)),
229 (inst 0, tglobaladdr:$off, I32:$addr, ty:$val)>;
230 def : AStorePatGlobalAddr<i32, atomic_store_32, ATOMIC_STORE_I32>;
231 def : AStorePatGlobalAddr<i64, atomic_store_64, ATOMIC_STORE_I64>;
233 class AStorePatExternalSym<ValueType ty, PatFrag kind, NI inst> :
234 Pat<(kind (add I32:$addr, (WebAssemblywrapper texternalsym:$off)), ty:$val),
235 (inst 0, texternalsym:$off, I32:$addr, ty:$val)>;
236 def : AStorePatExternalSym<i32, atomic_store_32, ATOMIC_STORE_I32>;
237 def : AStorePatExternalSym<i64, atomic_store_64, ATOMIC_STORE_I64>;
239 // Select stores with just a constant offset.
240 class AStorePatOffsetOnly<ValueType ty, PatFrag kind, NI inst> :
241 Pat<(kind imm:$off, ty:$val), (inst 0, imm:$off, (CONST_I32 0), ty:$val)>;
242 def : AStorePatOffsetOnly<i32, atomic_store_32, ATOMIC_STORE_I32>;
243 def : AStorePatOffsetOnly<i64, atomic_store_64, ATOMIC_STORE_I64>;
245 class AStorePatGlobalAddrOffOnly<ValueType ty, PatFrag kind, NI inst> :
246 Pat<(kind (WebAssemblywrapper tglobaladdr:$off), ty:$val),
247 (inst 0, tglobaladdr:$off, (CONST_I32 0), ty:$val)>;
248 def : AStorePatGlobalAddrOffOnly<i32, atomic_store_32, ATOMIC_STORE_I32>;
249 def : AStorePatGlobalAddrOffOnly<i64, atomic_store_64, ATOMIC_STORE_I64>;
251 class AStorePatExternSymOffOnly<ValueType ty, PatFrag kind, NI inst> :
252 Pat<(kind (WebAssemblywrapper texternalsym:$off), ty:$val),
253 (inst 0, texternalsym:$off, (CONST_I32 0), ty:$val)>;
254 def : AStorePatExternSymOffOnly<i32, atomic_store_32, ATOMIC_STORE_I32>;
255 def : AStorePatExternSymOffOnly<i64, atomic_store_64, ATOMIC_STORE_I64>;
257 } // Predicates = [HasAtomics]
259 // Truncating stores.
260 defm ATOMIC_STORE8_I32 : WebAssemblyStore<I32, "i32.atomic.store8", 0xfe19>;
261 defm ATOMIC_STORE16_I32 : WebAssemblyStore<I32, "i32.atomic.store16", 0xfe1a>;
262 defm ATOMIC_STORE8_I64 : WebAssemblyStore<I64, "i64.atomic.store8", 0xfe1b>;
263 defm ATOMIC_STORE16_I64 : WebAssemblyStore<I64, "i64.atomic.store16", 0xfe1c>;
264 defm ATOMIC_STORE32_I64 : WebAssemblyStore<I64, "i64.atomic.store32", 0xfe1d>;
266 // Fragments for truncating stores.
268 // We don't have single truncating atomic store instructions. For 32-bit
269 // instructions, we just need to match bare atomic stores. On the other hand,
270 // truncating stores from i64 values are once truncated to i32 first.
271 class trunc_astore_64<PatFrag kind> :
272 PatFrag<(ops node:$addr, node:$val),
273 (kind node:$addr, (i32 (trunc (i64 node:$val))))>;
274 def trunc_astore_8_64 : trunc_astore_64<atomic_store_8>;
275 def trunc_astore_16_64 : trunc_astore_64<atomic_store_16>;
276 def trunc_astore_32_64 : trunc_astore_64<atomic_store_32>;
278 let Predicates = [HasAtomics] in {
280 // Truncating stores with no constant offset
281 def : AStorePatNoOffset<i32, atomic_store_8, ATOMIC_STORE8_I32>;
282 def : AStorePatNoOffset<i32, atomic_store_16, ATOMIC_STORE16_I32>;
283 def : AStorePatNoOffset<i64, trunc_astore_8_64, ATOMIC_STORE8_I64>;
284 def : AStorePatNoOffset<i64, trunc_astore_16_64, ATOMIC_STORE16_I64>;
285 def : AStorePatNoOffset<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>;
287 // Truncating stores with a constant offset
288 def : AStorePatImmOff<i32, atomic_store_8, regPlusImm, ATOMIC_STORE8_I32>;
289 def : AStorePatImmOff<i32, atomic_store_16, regPlusImm, ATOMIC_STORE16_I32>;
290 def : AStorePatImmOff<i64, trunc_astore_8_64, regPlusImm, ATOMIC_STORE8_I64>;
291 def : AStorePatImmOff<i64, trunc_astore_16_64, regPlusImm, ATOMIC_STORE16_I64>;
292 def : AStorePatImmOff<i64, trunc_astore_32_64, regPlusImm, ATOMIC_STORE32_I64>;
293 def : AStorePatImmOff<i32, atomic_store_8, or_is_add, ATOMIC_STORE8_I32>;
294 def : AStorePatImmOff<i32, atomic_store_16, or_is_add, ATOMIC_STORE16_I32>;
295 def : AStorePatImmOff<i64, trunc_astore_8_64, or_is_add, ATOMIC_STORE8_I64>;
296 def : AStorePatImmOff<i64, trunc_astore_16_64, or_is_add, ATOMIC_STORE16_I64>;
297 def : AStorePatImmOff<i64, trunc_astore_32_64, or_is_add, ATOMIC_STORE32_I64>;
299 def : AStorePatGlobalAddr<i32, atomic_store_8, ATOMIC_STORE8_I32>;
300 def : AStorePatGlobalAddr<i32, atomic_store_16, ATOMIC_STORE16_I32>;
301 def : AStorePatGlobalAddr<i64, trunc_astore_8_64, ATOMIC_STORE8_I64>;
302 def : AStorePatGlobalAddr<i64, trunc_astore_16_64, ATOMIC_STORE16_I64>;
303 def : AStorePatGlobalAddr<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>;
305 def : AStorePatExternalSym<i32, atomic_store_8, ATOMIC_STORE8_I32>;
306 def : AStorePatExternalSym<i32, atomic_store_16, ATOMIC_STORE16_I32>;
307 def : AStorePatExternalSym<i64, trunc_astore_8_64, ATOMIC_STORE8_I64>;
308 def : AStorePatExternalSym<i64, trunc_astore_16_64, ATOMIC_STORE16_I64>;
309 def : AStorePatExternalSym<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>;
311 // Truncating stores with just a constant offset
312 def : AStorePatOffsetOnly<i32, atomic_store_8, ATOMIC_STORE8_I32>;
313 def : AStorePatOffsetOnly<i32, atomic_store_16, ATOMIC_STORE16_I32>;
314 def : AStorePatOffsetOnly<i64, trunc_astore_8_64, ATOMIC_STORE8_I64>;
315 def : AStorePatOffsetOnly<i64, trunc_astore_16_64, ATOMIC_STORE16_I64>;
316 def : AStorePatOffsetOnly<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>;
318 def : AStorePatGlobalAddrOffOnly<i32, atomic_store_8, ATOMIC_STORE8_I32>;
319 def : AStorePatGlobalAddrOffOnly<i32, atomic_store_16, ATOMIC_STORE16_I32>;
320 def : AStorePatGlobalAddrOffOnly<i64, trunc_astore_8_64, ATOMIC_STORE8_I64>;
321 def : AStorePatGlobalAddrOffOnly<i64, trunc_astore_16_64, ATOMIC_STORE16_I64>;
322 def : AStorePatGlobalAddrOffOnly<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>;
324 def : AStorePatExternSymOffOnly<i32, atomic_store_8, ATOMIC_STORE8_I32>;
325 def : AStorePatExternSymOffOnly<i32, atomic_store_16, ATOMIC_STORE16_I32>;
326 def : AStorePatExternSymOffOnly<i64, trunc_astore_8_64, ATOMIC_STORE8_I64>;
327 def : AStorePatExternSymOffOnly<i64, trunc_astore_16_64, ATOMIC_STORE16_I64>;
328 def : AStorePatExternSymOffOnly<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>;
330 } // Predicates = [HasAtomics]
332 //===----------------------------------------------------------------------===//
333 // Atomic binary read-modify-writes
334 //===----------------------------------------------------------------------===//
336 multiclass WebAssemblyBinRMW<WebAssemblyRegClass rc, string Name, int Opcode> {
337 defm "" : I<(outs rc:$dst),
338 (ins P2Align:$p2align, offset32_op:$off, I32:$addr, rc:$val),
339 (outs), (ins P2Align:$p2align, offset32_op:$off), [],
340 !strconcat(Name, "\t$dst, ${off}(${addr})${p2align}, $val"),
341 !strconcat(Name, "\t${off}, ${p2align}"), Opcode>;
344 defm ATOMIC_RMW_ADD_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.add", 0xfe1e>;
345 defm ATOMIC_RMW_ADD_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.add", 0xfe1f>;
346 defm ATOMIC_RMW8_U_ADD_I32 :
347 WebAssemblyBinRMW<I32, "i32.atomic.rmw8.add_u", 0xfe20>;
348 defm ATOMIC_RMW16_U_ADD_I32 :
349 WebAssemblyBinRMW<I32, "i32.atomic.rmw16.add_u", 0xfe21>;
350 defm ATOMIC_RMW8_U_ADD_I64 :
351 WebAssemblyBinRMW<I64, "i64.atomic.rmw8.add_u", 0xfe22>;
352 defm ATOMIC_RMW16_U_ADD_I64 :
353 WebAssemblyBinRMW<I64, "i64.atomic.rmw16.add_u", 0xfe23>;
354 defm ATOMIC_RMW32_U_ADD_I64 :
355 WebAssemblyBinRMW<I64, "i64.atomic.rmw32.add_u", 0xfe24>;
357 defm ATOMIC_RMW_SUB_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.sub", 0xfe25>;
358 defm ATOMIC_RMW_SUB_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.sub", 0xfe26>;
359 defm ATOMIC_RMW8_U_SUB_I32 :
360 WebAssemblyBinRMW<I32, "i32.atomic.rmw8.sub_u", 0xfe27>;
361 defm ATOMIC_RMW16_U_SUB_I32 :
362 WebAssemblyBinRMW<I32, "i32.atomic.rmw16.sub_u", 0xfe28>;
363 defm ATOMIC_RMW8_U_SUB_I64 :
364 WebAssemblyBinRMW<I64, "i64.atomic.rmw8.sub_u", 0xfe29>;
365 defm ATOMIC_RMW16_U_SUB_I64 :
366 WebAssemblyBinRMW<I64, "i64.atomic.rmw16.sub_u", 0xfe2a>;
367 defm ATOMIC_RMW32_U_SUB_I64 :
368 WebAssemblyBinRMW<I64, "i64.atomic.rmw32.sub_u", 0xfe2b>;
370 defm ATOMIC_RMW_AND_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.and", 0xfe2c>;
371 defm ATOMIC_RMW_AND_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.and", 0xfe2d>;
372 defm ATOMIC_RMW8_U_AND_I32 :
373 WebAssemblyBinRMW<I32, "i32.atomic.rmw8.and_u", 0xfe2e>;
374 defm ATOMIC_RMW16_U_AND_I32 :
375 WebAssemblyBinRMW<I32, "i32.atomic.rmw16.and_u", 0xfe2f>;
376 defm ATOMIC_RMW8_U_AND_I64 :
377 WebAssemblyBinRMW<I64, "i64.atomic.rmw8.and_u", 0xfe30>;
378 defm ATOMIC_RMW16_U_AND_I64 :
379 WebAssemblyBinRMW<I64, "i64.atomic.rmw16.and_u", 0xfe31>;
380 defm ATOMIC_RMW32_U_AND_I64 :
381 WebAssemblyBinRMW<I64, "i64.atomic.rmw32.and_u", 0xfe32>;
383 defm ATOMIC_RMW_OR_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.or", 0xfe33>;
384 defm ATOMIC_RMW_OR_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.or", 0xfe34>;
385 defm ATOMIC_RMW8_U_OR_I32 :
386 WebAssemblyBinRMW<I32, "i32.atomic.rmw8.or_u", 0xfe35>;
387 defm ATOMIC_RMW16_U_OR_I32 :
388 WebAssemblyBinRMW<I32, "i32.atomic.rmw16.or_u", 0xfe36>;
389 defm ATOMIC_RMW8_U_OR_I64 :
390 WebAssemblyBinRMW<I64, "i64.atomic.rmw8.or_u", 0xfe37>;
391 defm ATOMIC_RMW16_U_OR_I64 :
392 WebAssemblyBinRMW<I64, "i64.atomic.rmw16.or_u", 0xfe38>;
393 defm ATOMIC_RMW32_U_OR_I64 :
394 WebAssemblyBinRMW<I64, "i64.atomic.rmw32.or_u", 0xfe39>;
396 defm ATOMIC_RMW_XOR_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.xor", 0xfe3a>;
397 defm ATOMIC_RMW_XOR_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.xor", 0xfe3b>;
398 defm ATOMIC_RMW8_U_XOR_I32 :
399 WebAssemblyBinRMW<I32, "i32.atomic.rmw8.xor_u", 0xfe3c>;
400 defm ATOMIC_RMW16_U_XOR_I32 :
401 WebAssemblyBinRMW<I32, "i32.atomic.rmw16.xor_u", 0xfe3d>;
402 defm ATOMIC_RMW8_U_XOR_I64 :
403 WebAssemblyBinRMW<I64, "i64.atomic.rmw8.xor_u", 0xfe3e>;
404 defm ATOMIC_RMW16_U_XOR_I64 :
405 WebAssemblyBinRMW<I64, "i64.atomic.rmw16.xor_u", 0xfe3f>;
406 defm ATOMIC_RMW32_U_XOR_I64 :
407 WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xor_u", 0xfe40>;
409 defm ATOMIC_RMW_XCHG_I32 :
410 WebAssemblyBinRMW<I32, "i32.atomic.rmw.xchg", 0xfe41>;
411 defm ATOMIC_RMW_XCHG_I64 :
412 WebAssemblyBinRMW<I64, "i64.atomic.rmw.xchg", 0xfe42>;
413 defm ATOMIC_RMW8_U_XCHG_I32 :
414 WebAssemblyBinRMW<I32, "i32.atomic.rmw8.xchg_u", 0xfe43>;
415 defm ATOMIC_RMW16_U_XCHG_I32 :
416 WebAssemblyBinRMW<I32, "i32.atomic.rmw16.xchg_u", 0xfe44>;
417 defm ATOMIC_RMW8_U_XCHG_I64 :
418 WebAssemblyBinRMW<I64, "i64.atomic.rmw8.xchg_u", 0xfe45>;
419 defm ATOMIC_RMW16_U_XCHG_I64 :
420 WebAssemblyBinRMW<I64, "i64.atomic.rmw16.xchg_u", 0xfe46>;
421 defm ATOMIC_RMW32_U_XCHG_I64 :
422 WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xchg_u", 0xfe47>;
424 // Select binary RMWs with no constant offset.
425 class BinRMWPatNoOffset<ValueType ty, PatFrag kind, NI inst> :
426 Pat<(ty (kind I32:$addr, ty:$val)), (inst 0, 0, I32:$addr, ty:$val)>;
428 // Select binary RMWs with a constant offset.
430 // Pattern with address + immediate offset
431 class BinRMWPatImmOff<ValueType ty, PatFrag kind, PatFrag operand, NI inst> :
432 Pat<(ty (kind (operand I32:$addr, imm:$off), ty:$val)),
433 (inst 0, imm:$off, I32:$addr, ty:$val)>;
435 class BinRMWPatGlobalAddr<ValueType ty, PatFrag kind, NI inst> :
436 Pat<(ty (kind (regPlusGA I32:$addr, (WebAssemblywrapper tglobaladdr:$off)),
438 (inst 0, tglobaladdr:$off, I32:$addr, ty:$val)>;
440 class BinRMWPatExternalSym<ValueType ty, PatFrag kind, NI inst> :
441 Pat<(ty (kind (add I32:$addr, (WebAssemblywrapper texternalsym:$off)),
443 (inst 0, texternalsym:$off, I32:$addr, ty:$val)>;
445 // Select binary RMWs with just a constant offset.
446 class BinRMWPatOffsetOnly<ValueType ty, PatFrag kind, NI inst> :
447 Pat<(ty (kind imm:$off, ty:$val)),
448 (inst 0, imm:$off, (CONST_I32 0), ty:$val)>;
450 class BinRMWPatGlobalAddrOffOnly<ValueType ty, PatFrag kind, NI inst> :
451 Pat<(ty (kind (WebAssemblywrapper tglobaladdr:$off), ty:$val)),
452 (inst 0, tglobaladdr:$off, (CONST_I32 0), ty:$val)>;
454 class BinRMWPatExternSymOffOnly<ValueType ty, PatFrag kind, NI inst> :
455 Pat<(ty (kind (WebAssemblywrapper texternalsym:$off), ty:$val)),
456 (inst 0, texternalsym:$off, (CONST_I32 0), ty:$val)>;
458 // Patterns for various addressing modes.
459 multiclass BinRMWPattern<PatFrag rmw_32, PatFrag rmw_64, NI inst_32,
461 def : BinRMWPatNoOffset<i32, rmw_32, inst_32>;
462 def : BinRMWPatNoOffset<i64, rmw_64, inst_64>;
464 def : BinRMWPatImmOff<i32, rmw_32, regPlusImm, inst_32>;
465 def : BinRMWPatImmOff<i64, rmw_64, regPlusImm, inst_64>;
466 def : BinRMWPatImmOff<i32, rmw_32, or_is_add, inst_32>;
467 def : BinRMWPatImmOff<i64, rmw_64, or_is_add, inst_64>;
469 def : BinRMWPatGlobalAddr<i32, rmw_32, inst_32>;
470 def : BinRMWPatGlobalAddr<i64, rmw_64, inst_64>;
472 def : BinRMWPatExternalSym<i32, rmw_32, inst_32>;
473 def : BinRMWPatExternalSym<i64, rmw_64, inst_64>;
475 def : BinRMWPatOffsetOnly<i32, rmw_32, inst_32>;
476 def : BinRMWPatOffsetOnly<i64, rmw_64, inst_64>;
478 def : BinRMWPatGlobalAddrOffOnly<i32, rmw_32, inst_32>;
479 def : BinRMWPatGlobalAddrOffOnly<i64, rmw_64, inst_64>;
481 def : BinRMWPatExternSymOffOnly<i32, rmw_32, inst_32>;
482 def : BinRMWPatExternSymOffOnly<i64, rmw_64, inst_64>;
485 let Predicates = [HasAtomics] in {
486 defm : BinRMWPattern<atomic_load_add_32, atomic_load_add_64, ATOMIC_RMW_ADD_I32,
488 defm : BinRMWPattern<atomic_load_sub_32, atomic_load_sub_64, ATOMIC_RMW_SUB_I32,
490 defm : BinRMWPattern<atomic_load_and_32, atomic_load_and_64, ATOMIC_RMW_AND_I32,
492 defm : BinRMWPattern<atomic_load_or_32, atomic_load_or_64, ATOMIC_RMW_OR_I32,
494 defm : BinRMWPattern<atomic_load_xor_32, atomic_load_xor_64, ATOMIC_RMW_XOR_I32,
496 defm : BinRMWPattern<atomic_swap_32, atomic_swap_64, ATOMIC_RMW_XCHG_I32,
497 ATOMIC_RMW_XCHG_I64>;
498 } // Predicates = [HasAtomics]
500 // Truncating & zero-extending binary RMW patterns.
501 // These are combined patterns of truncating store patterns and zero-extending
502 // load patterns above.
503 class zext_bin_rmw_8_32<PatFrag kind> :
504 PatFrag<(ops node:$addr, node:$val),
505 (and (i32 (kind node:$addr, node:$val)), 255)>;
506 class zext_bin_rmw_16_32<PatFrag kind> :
507 PatFrag<(ops node:$addr, node:$val),
508 (and (i32 (kind node:$addr, node:$val)), 65535)>;
509 class zext_bin_rmw_8_64<PatFrag kind> :
510 PatFrag<(ops node:$addr, node:$val),
511 (and (i64 (anyext (i32 (kind node:$addr,
512 (i32 (trunc (i64 node:$val))))))), 255)>;
513 class zext_bin_rmw_16_64<PatFrag kind> :
514 PatFrag<(ops node:$addr, node:$val),
515 (and (i64 (anyext (i32 (kind node:$addr,
516 (i32 (trunc (i64 node:$val))))))), 65535)>;
517 class zext_bin_rmw_32_64<PatFrag kind> :
518 PatFrag<(ops node:$addr, node:$val),
519 (zext (i32 (kind node:$addr, (i32 (trunc (i64 node:$val))))))>;
521 // Truncating & sign-extending binary RMW patterns.
522 // These are combined patterns of truncating store patterns and sign-extending
523 // load patterns above. We match subword RMWs (for 32-bit) and anyext RMWs (for
524 // 64-bit) and select a zext RMW; the next instruction will be sext_inreg which
525 // is selected by itself.
526 class sext_bin_rmw_8_32<PatFrag kind> :
527 PatFrag<(ops node:$addr, node:$val), (kind node:$addr, node:$val)>;
528 class sext_bin_rmw_16_32<PatFrag kind> : sext_bin_rmw_8_32<kind>;
529 class sext_bin_rmw_8_64<PatFrag kind> :
530 PatFrag<(ops node:$addr, node:$val),
531 (anyext (i32 (kind node:$addr, (i32 (trunc (i64 node:$val))))))>;
532 class sext_bin_rmw_16_64<PatFrag kind> : sext_bin_rmw_8_64<kind>;
533 // 32->64 sext RMW gets selected as i32.atomic.rmw.***, i64.extend_i32_s
535 // Patterns for various addressing modes for truncating-extending binary RMWs.
536 multiclass BinRMWTruncExtPattern<
537 PatFrag rmw_8, PatFrag rmw_16, PatFrag rmw_32, PatFrag rmw_64,
538 NI inst8_32, NI inst16_32, NI inst8_64, NI inst16_64, NI inst32_64> {
539 // Truncating-extending binary RMWs with no constant offset
540 def : BinRMWPatNoOffset<i32, zext_bin_rmw_8_32<rmw_8>, inst8_32>;
541 def : BinRMWPatNoOffset<i32, zext_bin_rmw_16_32<rmw_16>, inst16_32>;
542 def : BinRMWPatNoOffset<i64, zext_bin_rmw_8_64<rmw_8>, inst8_64>;
543 def : BinRMWPatNoOffset<i64, zext_bin_rmw_16_64<rmw_16>, inst16_64>;
544 def : BinRMWPatNoOffset<i64, zext_bin_rmw_32_64<rmw_32>, inst32_64>;
546 def : BinRMWPatNoOffset<i32, sext_bin_rmw_8_32<rmw_8>, inst8_32>;
547 def : BinRMWPatNoOffset<i32, sext_bin_rmw_16_32<rmw_16>, inst16_32>;
548 def : BinRMWPatNoOffset<i64, sext_bin_rmw_8_64<rmw_8>, inst8_64>;
549 def : BinRMWPatNoOffset<i64, sext_bin_rmw_16_64<rmw_16>, inst16_64>;
551 // Truncating-extending binary RMWs with a constant offset
552 def : BinRMWPatImmOff<i32, zext_bin_rmw_8_32<rmw_8>, regPlusImm, inst8_32>;
553 def : BinRMWPatImmOff<i32, zext_bin_rmw_16_32<rmw_16>, regPlusImm, inst16_32>;
554 def : BinRMWPatImmOff<i64, zext_bin_rmw_8_64<rmw_8>, regPlusImm, inst8_64>;
555 def : BinRMWPatImmOff<i64, zext_bin_rmw_16_64<rmw_16>, regPlusImm, inst16_64>;
556 def : BinRMWPatImmOff<i64, zext_bin_rmw_32_64<rmw_32>, regPlusImm, inst32_64>;
557 def : BinRMWPatImmOff<i32, zext_bin_rmw_8_32<rmw_8>, or_is_add, inst8_32>;
558 def : BinRMWPatImmOff<i32, zext_bin_rmw_16_32<rmw_16>, or_is_add, inst16_32>;
559 def : BinRMWPatImmOff<i64, zext_bin_rmw_8_64<rmw_8>, or_is_add, inst8_64>;
560 def : BinRMWPatImmOff<i64, zext_bin_rmw_16_64<rmw_16>, or_is_add, inst16_64>;
561 def : BinRMWPatImmOff<i64, zext_bin_rmw_32_64<rmw_32>, or_is_add, inst32_64>;
563 def : BinRMWPatImmOff<i32, sext_bin_rmw_8_32<rmw_8>, regPlusImm, inst8_32>;
564 def : BinRMWPatImmOff<i32, sext_bin_rmw_16_32<rmw_16>, regPlusImm, inst16_32>;
565 def : BinRMWPatImmOff<i64, sext_bin_rmw_8_64<rmw_8>, regPlusImm, inst8_64>;
566 def : BinRMWPatImmOff<i64, sext_bin_rmw_16_64<rmw_16>, regPlusImm, inst16_64>;
567 def : BinRMWPatImmOff<i32, sext_bin_rmw_8_32<rmw_8>, or_is_add, inst8_32>;
568 def : BinRMWPatImmOff<i32, sext_bin_rmw_16_32<rmw_16>, or_is_add, inst16_32>;
569 def : BinRMWPatImmOff<i64, sext_bin_rmw_8_64<rmw_8>, or_is_add, inst8_64>;
570 def : BinRMWPatImmOff<i64, sext_bin_rmw_16_64<rmw_16>, or_is_add, inst16_64>;
572 def : BinRMWPatGlobalAddr<i32, zext_bin_rmw_8_32<rmw_8>, inst8_32>;
573 def : BinRMWPatGlobalAddr<i32, zext_bin_rmw_16_32<rmw_16>, inst16_32>;
574 def : BinRMWPatGlobalAddr<i64, zext_bin_rmw_8_64<rmw_8>, inst8_64>;
575 def : BinRMWPatGlobalAddr<i64, zext_bin_rmw_16_64<rmw_16>, inst16_64>;
576 def : BinRMWPatGlobalAddr<i64, zext_bin_rmw_32_64<rmw_32>, inst32_64>;
578 def : BinRMWPatGlobalAddr<i32, sext_bin_rmw_8_32<rmw_8>, inst8_32>;
579 def : BinRMWPatGlobalAddr<i32, sext_bin_rmw_16_32<rmw_16>, inst16_32>;
580 def : BinRMWPatGlobalAddr<i64, sext_bin_rmw_8_64<rmw_8>, inst8_64>;
581 def : BinRMWPatGlobalAddr<i64, sext_bin_rmw_16_64<rmw_16>, inst16_64>;
583 def : BinRMWPatExternalSym<i32, zext_bin_rmw_8_32<rmw_8>, inst8_32>;
584 def : BinRMWPatExternalSym<i32, zext_bin_rmw_16_32<rmw_16>, inst16_32>;
585 def : BinRMWPatExternalSym<i64, zext_bin_rmw_8_64<rmw_8>, inst8_64>;
586 def : BinRMWPatExternalSym<i64, zext_bin_rmw_16_64<rmw_16>, inst16_64>;
587 def : BinRMWPatExternalSym<i64, zext_bin_rmw_32_64<rmw_32>, inst32_64>;
589 def : BinRMWPatExternalSym<i32, sext_bin_rmw_8_32<rmw_8>, inst8_32>;
590 def : BinRMWPatExternalSym<i32, sext_bin_rmw_16_32<rmw_16>, inst16_32>;
591 def : BinRMWPatExternalSym<i64, sext_bin_rmw_8_64<rmw_8>, inst8_64>;
592 def : BinRMWPatExternalSym<i64, sext_bin_rmw_16_64<rmw_16>, inst16_64>;
594 // Truncating-extending binary RMWs with just a constant offset
595 def : BinRMWPatOffsetOnly<i32, zext_bin_rmw_8_32<rmw_8>, inst8_32>;
596 def : BinRMWPatOffsetOnly<i32, zext_bin_rmw_16_32<rmw_16>, inst16_32>;
597 def : BinRMWPatOffsetOnly<i64, zext_bin_rmw_8_64<rmw_8>, inst8_64>;
598 def : BinRMWPatOffsetOnly<i64, zext_bin_rmw_16_64<rmw_16>, inst16_64>;
599 def : BinRMWPatOffsetOnly<i64, zext_bin_rmw_32_64<rmw_32>, inst32_64>;
601 def : BinRMWPatOffsetOnly<i32, sext_bin_rmw_8_32<rmw_8>, inst8_32>;
602 def : BinRMWPatOffsetOnly<i32, sext_bin_rmw_16_32<rmw_16>, inst16_32>;
603 def : BinRMWPatOffsetOnly<i64, sext_bin_rmw_8_64<rmw_8>, inst8_64>;
604 def : BinRMWPatOffsetOnly<i64, sext_bin_rmw_16_64<rmw_16>, inst16_64>;
606 def : BinRMWPatGlobalAddrOffOnly<i32, zext_bin_rmw_8_32<rmw_8>, inst8_32>;
607 def : BinRMWPatGlobalAddrOffOnly<i32, zext_bin_rmw_16_32<rmw_16>, inst16_32>;
608 def : BinRMWPatGlobalAddrOffOnly<i64, zext_bin_rmw_8_64<rmw_8>, inst8_64>;
609 def : BinRMWPatGlobalAddrOffOnly<i64, zext_bin_rmw_16_64<rmw_16>, inst16_64>;
610 def : BinRMWPatGlobalAddrOffOnly<i64, zext_bin_rmw_32_64<rmw_32>, inst32_64>;
612 def : BinRMWPatGlobalAddrOffOnly<i32, sext_bin_rmw_8_32<rmw_8>, inst8_32>;
613 def : BinRMWPatGlobalAddrOffOnly<i32, sext_bin_rmw_16_32<rmw_16>, inst16_32>;
614 def : BinRMWPatGlobalAddrOffOnly<i64, sext_bin_rmw_8_64<rmw_8>, inst8_64>;
615 def : BinRMWPatGlobalAddrOffOnly<i64, sext_bin_rmw_16_64<rmw_16>, inst16_64>;
617 def : BinRMWPatExternSymOffOnly<i32, zext_bin_rmw_8_32<rmw_8>, inst8_32>;
618 def : BinRMWPatExternSymOffOnly<i32, zext_bin_rmw_16_32<rmw_16>, inst16_32>;
619 def : BinRMWPatExternSymOffOnly<i64, zext_bin_rmw_8_64<rmw_8>, inst8_64>;
620 def : BinRMWPatExternSymOffOnly<i64, zext_bin_rmw_16_64<rmw_16>, inst16_64>;
621 def : BinRMWPatExternSymOffOnly<i64, zext_bin_rmw_32_64<rmw_32>, inst32_64>;
623 def : BinRMWPatExternSymOffOnly<i32, sext_bin_rmw_8_32<rmw_8>, inst8_32>;
624 def : BinRMWPatExternSymOffOnly<i32, sext_bin_rmw_16_32<rmw_16>, inst16_32>;
625 def : BinRMWPatExternSymOffOnly<i64, sext_bin_rmw_8_64<rmw_8>, inst8_64>;
626 def : BinRMWPatExternSymOffOnly<i64, sext_bin_rmw_16_64<rmw_16>, inst16_64>;
629 let Predicates = [HasAtomics] in {
630 defm : BinRMWTruncExtPattern<
631 atomic_load_add_8, atomic_load_add_16, atomic_load_add_32, atomic_load_add_64,
632 ATOMIC_RMW8_U_ADD_I32, ATOMIC_RMW16_U_ADD_I32,
633 ATOMIC_RMW8_U_ADD_I64, ATOMIC_RMW16_U_ADD_I64, ATOMIC_RMW32_U_ADD_I64>;
634 defm : BinRMWTruncExtPattern<
635 atomic_load_sub_8, atomic_load_sub_16, atomic_load_sub_32, atomic_load_sub_64,
636 ATOMIC_RMW8_U_SUB_I32, ATOMIC_RMW16_U_SUB_I32,
637 ATOMIC_RMW8_U_SUB_I64, ATOMIC_RMW16_U_SUB_I64, ATOMIC_RMW32_U_SUB_I64>;
638 defm : BinRMWTruncExtPattern<
639 atomic_load_and_8, atomic_load_and_16, atomic_load_and_32, atomic_load_and_64,
640 ATOMIC_RMW8_U_AND_I32, ATOMIC_RMW16_U_AND_I32,
641 ATOMIC_RMW8_U_AND_I64, ATOMIC_RMW16_U_AND_I64, ATOMIC_RMW32_U_AND_I64>;
642 defm : BinRMWTruncExtPattern<
643 atomic_load_or_8, atomic_load_or_16, atomic_load_or_32, atomic_load_or_64,
644 ATOMIC_RMW8_U_OR_I32, ATOMIC_RMW16_U_OR_I32,
645 ATOMIC_RMW8_U_OR_I64, ATOMIC_RMW16_U_OR_I64, ATOMIC_RMW32_U_OR_I64>;
646 defm : BinRMWTruncExtPattern<
647 atomic_load_xor_8, atomic_load_xor_16, atomic_load_xor_32, atomic_load_xor_64,
648 ATOMIC_RMW8_U_XOR_I32, ATOMIC_RMW16_U_XOR_I32,
649 ATOMIC_RMW8_U_XOR_I64, ATOMIC_RMW16_U_XOR_I64, ATOMIC_RMW32_U_XOR_I64>;
650 defm : BinRMWTruncExtPattern<
651 atomic_swap_8, atomic_swap_16, atomic_swap_32, atomic_swap_64,
652 ATOMIC_RMW8_U_XCHG_I32, ATOMIC_RMW16_U_XCHG_I32,
653 ATOMIC_RMW8_U_XCHG_I64, ATOMIC_RMW16_U_XCHG_I64, ATOMIC_RMW32_U_XCHG_I64>;
654 } // Predicates = [HasAtomics]
656 //===----------------------------------------------------------------------===//
657 // Atomic ternary read-modify-writes
658 //===----------------------------------------------------------------------===//
660 // TODO LLVM IR's cmpxchg instruction returns a pair of {loaded value, success
661 // flag}. When we use the success flag or both values, we can't make use of i64
662 // truncate/extend versions of instructions for now, which is suboptimal.
663 // Consider adding a pass after instruction selection that optimizes this case
664 // if it is frequent.
666 multiclass WebAssemblyTerRMW<WebAssemblyRegClass rc, string Name, int Opcode> {
667 defm "" : I<(outs rc:$dst),
668 (ins P2Align:$p2align, offset32_op:$off, I32:$addr, rc:$exp,
670 (outs), (ins P2Align:$p2align, offset32_op:$off), [],
671 !strconcat(Name, "\t$dst, ${off}(${addr})${p2align}, $exp, $new"),
672 !strconcat(Name, "\t${off}, ${p2align}"), Opcode>;
675 defm ATOMIC_RMW_CMPXCHG_I32 :
676 WebAssemblyTerRMW<I32, "i32.atomic.rmw.cmpxchg", 0xfe48>;
677 defm ATOMIC_RMW_CMPXCHG_I64 :
678 WebAssemblyTerRMW<I64, "i64.atomic.rmw.cmpxchg", 0xfe49>;
679 defm ATOMIC_RMW8_U_CMPXCHG_I32 :
680 WebAssemblyTerRMW<I32, "i32.atomic.rmw8.cmpxchg_u", 0xfe4a>;
681 defm ATOMIC_RMW16_U_CMPXCHG_I32 :
682 WebAssemblyTerRMW<I32, "i32.atomic.rmw16.cmpxchg_u", 0xfe4b>;
683 defm ATOMIC_RMW8_U_CMPXCHG_I64 :
684 WebAssemblyTerRMW<I64, "i64.atomic.rmw8.cmpxchg_u", 0xfe4c>;
685 defm ATOMIC_RMW16_U_CMPXCHG_I64 :
686 WebAssemblyTerRMW<I64, "i64.atomic.rmw16.cmpxchg_u", 0xfe4d>;
687 defm ATOMIC_RMW32_U_CMPXCHG_I64 :
688 WebAssemblyTerRMW<I64, "i64.atomic.rmw32.cmpxchg_u", 0xfe4e>;
690 // Select ternary RMWs with no constant offset.
691 class TerRMWPatNoOffset<ValueType ty, PatFrag kind, NI inst> :
692 Pat<(ty (kind I32:$addr, ty:$exp, ty:$new)),
693 (inst 0, 0, I32:$addr, ty:$exp, ty:$new)>;
695 // Select ternary RMWs with a constant offset.
697 // Pattern with address + immediate offset
698 class TerRMWPatImmOff<ValueType ty, PatFrag kind, PatFrag operand, NI inst> :
699 Pat<(ty (kind (operand I32:$addr, imm:$off), ty:$exp, ty:$new)),
700 (inst 0, imm:$off, I32:$addr, ty:$exp, ty:$new)>;
702 class TerRMWPatGlobalAddr<ValueType ty, PatFrag kind, NI inst> :
703 Pat<(ty (kind (regPlusGA I32:$addr, (WebAssemblywrapper tglobaladdr:$off)),
705 (inst 0, tglobaladdr:$off, I32:$addr, ty:$exp, ty:$new)>;
707 class TerRMWPatExternalSym<ValueType ty, PatFrag kind, NI inst> :
708 Pat<(ty (kind (add I32:$addr, (WebAssemblywrapper texternalsym:$off)),
710 (inst 0, texternalsym:$off, I32:$addr, ty:$exp, ty:$new)>;
712 // Select ternary RMWs with just a constant offset.
713 class TerRMWPatOffsetOnly<ValueType ty, PatFrag kind, NI inst> :
714 Pat<(ty (kind imm:$off, ty:$exp, ty:$new)),
715 (inst 0, imm:$off, (CONST_I32 0), ty:$exp, ty:$new)>;
717 class TerRMWPatGlobalAddrOffOnly<ValueType ty, PatFrag kind, NI inst> :
718 Pat<(ty (kind (WebAssemblywrapper tglobaladdr:$off), ty:$exp, ty:$new)),
719 (inst 0, tglobaladdr:$off, (CONST_I32 0), ty:$exp, ty:$new)>;
721 class TerRMWPatExternSymOffOnly<ValueType ty, PatFrag kind, NI inst> :
722 Pat<(ty (kind (WebAssemblywrapper texternalsym:$off), ty:$exp, ty:$new)),
723 (inst 0, texternalsym:$off, (CONST_I32 0), ty:$exp, ty:$new)>;
725 // Patterns for various addressing modes.
726 multiclass TerRMWPattern<PatFrag rmw_32, PatFrag rmw_64, NI inst_32,
728 def : TerRMWPatNoOffset<i32, rmw_32, inst_32>;
729 def : TerRMWPatNoOffset<i64, rmw_64, inst_64>;
731 def : TerRMWPatImmOff<i32, rmw_32, regPlusImm, inst_32>;
732 def : TerRMWPatImmOff<i64, rmw_64, regPlusImm, inst_64>;
733 def : TerRMWPatImmOff<i32, rmw_32, or_is_add, inst_32>;
734 def : TerRMWPatImmOff<i64, rmw_64, or_is_add, inst_64>;
736 def : TerRMWPatGlobalAddr<i32, rmw_32, inst_32>;
737 def : TerRMWPatGlobalAddr<i64, rmw_64, inst_64>;
739 def : TerRMWPatExternalSym<i32, rmw_32, inst_32>;
740 def : TerRMWPatExternalSym<i64, rmw_64, inst_64>;
742 def : TerRMWPatOffsetOnly<i32, rmw_32, inst_32>;
743 def : TerRMWPatOffsetOnly<i64, rmw_64, inst_64>;
745 def : TerRMWPatGlobalAddrOffOnly<i32, rmw_32, inst_32>;
746 def : TerRMWPatGlobalAddrOffOnly<i64, rmw_64, inst_64>;
748 def : TerRMWPatExternSymOffOnly<i32, rmw_32, inst_32>;
749 def : TerRMWPatExternSymOffOnly<i64, rmw_64, inst_64>;
752 let Predicates = [HasAtomics] in {
753 defm : TerRMWPattern<atomic_cmp_swap_32, atomic_cmp_swap_64,
754 ATOMIC_RMW_CMPXCHG_I32, ATOMIC_RMW_CMPXCHG_I64>;
755 } // Predicates = [HasAtomics]
757 // Truncating & zero-extending ternary RMW patterns.
758 // DAG legalization & optimization before instruction selection may introduce
759 // additional nodes such as anyext or assertzext depending on operand types.
760 class zext_ter_rmw_8_32<PatFrag kind> :
761 PatFrag<(ops node:$addr, node:$exp, node:$new),
762 (and (i32 (kind node:$addr, node:$exp, node:$new)), 255)>;
763 class zext_ter_rmw_16_32<PatFrag kind> :
764 PatFrag<(ops node:$addr, node:$exp, node:$new),
765 (and (i32 (kind node:$addr, node:$exp, node:$new)), 65535)>;
766 class zext_ter_rmw_8_64<PatFrag kind> :
767 PatFrag<(ops node:$addr, node:$exp, node:$new),
768 (zext (i32 (assertzext (i32 (kind node:$addr,
769 (i32 (trunc (i64 node:$exp))),
770 (i32 (trunc (i64 node:$new))))))))>;
771 class zext_ter_rmw_16_64<PatFrag kind> : zext_ter_rmw_8_64<kind>;
772 class zext_ter_rmw_32_64<PatFrag kind> :
773 PatFrag<(ops node:$addr, node:$exp, node:$new),
774 (zext (i32 (kind node:$addr,
775 (i32 (trunc (i64 node:$exp))),
776 (i32 (trunc (i64 node:$new))))))>;
778 // Truncating & sign-extending ternary RMW patterns.
779 // We match subword RMWs (for 32-bit) and anyext RMWs (for 64-bit) and select a
780 // zext RMW; the next instruction will be sext_inreg which is selected by
782 class sext_ter_rmw_8_32<PatFrag kind> :
783 PatFrag<(ops node:$addr, node:$exp, node:$new),
784 (kind node:$addr, node:$exp, node:$new)>;
785 class sext_ter_rmw_16_32<PatFrag kind> : sext_ter_rmw_8_32<kind>;
786 class sext_ter_rmw_8_64<PatFrag kind> :
787 PatFrag<(ops node:$addr, node:$exp, node:$new),
788 (anyext (i32 (assertzext (i32
790 (i32 (trunc (i64 node:$exp))),
791 (i32 (trunc (i64 node:$new))))))))>;
792 class sext_ter_rmw_16_64<PatFrag kind> : sext_ter_rmw_8_64<kind>;
793 // 32->64 sext RMW gets selected as i32.atomic.rmw.***, i64.extend_i32_s
795 // Patterns for various addressing modes for truncating-extending ternary RMWs.
796 multiclass TerRMWTruncExtPattern<
797 PatFrag rmw_8, PatFrag rmw_16, PatFrag rmw_32, PatFrag rmw_64,
798 NI inst8_32, NI inst16_32, NI inst8_64, NI inst16_64, NI inst32_64> {
799 // Truncating-extending ternary RMWs with no constant offset
800 def : TerRMWPatNoOffset<i32, zext_ter_rmw_8_32<rmw_8>, inst8_32>;
801 def : TerRMWPatNoOffset<i32, zext_ter_rmw_16_32<rmw_16>, inst16_32>;
802 def : TerRMWPatNoOffset<i64, zext_ter_rmw_8_64<rmw_8>, inst8_64>;
803 def : TerRMWPatNoOffset<i64, zext_ter_rmw_16_64<rmw_16>, inst16_64>;
804 def : TerRMWPatNoOffset<i64, zext_ter_rmw_32_64<rmw_32>, inst32_64>;
806 def : TerRMWPatNoOffset<i32, sext_ter_rmw_8_32<rmw_8>, inst8_32>;
807 def : TerRMWPatNoOffset<i32, sext_ter_rmw_16_32<rmw_16>, inst16_32>;
808 def : TerRMWPatNoOffset<i64, sext_ter_rmw_8_64<rmw_8>, inst8_64>;
809 def : TerRMWPatNoOffset<i64, sext_ter_rmw_16_64<rmw_16>, inst16_64>;
811 // Truncating-extending ternary RMWs with a constant offset
812 def : TerRMWPatImmOff<i32, zext_ter_rmw_8_32<rmw_8>, regPlusImm, inst8_32>;
813 def : TerRMWPatImmOff<i32, zext_ter_rmw_16_32<rmw_16>, regPlusImm, inst16_32>;
814 def : TerRMWPatImmOff<i64, zext_ter_rmw_8_64<rmw_8>, regPlusImm, inst8_64>;
815 def : TerRMWPatImmOff<i64, zext_ter_rmw_16_64<rmw_16>, regPlusImm, inst16_64>;
816 def : TerRMWPatImmOff<i64, zext_ter_rmw_32_64<rmw_32>, regPlusImm, inst32_64>;
817 def : TerRMWPatImmOff<i32, zext_ter_rmw_8_32<rmw_8>, or_is_add, inst8_32>;
818 def : TerRMWPatImmOff<i32, zext_ter_rmw_16_32<rmw_16>, or_is_add, inst16_32>;
819 def : TerRMWPatImmOff<i64, zext_ter_rmw_8_64<rmw_8>, or_is_add, inst8_64>;
820 def : TerRMWPatImmOff<i64, zext_ter_rmw_16_64<rmw_16>, or_is_add, inst16_64>;
821 def : TerRMWPatImmOff<i64, zext_ter_rmw_32_64<rmw_32>, or_is_add, inst32_64>;
823 def : TerRMWPatImmOff<i32, sext_ter_rmw_8_32<rmw_8>, regPlusImm, inst8_32>;
824 def : TerRMWPatImmOff<i32, sext_ter_rmw_16_32<rmw_16>, regPlusImm, inst16_32>;
825 def : TerRMWPatImmOff<i64, sext_ter_rmw_8_64<rmw_8>, regPlusImm, inst8_64>;
826 def : TerRMWPatImmOff<i64, sext_ter_rmw_16_64<rmw_16>, regPlusImm, inst16_64>;
827 def : TerRMWPatImmOff<i32, sext_ter_rmw_8_32<rmw_8>, or_is_add, inst8_32>;
828 def : TerRMWPatImmOff<i32, sext_ter_rmw_16_32<rmw_16>, or_is_add, inst16_32>;
829 def : TerRMWPatImmOff<i64, sext_ter_rmw_8_64<rmw_8>, or_is_add, inst8_64>;
830 def : TerRMWPatImmOff<i64, sext_ter_rmw_16_64<rmw_16>, or_is_add, inst16_64>;
832 def : TerRMWPatGlobalAddr<i32, zext_ter_rmw_8_32<rmw_8>, inst8_32>;
833 def : TerRMWPatGlobalAddr<i32, zext_ter_rmw_16_32<rmw_16>, inst16_32>;
834 def : TerRMWPatGlobalAddr<i64, zext_ter_rmw_8_64<rmw_8>, inst8_64>;
835 def : TerRMWPatGlobalAddr<i64, zext_ter_rmw_16_64<rmw_16>, inst16_64>;
836 def : TerRMWPatGlobalAddr<i64, zext_ter_rmw_32_64<rmw_32>, inst32_64>;
838 def : TerRMWPatGlobalAddr<i32, sext_ter_rmw_8_32<rmw_8>, inst8_32>;
839 def : TerRMWPatGlobalAddr<i32, sext_ter_rmw_16_32<rmw_16>, inst16_32>;
840 def : TerRMWPatGlobalAddr<i64, sext_ter_rmw_8_64<rmw_8>, inst8_64>;
841 def : TerRMWPatGlobalAddr<i64, sext_ter_rmw_16_64<rmw_16>, inst16_64>;
843 def : TerRMWPatExternalSym<i32, zext_ter_rmw_8_32<rmw_8>, inst8_32>;
844 def : TerRMWPatExternalSym<i32, zext_ter_rmw_16_32<rmw_16>, inst16_32>;
845 def : TerRMWPatExternalSym<i64, zext_ter_rmw_8_64<rmw_8>, inst8_64>;
846 def : TerRMWPatExternalSym<i64, zext_ter_rmw_16_64<rmw_16>, inst16_64>;
847 def : TerRMWPatExternalSym<i64, zext_ter_rmw_32_64<rmw_32>, inst32_64>;
849 def : TerRMWPatExternalSym<i32, sext_ter_rmw_8_32<rmw_8>, inst8_32>;
850 def : TerRMWPatExternalSym<i32, sext_ter_rmw_16_32<rmw_16>, inst16_32>;
851 def : TerRMWPatExternalSym<i64, sext_ter_rmw_8_64<rmw_8>, inst8_64>;
852 def : TerRMWPatExternalSym<i64, sext_ter_rmw_16_64<rmw_16>, inst16_64>;
854 // Truncating-extending ternary RMWs with just a constant offset
855 def : TerRMWPatOffsetOnly<i32, zext_ter_rmw_8_32<rmw_8>, inst8_32>;
856 def : TerRMWPatOffsetOnly<i32, zext_ter_rmw_16_32<rmw_16>, inst16_32>;
857 def : TerRMWPatOffsetOnly<i64, zext_ter_rmw_8_64<rmw_8>, inst8_64>;
858 def : TerRMWPatOffsetOnly<i64, zext_ter_rmw_16_64<rmw_16>, inst16_64>;
859 def : TerRMWPatOffsetOnly<i64, zext_ter_rmw_32_64<rmw_32>, inst32_64>;
861 def : TerRMWPatOffsetOnly<i32, sext_ter_rmw_8_32<rmw_8>, inst8_32>;
862 def : TerRMWPatOffsetOnly<i32, sext_ter_rmw_16_32<rmw_16>, inst16_32>;
863 def : TerRMWPatOffsetOnly<i64, sext_ter_rmw_8_64<rmw_8>, inst8_64>;
864 def : TerRMWPatOffsetOnly<i64, sext_ter_rmw_16_64<rmw_16>, inst16_64>;
866 def : TerRMWPatGlobalAddrOffOnly<i32, zext_ter_rmw_8_32<rmw_8>, inst8_32>;
867 def : TerRMWPatGlobalAddrOffOnly<i32, zext_ter_rmw_16_32<rmw_16>, inst16_32>;
868 def : TerRMWPatGlobalAddrOffOnly<i64, zext_ter_rmw_8_64<rmw_8>, inst8_64>;
869 def : TerRMWPatGlobalAddrOffOnly<i64, zext_ter_rmw_16_64<rmw_16>, inst16_64>;
870 def : TerRMWPatGlobalAddrOffOnly<i64, zext_ter_rmw_32_64<rmw_32>, inst32_64>;
872 def : TerRMWPatGlobalAddrOffOnly<i32, sext_ter_rmw_8_32<rmw_8>, inst8_32>;
873 def : TerRMWPatGlobalAddrOffOnly<i32, sext_ter_rmw_16_32<rmw_16>, inst16_32>;
874 def : TerRMWPatGlobalAddrOffOnly<i64, sext_ter_rmw_8_64<rmw_8>, inst8_64>;
875 def : TerRMWPatGlobalAddrOffOnly<i64, sext_ter_rmw_16_64<rmw_16>, inst16_64>;
877 def : TerRMWPatExternSymOffOnly<i32, zext_ter_rmw_8_32<rmw_8>, inst8_32>;
878 def : TerRMWPatExternSymOffOnly<i32, zext_ter_rmw_16_32<rmw_16>, inst16_32>;
879 def : TerRMWPatExternSymOffOnly<i64, zext_ter_rmw_8_64<rmw_8>, inst8_64>;
880 def : TerRMWPatExternSymOffOnly<i64, zext_ter_rmw_16_64<rmw_16>, inst16_64>;
881 def : TerRMWPatExternSymOffOnly<i64, zext_ter_rmw_32_64<rmw_32>, inst32_64>;
883 def : TerRMWPatExternSymOffOnly<i32, sext_ter_rmw_8_32<rmw_8>, inst8_32>;
884 def : TerRMWPatExternSymOffOnly<i32, sext_ter_rmw_16_32<rmw_16>, inst16_32>;
885 def : TerRMWPatExternSymOffOnly<i64, sext_ter_rmw_8_64<rmw_8>, inst8_64>;
886 def : TerRMWPatExternSymOffOnly<i64, sext_ter_rmw_16_64<rmw_16>, inst16_64>;
889 let Predicates = [HasAtomics] in {
890 defm : TerRMWTruncExtPattern<
891 atomic_cmp_swap_8, atomic_cmp_swap_16, atomic_cmp_swap_32, atomic_cmp_swap_64,
892 ATOMIC_RMW8_U_CMPXCHG_I32, ATOMIC_RMW16_U_CMPXCHG_I32,
893 ATOMIC_RMW8_U_CMPXCHG_I64, ATOMIC_RMW16_U_CMPXCHG_I64,
894 ATOMIC_RMW32_U_CMPXCHG_I64>;
897 //===----------------------------------------------------------------------===//
898 // Atomic wait / notify
899 //===----------------------------------------------------------------------===//
901 let hasSideEffects = 1 in {
904 (ins P2Align:$p2align, offset32_op:$off, I32:$addr, I32:$count),
905 (outs), (ins P2Align:$p2align, offset32_op:$off), [],
906 "atomic.notify \t$dst, ${off}(${addr})${p2align}, $count",
907 "atomic.notify \t${off}, ${p2align}", 0xfe00>;
909 defm ATOMIC_WAIT_I32 :
911 (ins P2Align:$p2align, offset32_op:$off, I32:$addr, I32:$exp, I64:$timeout),
912 (outs), (ins P2Align:$p2align, offset32_op:$off), [],
913 "i32.atomic.wait \t$dst, ${off}(${addr})${p2align}, $exp, $timeout",
914 "i32.atomic.wait \t${off}, ${p2align}", 0xfe01>;
915 defm ATOMIC_WAIT_I64 :
917 (ins P2Align:$p2align, offset32_op:$off, I32:$addr, I64:$exp, I64:$timeout),
918 (outs), (ins P2Align:$p2align, offset32_op:$off), [],
919 "i64.atomic.wait \t$dst, ${off}(${addr})${p2align}, $exp, $timeout",
920 "i64.atomic.wait \t${off}, ${p2align}", 0xfe02>;
922 } // hasSideEffects = 1
924 let Predicates = [HasAtomics] in {
925 // Select notifys with no constant offset.
926 class NotifyPatNoOffset<Intrinsic kind> :
927 Pat<(i32 (kind I32:$addr, I32:$count)),
928 (ATOMIC_NOTIFY 0, 0, I32:$addr, I32:$count)>;
929 def : NotifyPatNoOffset<int_wasm_atomic_notify>;
931 // Select notifys with a constant offset.
933 // Pattern with address + immediate offset
934 class NotifyPatImmOff<Intrinsic kind, PatFrag operand> :
935 Pat<(i32 (kind (operand I32:$addr, imm:$off), I32:$count)),
936 (ATOMIC_NOTIFY 0, imm:$off, I32:$addr, I32:$count)>;
937 def : NotifyPatImmOff<int_wasm_atomic_notify, regPlusImm>;
938 def : NotifyPatImmOff<int_wasm_atomic_notify, or_is_add>;
940 class NotifyPatGlobalAddr<Intrinsic kind> :
941 Pat<(i32 (kind (regPlusGA I32:$addr, (WebAssemblywrapper tglobaladdr:$off)),
943 (ATOMIC_NOTIFY 0, tglobaladdr:$off, I32:$addr, I32:$count)>;
944 def : NotifyPatGlobalAddr<int_wasm_atomic_notify>;
946 class NotifyPatExternalSym<Intrinsic kind> :
947 Pat<(i32 (kind (add I32:$addr, (WebAssemblywrapper texternalsym:$off)),
949 (ATOMIC_NOTIFY 0, texternalsym:$off, I32:$addr, I32:$count)>;
950 def : NotifyPatExternalSym<int_wasm_atomic_notify>;
952 // Select notifys with just a constant offset.
953 class NotifyPatOffsetOnly<Intrinsic kind> :
954 Pat<(i32 (kind imm:$off, I32:$count)),
955 (ATOMIC_NOTIFY 0, imm:$off, (CONST_I32 0), I32:$count)>;
956 def : NotifyPatOffsetOnly<int_wasm_atomic_notify>;
958 class NotifyPatGlobalAddrOffOnly<Intrinsic kind> :
959 Pat<(i32 (kind (WebAssemblywrapper tglobaladdr:$off), I32:$count)),
960 (ATOMIC_NOTIFY 0, tglobaladdr:$off, (CONST_I32 0), I32:$count)>;
961 def : NotifyPatGlobalAddrOffOnly<int_wasm_atomic_notify>;
963 class NotifyPatExternSymOffOnly<Intrinsic kind> :
964 Pat<(i32 (kind (WebAssemblywrapper texternalsym:$off), I32:$count)),
965 (ATOMIC_NOTIFY 0, texternalsym:$off, (CONST_I32 0), I32:$count)>;
966 def : NotifyPatExternSymOffOnly<int_wasm_atomic_notify>;
968 // Select waits with no constant offset.
969 class WaitPatNoOffset<ValueType ty, Intrinsic kind, NI inst> :
970 Pat<(i32 (kind I32:$addr, ty:$exp, I64:$timeout)),
971 (inst 0, 0, I32:$addr, ty:$exp, I64:$timeout)>;
972 def : WaitPatNoOffset<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
973 def : WaitPatNoOffset<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
975 // Select waits with a constant offset.
977 // Pattern with address + immediate offset
978 class WaitPatImmOff<ValueType ty, Intrinsic kind, PatFrag operand, NI inst> :
979 Pat<(i32 (kind (operand I32:$addr, imm:$off), ty:$exp, I64:$timeout)),
980 (inst 0, imm:$off, I32:$addr, ty:$exp, I64:$timeout)>;
981 def : WaitPatImmOff<i32, int_wasm_atomic_wait_i32, regPlusImm, ATOMIC_WAIT_I32>;
982 def : WaitPatImmOff<i32, int_wasm_atomic_wait_i32, or_is_add, ATOMIC_WAIT_I32>;
983 def : WaitPatImmOff<i64, int_wasm_atomic_wait_i64, regPlusImm, ATOMIC_WAIT_I64>;
984 def : WaitPatImmOff<i64, int_wasm_atomic_wait_i64, or_is_add, ATOMIC_WAIT_I64>;
986 class WaitPatGlobalAddr<ValueType ty, Intrinsic kind, NI inst> :
987 Pat<(i32 (kind (regPlusGA I32:$addr, (WebAssemblywrapper tglobaladdr:$off)),
988 ty:$exp, I64:$timeout)),
989 (inst 0, tglobaladdr:$off, I32:$addr, ty:$exp, I64:$timeout)>;
990 def : WaitPatGlobalAddr<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
991 def : WaitPatGlobalAddr<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
993 class WaitPatExternalSym<ValueType ty, Intrinsic kind, NI inst> :
994 Pat<(i32 (kind (add I32:$addr, (WebAssemblywrapper texternalsym:$off)),
995 ty:$exp, I64:$timeout)),
996 (inst 0, texternalsym:$off, I32:$addr, ty:$exp, I64:$timeout)>;
997 def : WaitPatExternalSym<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
998 def : WaitPatExternalSym<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
1000 // Select wait_i32, ATOMIC_WAIT_I32s with just a constant offset.
1001 class WaitPatOffsetOnly<ValueType ty, Intrinsic kind, NI inst> :
1002 Pat<(i32 (kind imm:$off, ty:$exp, I64:$timeout)),
1003 (inst 0, imm:$off, (CONST_I32 0), ty:$exp, I64:$timeout)>;
1004 def : WaitPatOffsetOnly<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
1005 def : WaitPatOffsetOnly<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
1007 class WaitPatGlobalAddrOffOnly<ValueType ty, Intrinsic kind, NI inst> :
1008 Pat<(i32 (kind (WebAssemblywrapper tglobaladdr:$off), ty:$exp, I64:$timeout)),
1009 (inst 0, tglobaladdr:$off, (CONST_I32 0), ty:$exp, I64:$timeout)>;
1010 def : WaitPatGlobalAddrOffOnly<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
1011 def : WaitPatGlobalAddrOffOnly<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
1013 class WaitPatExternSymOffOnly<ValueType ty, Intrinsic kind, NI inst> :
1014 Pat<(i32 (kind (WebAssemblywrapper texternalsym:$off), ty:$exp,
1016 (inst 0, texternalsym:$off, (CONST_I32 0), ty:$exp, I64:$timeout)>;
1017 def : WaitPatExternSymOffOnly<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
1018 def : WaitPatExternSymOffOnly<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
1019 } // Predicates = [HasAtomics]