1 //===-- WebAssemblyInstrInfo.cpp - WebAssembly Instruction Information ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file contains the WebAssembly implementation of the
12 /// TargetInstrInfo class.
14 //===----------------------------------------------------------------------===//
16 #include "WebAssemblyInstrInfo.h"
17 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
18 #include "WebAssemblyMachineFunctionInfo.h"
19 #include "WebAssemblySubtarget.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #define DEBUG_TYPE "wasm-instr-info"
28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "WebAssemblyGenInstrInfo.inc"
31 WebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
32 : WebAssemblyGenInstrInfo(WebAssembly::ADJCALLSTACKDOWN,
33 WebAssembly::ADJCALLSTACKUP),
34 RI(STI.getTargetTriple()) {}
36 bool WebAssemblyInstrInfo::isReallyTriviallyReMaterializable(
37 const MachineInstr &MI, AliasAnalysis *AA) const {
38 switch (MI.getOpcode()) {
39 case WebAssembly::CONST_I32:
40 case WebAssembly::CONST_I64:
41 case WebAssembly::CONST_F32:
42 case WebAssembly::CONST_F64:
43 // isReallyTriviallyReMaterializableGeneric misses these because of the
44 // ARGUMENTS implicit def, so we manualy override it here.
51 void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
52 MachineBasicBlock::iterator I,
53 const DebugLoc &DL, unsigned DestReg,
54 unsigned SrcReg, bool KillSrc) const {
55 // This method is called by post-RA expansion, which expects only pregs to
56 // exist. However we need to handle both here.
57 auto &MRI = MBB.getParent()->getRegInfo();
58 const TargetRegisterClass *RC =
59 TargetRegisterInfo::isVirtualRegister(DestReg)
60 ? MRI.getRegClass(DestReg)
61 : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg);
64 if (RC == &WebAssembly::I32RegClass)
65 CopyOpcode = WebAssembly::COPY_I32;
66 else if (RC == &WebAssembly::I64RegClass)
67 CopyOpcode = WebAssembly::COPY_I64;
68 else if (RC == &WebAssembly::F32RegClass)
69 CopyOpcode = WebAssembly::COPY_F32;
70 else if (RC == &WebAssembly::F64RegClass)
71 CopyOpcode = WebAssembly::COPY_F64;
73 llvm_unreachable("Unexpected register class");
75 BuildMI(MBB, I, DL, get(CopyOpcode), DestReg)
76 .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
80 WebAssemblyInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
82 unsigned OpIdx2) const {
83 // If the operands are stackified, we can't reorder them.
84 WebAssemblyFunctionInfo &MFI =
85 *MI.getParent()->getParent()->getInfo<WebAssemblyFunctionInfo>();
86 if (MFI.isVRegStackified(MI.getOperand(OpIdx1).getReg()) ||
87 MFI.isVRegStackified(MI.getOperand(OpIdx2).getReg()))
90 // Otherwise use the default implementation.
91 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
95 bool WebAssemblyInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
96 MachineBasicBlock *&TBB,
97 MachineBasicBlock *&FBB,
98 SmallVectorImpl<MachineOperand> &Cond,
99 bool /*AllowModify*/) const {
100 bool HaveCond = false;
101 for (MachineInstr &MI : MBB.terminators()) {
102 switch (MI.getOpcode()) {
104 // Unhandled instruction; bail out.
106 case WebAssembly::BR_IF:
109 // If we're running after CFGStackify, we can't optimize further.
110 if (!MI.getOperand(0).isMBB())
112 Cond.push_back(MachineOperand::CreateImm(true));
113 Cond.push_back(MI.getOperand(1));
114 TBB = MI.getOperand(0).getMBB();
117 case WebAssembly::BR_UNLESS:
120 // If we're running after CFGStackify, we can't optimize further.
121 if (!MI.getOperand(0).isMBB())
123 Cond.push_back(MachineOperand::CreateImm(false));
124 Cond.push_back(MI.getOperand(1));
125 TBB = MI.getOperand(0).getMBB();
128 case WebAssembly::BR:
129 // If we're running after CFGStackify, we can't optimize further.
130 if (!MI.getOperand(0).isMBB())
133 TBB = MI.getOperand(0).getMBB();
135 FBB = MI.getOperand(0).getMBB();
145 unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB,
146 int *BytesRemoved) const {
147 assert(!BytesRemoved && "code size not handled");
149 MachineBasicBlock::instr_iterator I = MBB.instr_end();
152 while (I != MBB.instr_begin()) {
154 if (I->isDebugValue())
156 if (!I->isTerminator())
158 // Remove the branch.
159 I->eraseFromParent();
167 unsigned WebAssemblyInstrInfo::insertBranch(MachineBasicBlock &MBB,
168 MachineBasicBlock *TBB,
169 MachineBasicBlock *FBB,
170 ArrayRef<MachineOperand> Cond,
172 int *BytesAdded) const {
173 assert(!BytesAdded && "code size not handled");
179 BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
183 assert(Cond.size() == 2 && "Expected a flag and a successor block");
185 if (Cond[0].getImm()) {
186 BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]);
188 BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]);
193 BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
197 bool WebAssemblyInstrInfo::reverseBranchCondition(
198 SmallVectorImpl<MachineOperand> &Cond) const {
199 assert(Cond.size() == 2 && "Expected a flag and a successor block");
200 Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());