1 //===-- WebAssemblyLowerBrUnless.cpp - Lower br_unless --------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// This file lowers br_unless into br_if with an inverted condition.
12 /// br_unless is not currently in the spec, but it's very convenient for LLVM
13 /// to use. This pass allows LLVM to use it, for now.
15 //===----------------------------------------------------------------------===//
17 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
18 #include "WebAssembly.h"
19 #include "WebAssemblyMachineFunctionInfo.h"
20 #include "WebAssemblySubtarget.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/raw_ostream.h"
27 #define DEBUG_TYPE "wasm-lower-br_unless"
30 class WebAssemblyLowerBrUnless final : public MachineFunctionPass {
31 StringRef getPassName() const override {
32 return "WebAssembly Lower br_unless";
35 void getAnalysisUsage(AnalysisUsage &AU) const override {
37 MachineFunctionPass::getAnalysisUsage(AU);
40 bool runOnMachineFunction(MachineFunction &MF) override;
43 static char ID; // Pass identification, replacement for typeid
44 WebAssemblyLowerBrUnless() : MachineFunctionPass(ID) {}
46 } // end anonymous namespace
48 char WebAssemblyLowerBrUnless::ID = 0;
49 INITIALIZE_PASS(WebAssemblyLowerBrUnless, DEBUG_TYPE,
50 "Lowers br_unless into inverted br_if", false, false)
52 FunctionPass *llvm::createWebAssemblyLowerBrUnless() {
53 return new WebAssemblyLowerBrUnless();
56 bool WebAssemblyLowerBrUnless::runOnMachineFunction(MachineFunction &MF) {
57 LLVM_DEBUG(dbgs() << "********** Lowering br_unless **********\n"
58 "********** Function: "
59 << MF.getName() << '\n');
61 auto &MFI = *MF.getInfo<WebAssemblyFunctionInfo>();
62 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
63 auto &MRI = MF.getRegInfo();
65 for (auto &MBB : MF) {
66 for (auto MII = MBB.begin(); MII != MBB.end();) {
67 MachineInstr *MI = &*MII++;
68 if (MI->getOpcode() != WebAssembly::BR_UNLESS)
71 unsigned Cond = MI->getOperand(1).getReg();
72 bool Inverted = false;
74 // Attempt to invert the condition in place.
75 if (MFI.isVRegStackified(Cond)) {
76 assert(MRI.hasOneDef(Cond));
77 MachineInstr *Def = MRI.getVRegDef(Cond);
78 switch (Def->getOpcode()) {
79 using namespace WebAssembly;
81 Def->setDesc(TII.get(NE_I32));
85 Def->setDesc(TII.get(EQ_I32));
89 Def->setDesc(TII.get(LE_S_I32));
93 Def->setDesc(TII.get(LT_S_I32));
97 Def->setDesc(TII.get(GE_S_I32));
101 Def->setDesc(TII.get(GT_S_I32));
105 Def->setDesc(TII.get(LE_U_I32));
109 Def->setDesc(TII.get(LT_U_I32));
113 Def->setDesc(TII.get(GE_U_I32));
117 Def->setDesc(TII.get(GT_U_I32));
121 Def->setDesc(TII.get(NE_I64));
125 Def->setDesc(TII.get(EQ_I64));
129 Def->setDesc(TII.get(LE_S_I64));
133 Def->setDesc(TII.get(LT_S_I64));
137 Def->setDesc(TII.get(GE_S_I64));
141 Def->setDesc(TII.get(GT_S_I64));
145 Def->setDesc(TII.get(LE_U_I64));
149 Def->setDesc(TII.get(LT_U_I64));
153 Def->setDesc(TII.get(GE_U_I64));
157 Def->setDesc(TII.get(GT_U_I64));
161 Def->setDesc(TII.get(NE_F32));
165 Def->setDesc(TII.get(EQ_F32));
169 Def->setDesc(TII.get(NE_F64));
173 Def->setDesc(TII.get(EQ_F64));
177 // Invert an eqz by replacing it with its operand.
178 Cond = Def->getOperand(1).getReg();
179 Def->eraseFromParent();
188 // If we weren't able to invert the condition in place. Insert an
189 // instruction to invert it.
191 unsigned Tmp = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
192 BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::EQZ_I32), Tmp)
194 MFI.stackifyVReg(Tmp);
199 // The br_unless condition has now been inverted. Insert a br_if and
200 // delete the br_unless.
202 BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::BR_IF))
203 .add(MI->getOperand(0))