1 //===-- WebAssemblyRegisterInfo.cpp - WebAssembly Register Information ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file contains the WebAssembly implementation of the
12 /// TargetRegisterInfo class.
14 //===----------------------------------------------------------------------===//
16 #include "WebAssemblyRegisterInfo.h"
17 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
18 #include "WebAssemblyFrameLowering.h"
19 #include "WebAssemblyInstrInfo.h"
20 #include "WebAssemblyMachineFunctionInfo.h"
21 #include "WebAssemblySubtarget.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Target/TargetFrameLowering.h"
28 #include "llvm/Target/TargetOptions.h"
31 #define DEBUG_TYPE "wasm-reg-info"
33 #define GET_REGINFO_TARGET_DESC
34 #include "WebAssemblyGenRegisterInfo.inc"
36 WebAssemblyRegisterInfo::WebAssemblyRegisterInfo(const Triple &TT)
37 : WebAssemblyGenRegisterInfo(0), TT(TT) {}
40 WebAssemblyRegisterInfo::getCalleeSavedRegs(const MachineFunction *) const {
41 static const MCPhysReg CalleeSavedRegs[] = {0};
42 return CalleeSavedRegs;
46 WebAssemblyRegisterInfo::getReservedRegs(const MachineFunction & /*MF*/) const {
47 BitVector Reserved(getNumRegs());
48 for (auto Reg : {WebAssembly::SP32, WebAssembly::SP64, WebAssembly::FP32,
54 void WebAssemblyRegisterInfo::eliminateFrameIndex(
55 MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum,
56 RegScavenger * /*RS*/) const {
58 MachineInstr &MI = *II;
60 MachineBasicBlock &MBB = *MI.getParent();
61 MachineFunction &MF = *MBB.getParent();
62 MachineRegisterInfo &MRI = MF.getRegInfo();
63 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
64 const MachineFrameInfo &MFI = *MF.getFrameInfo();
65 int64_t FrameOffset = MFI.getStackSize() + MFI.getObjectOffset(FrameIndex);
67 // If this is the address operand of a load or store, make it relative to SP
68 // and fold the frame offset directly in.
69 if (MI.mayLoadOrStore() && FIOperandNum == WebAssembly::MemOpAddressOperandNo) {
70 assert(FrameOffset >= 0 && MI.getOperand(1).getImm() >= 0);
71 int64_t Offset = MI.getOperand(1).getImm() + FrameOffset;
73 if (static_cast<uint64_t>(Offset) <= std::numeric_limits<uint32_t>::max()) {
74 MI.getOperand(FIOperandNum - 1).setImm(Offset);
75 MI.getOperand(FIOperandNum)
76 .ChangeToRegister(WebAssembly::SP32, /*IsDef=*/false);
81 // If this is an address being added to a constant, fold the frame offset
83 if (MI.getOpcode() == WebAssembly::ADD_I32) {
84 MachineOperand &OtherMO = MI.getOperand(3 - FIOperandNum);
85 if (OtherMO.isReg()) {
86 unsigned OtherMOReg = OtherMO.getReg();
87 if (TargetRegisterInfo::isVirtualRegister(OtherMOReg)) {
88 MachineInstr *Def = MF.getRegInfo().getUniqueVRegDef(OtherMOReg);
89 // TODO: For now we just opportunistically do this in the case where
90 // the CONST_I32 happens to have exactly one def and one use. We
91 // should generalize this to optimize in more cases.
92 if (Def && Def->getOpcode() == WebAssembly::CONST_I32 &&
93 MRI.hasOneNonDBGUse(Def->getOperand(0).getReg())) {
94 MachineOperand &ImmMO = Def->getOperand(1);
95 ImmMO.setImm(ImmMO.getImm() + uint32_t(FrameOffset));
96 MI.getOperand(FIOperandNum)
97 .ChangeToRegister(WebAssembly::SP32, /*IsDef=*/false);
104 // Otherwise create an i32.add SP, offset and make it the operand.
105 const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
107 unsigned FIRegOperand = WebAssembly::SP32;
109 // Create i32.add SP, offset and make it the operand.
110 const TargetRegisterClass *PtrRC =
111 MRI.getTargetRegisterInfo()->getPointerRegClass(MF);
112 unsigned OffsetOp = MRI.createVirtualRegister(PtrRC);
113 BuildMI(MBB, *II, II->getDebugLoc(), TII->get(WebAssembly::CONST_I32),
115 .addImm(FrameOffset);
116 FIRegOperand = MRI.createVirtualRegister(PtrRC);
117 BuildMI(MBB, *II, II->getDebugLoc(), TII->get(WebAssembly::ADD_I32),
119 .addReg(WebAssembly::SP32)
122 MI.getOperand(FIOperandNum).ChangeToRegister(FIRegOperand, /*IsDef=*/false);
126 WebAssemblyRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
127 static const unsigned Regs[2][2] = {
128 /* !isArch64Bit isArch64Bit */
129 /* !hasFP */ {WebAssembly::SP32, WebAssembly::SP64},
130 /* hasFP */ {WebAssembly::FP32, WebAssembly::FP64}};
131 const WebAssemblyFrameLowering *TFI = getFrameLowering(MF);
132 return Regs[TFI->hasFP(MF)][TT.isArch64Bit()];
135 const TargetRegisterClass *
136 WebAssemblyRegisterInfo::getPointerRegClass(const MachineFunction &MF,
137 unsigned Kind) const {
138 assert(Kind == 0 && "Only one kind of pointer on WebAssembly");
139 if (MF.getSubtarget<WebAssemblySubtarget>().hasAddr64())
140 return &WebAssembly::I64RegClass;
141 return &WebAssembly::I32RegClass;