1 //WebAssemblyRegisterInfo.td-Describe the WebAssembly Registers -*- tablegen -*-
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file describes the WebAssembly register classes and some nominal
12 /// physical registers.
14 //===----------------------------------------------------------------------===//
16 class WebAssemblyReg<string n> : Register<n> {
17 let Namespace = "WebAssembly";
20 class WebAssemblyRegClass<list<ValueType> regTypes, int alignment, dag regList>
21 : RegisterClass<"WebAssembly", regTypes, alignment, regList>;
23 //===----------------------------------------------------------------------===//
25 //===----------------------------------------------------------------------===//
27 // Special registers used as the frame and stack pointer.
29 // WebAssembly may someday supports mixed 32-bit and 64-bit heaps in the same
30 // application, which requires separate width FP and SP.
31 def FP32 : WebAssemblyReg<"%FP32">;
32 def FP64 : WebAssemblyReg<"%FP64">;
33 def SP32 : WebAssemblyReg<"%SP32">;
34 def SP64 : WebAssemblyReg<"%SP64">;
36 // The register allocation framework requires register classes have at least
37 // one register, so we define a few for the floating point register classes
38 // since we otherwise don't need a physical register in those classes.
39 def F32_0 : WebAssemblyReg<"%f32.0">;
40 def F64_0 : WebAssemblyReg<"%f64.0">;
42 def V128_0: WebAssemblyReg<"%v128">;
44 // The value stack "register". This is an opaque entity which serves to order
45 // uses and defs that must remain in LIFO order.
46 def VALUE_STACK : WebAssemblyReg<"STACK">;
48 // The incoming arguments "register". This is an opaque entity which serves to
49 // order the ARGUMENT instructions that are emulating live-in registers and
50 // must not be scheduled below other instructions.
51 def ARGUMENTS : WebAssemblyReg<"ARGUMENTS">;
53 //===----------------------------------------------------------------------===//
55 //===----------------------------------------------------------------------===//
57 def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32)>;
58 def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64)>;
59 def F32 : WebAssemblyRegClass<[f32], 32, (add F32_0)>;
60 def F64 : WebAssemblyRegClass<[f64], 64, (add F64_0)>;
61 def V128 : WebAssemblyRegClass<[v4f32, v4i32, v16i8, v8i16], 128, (add V128_0)>;