1 //===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file defines the WebAssembly-specific subclass of TargetMachine.
13 //===----------------------------------------------------------------------===//
15 #include "WebAssemblyTargetMachine.h"
16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17 #include "WebAssembly.h"
18 #include "WebAssemblyTargetObjectFile.h"
19 #include "WebAssemblyTargetTransformInfo.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/RegAllocRegistry.h"
23 #include "llvm/CodeGen/TargetPassConfig.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Transforms/Scalar.h"
30 #define DEBUG_TYPE "wasm"
32 // Emscripten's asm.js-style exception handling
33 static cl::opt<bool> EnableEmException(
34 "enable-emscripten-cxx-exceptions",
35 cl::desc("WebAssembly Emscripten-style exception handling"),
38 // Emscripten's asm.js-style setjmp/longjmp handling
39 static cl::opt<bool> EnableEmSjLj(
40 "enable-emscripten-sjlj",
41 cl::desc("WebAssembly Emscripten-style setjmp/longjmp handling"),
44 extern "C" void LLVMInitializeWebAssemblyTarget() {
45 // Register the target.
46 RegisterTargetMachine<WebAssemblyTargetMachine> X(
47 getTheWebAssemblyTarget32());
48 RegisterTargetMachine<WebAssemblyTargetMachine> Y(
49 getTheWebAssemblyTarget64());
51 // Register exception handling pass to opt
52 initializeWebAssemblyLowerEmscriptenEHSjLjPass(
53 *PassRegistry::getPassRegistry());
56 //===----------------------------------------------------------------------===//
57 // WebAssembly Lowering public interface.
58 //===----------------------------------------------------------------------===//
60 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
66 /// Create an WebAssembly architecture model.
68 WebAssemblyTargetMachine::WebAssemblyTargetMachine(
69 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
70 const TargetOptions &Options, Optional<Reloc::Model> RM,
71 Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
72 : LLVMTargetMachine(T,
73 TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128"
74 : "e-m:e-p:32:32-i64:64-n32:64-S128",
75 TT, CPU, FS, Options, getEffectiveRelocModel(RM),
76 CM ? *CM : CodeModel::Large, OL),
77 TLOF(TT.isOSBinFormatELF() ?
78 static_cast<TargetLoweringObjectFile*>(
79 new WebAssemblyTargetObjectFileELF()) :
80 static_cast<TargetLoweringObjectFile*>(
81 new WebAssemblyTargetObjectFile())) {
82 // WebAssembly type-checks instructions, but a noreturn function with a return
83 // type that doesn't match the context will cause a check failure. So we lower
84 // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's
85 // 'unreachable' instructions which is meant for that case.
86 this->Options.TrapUnreachable = true;
88 // WebAssembly treats each function as an independent unit. Force
89 // -ffunction-sections, effectively, so that we can emit them independently.
90 if (!TT.isOSBinFormatELF()) {
91 this->Options.FunctionSections = true;
92 this->Options.DataSections = true;
93 this->Options.UniqueSectionNames = true;
98 // Note that we don't use setRequiresStructuredCFG(true). It disables
99 // optimizations than we're ok with, and want, such as critical edge
100 // splitting and tail merging.
103 WebAssemblyTargetMachine::~WebAssemblyTargetMachine() {}
105 const WebAssemblySubtarget *
106 WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const {
107 Attribute CPUAttr = F.getFnAttribute("target-cpu");
108 Attribute FSAttr = F.getFnAttribute("target-features");
110 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
111 ? CPUAttr.getValueAsString().str()
113 std::string FS = !FSAttr.hasAttribute(Attribute::None)
114 ? FSAttr.getValueAsString().str()
117 auto &I = SubtargetMap[CPU + FS];
119 // This needs to be done before we create a new subtarget since any
120 // creation will depend on the TM and the code generation flags on the
121 // function that reside in TargetOptions.
122 resetTargetOptions(F);
123 I = llvm::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this);
129 /// WebAssembly Code Generator Pass Configuration Options.
130 class WebAssemblyPassConfig final : public TargetPassConfig {
132 WebAssemblyPassConfig(WebAssemblyTargetMachine &TM, PassManagerBase &PM)
133 : TargetPassConfig(TM, PM) {}
135 WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const {
136 return getTM<WebAssemblyTargetMachine>();
139 FunctionPass *createTargetRegisterAllocator(bool) override;
141 void addIRPasses() override;
142 bool addInstSelector() override;
143 void addPostRegAlloc() override;
144 bool addGCPasses() override { return false; }
145 void addPreEmitPass() override;
147 } // end anonymous namespace
150 WebAssemblyTargetMachine::getTargetTransformInfo(const Function &F) {
151 return TargetTransformInfo(WebAssemblyTTIImpl(this, F));
155 WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) {
156 return new WebAssemblyPassConfig(*this, PM);
159 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) {
160 return nullptr; // No reg alloc
163 //===----------------------------------------------------------------------===//
164 // The following functions are called from lib/CodeGen/Passes.cpp to modify
165 // the CodeGen pass sequence.
166 //===----------------------------------------------------------------------===//
168 void WebAssemblyPassConfig::addIRPasses() {
169 if (TM->Options.ThreadModel == ThreadModel::Single)
170 // In "single" mode, atomics get lowered to non-atomics.
171 addPass(createLowerAtomicPass());
173 // Expand some atomic operations. WebAssemblyTargetLowering has hooks which
174 // control specifically what gets lowered.
175 addPass(createAtomicExpandPass());
177 // Lower .llvm.global_dtors into .llvm_global_ctors with __cxa_atexit calls.
178 addPass(createWebAssemblyLowerGlobalDtors());
180 // Fix function bitcasts, as WebAssembly requires caller and callee signatures
182 addPass(createWebAssemblyFixFunctionBitcasts());
184 // Optimize "returned" function attributes.
185 if (getOptLevel() != CodeGenOpt::None)
186 addPass(createWebAssemblyOptimizeReturned());
188 // If exception handling is not enabled and setjmp/longjmp handling is
189 // enabled, we lower invokes into calls and delete unreachable landingpad
190 // blocks. Lowering invokes when there is no EH support is done in
191 // TargetPassConfig::addPassesToHandleExceptions, but this runs after this
192 // function and SjLj handling expects all invokes to be lowered before.
193 if (!EnableEmException) {
194 addPass(createLowerInvokePass());
195 // The lower invoke pass may create unreachable code. Remove it in order not
196 // to process dead blocks in setjmp/longjmp handling.
197 addPass(createUnreachableBlockEliminationPass());
200 // Handle exceptions and setjmp/longjmp if enabled.
201 if (EnableEmException || EnableEmSjLj)
202 addPass(createWebAssemblyLowerEmscriptenEHSjLj(EnableEmException,
205 TargetPassConfig::addIRPasses();
208 bool WebAssemblyPassConfig::addInstSelector() {
209 (void)TargetPassConfig::addInstSelector();
211 createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel()));
212 // Run the argument-move pass immediately after the ScheduleDAG scheduler
213 // so that we can fix up the ARGUMENT instructions before anything else
214 // sees them in the wrong place.
215 addPass(createWebAssemblyArgumentMove());
216 // Set the p2align operands. This information is present during ISel, however
217 // it's inconvenient to collect. Collect it now, and update the immediate
219 addPass(createWebAssemblySetP2AlignOperands());
223 void WebAssemblyPassConfig::addPostRegAlloc() {
224 // TODO: The following CodeGen passes don't currently support code containing
225 // virtual registers. Consider removing their restrictions and re-enabling
228 // Has no asserts of its own, but was not written to handle virtual regs.
229 disablePass(&ShrinkWrapID);
231 // These functions all require the NoVRegs property.
232 disablePass(&MachineCopyPropagationID);
233 disablePass(&PostRASchedulerID);
234 disablePass(&FuncletLayoutID);
235 disablePass(&StackMapLivenessID);
236 disablePass(&LiveDebugValuesID);
237 disablePass(&PatchableFunctionID);
239 TargetPassConfig::addPostRegAlloc();
242 void WebAssemblyPassConfig::addPreEmitPass() {
243 TargetPassConfig::addPreEmitPass();
245 // Now that we have a prologue and epilogue and all frame indices are
246 // rewritten, eliminate SP and FP. This allows them to be stackified,
247 // colored, and numbered with the rest of the registers.
248 addPass(createWebAssemblyReplacePhysRegs());
250 // Rewrite pseudo call_indirect instructions as real instructions.
251 // This needs to run before register stackification, because we change the
252 // order of the arguments.
253 addPass(createWebAssemblyCallIndirectFixup());
255 if (getOptLevel() != CodeGenOpt::None) {
256 // LiveIntervals isn't commonly run this late. Re-establish preconditions.
257 addPass(createWebAssemblyPrepareForLiveIntervals());
259 // Depend on LiveIntervals and perform some optimizations on it.
260 addPass(createWebAssemblyOptimizeLiveIntervals());
262 // Prepare store instructions for register stackifying.
263 addPass(createWebAssemblyStoreResults());
265 // Mark registers as representing wasm's value stack. This is a key
266 // code-compression technique in WebAssembly. We run this pass (and
267 // StoreResults above) very late, so that it sees as much code as possible,
268 // including code emitted by PEI and expanded by late tail duplication.
269 addPass(createWebAssemblyRegStackify());
271 // Run the register coloring pass to reduce the total number of registers.
272 // This runs after stackification so that it doesn't consider registers
273 // that become stackified.
274 addPass(createWebAssemblyRegColoring());
277 // Eliminate multiple-entry loops. Do this before inserting explicit get_local
278 // and set_local operators because we create a new variable that we want
279 // converted into a local.
280 addPass(createWebAssemblyFixIrreducibleControlFlow());
282 // Insert explicit get_local and set_local operators.
283 addPass(createWebAssemblyExplicitLocals());
285 // Sort the blocks of the CFG into topological order, a prerequisite for
286 // BLOCK and LOOP markers.
287 addPass(createWebAssemblyCFGSort());
289 // Insert BLOCK and LOOP markers.
290 addPass(createWebAssemblyCFGStackify());
292 // Lower br_unless into br_if.
293 addPass(createWebAssemblyLowerBrUnless());
295 // Perform the very last peephole optimizations on the code.
296 if (getOptLevel() != CodeGenOpt::None)
297 addPass(createWebAssemblyPeephole());
299 // Create a mapping from LLVM CodeGen virtual registers to wasm registers.
300 addPass(createWebAssemblyRegNumbering());