1 //===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file defines the WebAssembly-specific subclass of TargetMachine.
13 //===----------------------------------------------------------------------===//
15 #include "WebAssembly.h"
16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17 #include "WebAssemblyTargetMachine.h"
18 #include "WebAssemblyTargetObjectFile.h"
19 #include "WebAssemblyTargetTransformInfo.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/RegAllocRegistry.h"
23 #include "llvm/CodeGen/TargetPassConfig.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Transforms/Scalar.h"
30 #define DEBUG_TYPE "wasm"
32 // Emscripten's asm.js-style exception handling
33 static cl::opt<bool> EnableEmException(
34 "enable-emscripten-cxx-exceptions",
35 cl::desc("WebAssembly Emscripten-style exception handling"),
38 // Emscripten's asm.js-style setjmp/longjmp handling
39 static cl::opt<bool> EnableEmSjLj(
40 "enable-emscripten-sjlj",
41 cl::desc("WebAssembly Emscripten-style setjmp/longjmp handling"),
44 extern "C" void LLVMInitializeWebAssemblyTarget() {
45 // Register the target.
46 RegisterTargetMachine<WebAssemblyTargetMachine> X(
47 getTheWebAssemblyTarget32());
48 RegisterTargetMachine<WebAssemblyTargetMachine> Y(
49 getTheWebAssemblyTarget64());
51 // Register exception handling pass to opt
52 initializeWebAssemblyLowerEmscriptenEHSjLjPass(
53 *PassRegistry::getPassRegistry());
56 //===----------------------------------------------------------------------===//
57 // WebAssembly Lowering public interface.
58 //===----------------------------------------------------------------------===//
60 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
66 /// Create an WebAssembly architecture model.
68 WebAssemblyTargetMachine::WebAssemblyTargetMachine(
69 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
70 const TargetOptions &Options, Optional<Reloc::Model> RM,
71 CodeModel::Model CM, CodeGenOpt::Level OL)
72 : LLVMTargetMachine(T,
73 TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128"
74 : "e-m:e-p:32:32-i64:64-n32:64-S128",
75 TT, CPU, FS, Options, getEffectiveRelocModel(RM),
77 TLOF(make_unique<WebAssemblyTargetObjectFile>()) {
78 // WebAssembly type-checks instructions, but a noreturn function with a return
79 // type that doesn't match the context will cause a check failure. So we lower
80 // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's
81 // 'unreachable' instructions which is meant for that case.
82 this->Options.TrapUnreachable = true;
86 // Note that we don't use setRequiresStructuredCFG(true). It disables
87 // optimizations than we're ok with, and want, such as critical edge
88 // splitting and tail merging.
91 WebAssemblyTargetMachine::~WebAssemblyTargetMachine() {}
93 const WebAssemblySubtarget *
94 WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const {
95 Attribute CPUAttr = F.getFnAttribute("target-cpu");
96 Attribute FSAttr = F.getFnAttribute("target-features");
98 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
99 ? CPUAttr.getValueAsString().str()
101 std::string FS = !FSAttr.hasAttribute(Attribute::None)
102 ? FSAttr.getValueAsString().str()
105 auto &I = SubtargetMap[CPU + FS];
107 // This needs to be done before we create a new subtarget since any
108 // creation will depend on the TM and the code generation flags on the
109 // function that reside in TargetOptions.
110 resetTargetOptions(F);
111 I = llvm::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this);
117 /// WebAssembly Code Generator Pass Configuration Options.
118 class WebAssemblyPassConfig final : public TargetPassConfig {
120 WebAssemblyPassConfig(WebAssemblyTargetMachine *TM, PassManagerBase &PM)
121 : TargetPassConfig(TM, PM) {}
123 WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const {
124 return getTM<WebAssemblyTargetMachine>();
127 FunctionPass *createTargetRegisterAllocator(bool) override;
129 void addIRPasses() override;
130 bool addInstSelector() override;
131 void addPostRegAlloc() override;
132 bool addGCPasses() override { return false; }
133 void addPreEmitPass() override;
135 } // end anonymous namespace
137 TargetIRAnalysis WebAssemblyTargetMachine::getTargetIRAnalysis() {
138 return TargetIRAnalysis([this](const Function &F) {
139 return TargetTransformInfo(WebAssemblyTTIImpl(this, F));
144 WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) {
145 return new WebAssemblyPassConfig(this, PM);
148 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) {
149 return nullptr; // No reg alloc
152 //===----------------------------------------------------------------------===//
153 // The following functions are called from lib/CodeGen/Passes.cpp to modify
154 // the CodeGen pass sequence.
155 //===----------------------------------------------------------------------===//
157 void WebAssemblyPassConfig::addIRPasses() {
158 if (TM->Options.ThreadModel == ThreadModel::Single)
159 // In "single" mode, atomics get lowered to non-atomics.
160 addPass(createLowerAtomicPass());
162 // Expand some atomic operations. WebAssemblyTargetLowering has hooks which
163 // control specifically what gets lowered.
164 addPass(createAtomicExpandPass(TM));
166 // Optimize "returned" function attributes.
167 if (getOptLevel() != CodeGenOpt::None)
168 addPass(createWebAssemblyOptimizeReturned());
170 // If exception handling is not enabled and setjmp/longjmp handling is
171 // enabled, we lower invokes into calls and delete unreachable landingpad
172 // blocks. Lowering invokes when there is no EH support is done in
173 // TargetPassConfig::addPassesToHandleExceptions, but this runs after this
174 // function and SjLj handling expects all invokes to be lowered before.
175 if (!EnableEmException) {
176 addPass(createLowerInvokePass());
177 // The lower invoke pass may create unreachable code. Remove it in order not
178 // to process dead blocks in setjmp/longjmp handling.
179 addPass(createUnreachableBlockEliminationPass());
182 // Handle exceptions and setjmp/longjmp if enabled.
183 if (EnableEmException || EnableEmSjLj)
184 addPass(createWebAssemblyLowerEmscriptenEHSjLj(EnableEmException,
187 TargetPassConfig::addIRPasses();
190 bool WebAssemblyPassConfig::addInstSelector() {
191 (void)TargetPassConfig::addInstSelector();
193 createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel()));
194 // Run the argument-move pass immediately after the ScheduleDAG scheduler
195 // so that we can fix up the ARGUMENT instructions before anything else
196 // sees them in the wrong place.
197 addPass(createWebAssemblyArgumentMove());
198 // Set the p2align operands. This information is present during ISel, however
199 // it's inconvenient to collect. Collect it now, and update the immediate
201 addPass(createWebAssemblySetP2AlignOperands());
205 void WebAssemblyPassConfig::addPostRegAlloc() {
206 // TODO: The following CodeGen passes don't currently support code containing
207 // virtual registers. Consider removing their restrictions and re-enabling
210 // Has no asserts of its own, but was not written to handle virtual regs.
211 disablePass(&ShrinkWrapID);
213 // These functions all require the NoVRegs property.
214 disablePass(&MachineCopyPropagationID);
215 disablePass(&PostRASchedulerID);
216 disablePass(&FuncletLayoutID);
217 disablePass(&StackMapLivenessID);
218 disablePass(&LiveDebugValuesID);
219 disablePass(&PatchableFunctionID);
221 TargetPassConfig::addPostRegAlloc();
224 void WebAssemblyPassConfig::addPreEmitPass() {
225 TargetPassConfig::addPreEmitPass();
227 // Now that we have a prologue and epilogue and all frame indices are
228 // rewritten, eliminate SP and FP. This allows them to be stackified,
229 // colored, and numbered with the rest of the registers.
230 addPass(createWebAssemblyReplacePhysRegs());
232 // Rewrite pseudo call_indirect instructions as real instructions.
233 // This needs to run before register stackification, because we change the
234 // order of the arguments.
235 addPass(createWebAssemblyCallIndirectFixup());
237 if (getOptLevel() != CodeGenOpt::None) {
238 // LiveIntervals isn't commonly run this late. Re-establish preconditions.
239 addPass(createWebAssemblyPrepareForLiveIntervals());
241 // Depend on LiveIntervals and perform some optimizations on it.
242 addPass(createWebAssemblyOptimizeLiveIntervals());
244 // Prepare store instructions for register stackifying.
245 addPass(createWebAssemblyStoreResults());
247 // Mark registers as representing wasm's value stack. This is a key
248 // code-compression technique in WebAssembly. We run this pass (and
249 // StoreResults above) very late, so that it sees as much code as possible,
250 // including code emitted by PEI and expanded by late tail duplication.
251 addPass(createWebAssemblyRegStackify());
253 // Run the register coloring pass to reduce the total number of registers.
254 // This runs after stackification so that it doesn't consider registers
255 // that become stackified.
256 addPass(createWebAssemblyRegColoring());
259 // Insert explicit get_local and set_local operators.
260 addPass(createWebAssemblyExplicitLocals());
262 // Eliminate multiple-entry loops.
263 addPass(createWebAssemblyFixIrreducibleControlFlow());
265 // Put the CFG in structured form; insert BLOCK and LOOP markers.
266 addPass(createWebAssemblyCFGStackify());
268 // Lower br_unless into br_if.
269 addPass(createWebAssemblyLowerBrUnless());
271 // Perform the very last peephole optimizations on the code.
272 if (getOptLevel() != CodeGenOpt::None)
273 addPass(createWebAssemblyPeephole());
275 // Create a mapping from LLVM CodeGen virtual registers to wasm registers.
276 addPass(createWebAssemblyRegNumbering());