1 //===-- X86DisassemblerDecoderInternal.h - Disassembler decoder -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler.
11 // It contains the public interface of the instruction decoder.
12 // Documentation for the disassembler can be found in X86Disassembler.h.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H
17 #define LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/Support/X86DisassemblerDecoderCommon.h"
23 namespace X86Disassembler {
25 // Accessor functions for various fields of an Intel instruction
26 #define modFromModRM(modRM) (((modRM) & 0xc0) >> 6)
27 #define regFromModRM(modRM) (((modRM) & 0x38) >> 3)
28 #define rmFromModRM(modRM) ((modRM) & 0x7)
29 #define scaleFromSIB(sib) (((sib) & 0xc0) >> 6)
30 #define indexFromSIB(sib) (((sib) & 0x38) >> 3)
31 #define baseFromSIB(sib) ((sib) & 0x7)
32 #define wFromREX(rex) (((rex) & 0x8) >> 3)
33 #define rFromREX(rex) (((rex) & 0x4) >> 2)
34 #define xFromREX(rex) (((rex) & 0x2) >> 1)
35 #define bFromREX(rex) ((rex) & 0x1)
37 #define rFromEVEX2of4(evex) (((~(evex)) & 0x80) >> 7)
38 #define xFromEVEX2of4(evex) (((~(evex)) & 0x40) >> 6)
39 #define bFromEVEX2of4(evex) (((~(evex)) & 0x20) >> 5)
40 #define r2FromEVEX2of4(evex) (((~(evex)) & 0x10) >> 4)
41 #define mmFromEVEX2of4(evex) ((evex) & 0x3)
42 #define wFromEVEX3of4(evex) (((evex) & 0x80) >> 7)
43 #define vvvvFromEVEX3of4(evex) (((~(evex)) & 0x78) >> 3)
44 #define ppFromEVEX3of4(evex) ((evex) & 0x3)
45 #define zFromEVEX4of4(evex) (((evex) & 0x80) >> 7)
46 #define l2FromEVEX4of4(evex) (((evex) & 0x40) >> 6)
47 #define lFromEVEX4of4(evex) (((evex) & 0x20) >> 5)
48 #define bFromEVEX4of4(evex) (((evex) & 0x10) >> 4)
49 #define v2FromEVEX4of4(evex) (((~evex) & 0x8) >> 3)
50 #define aaaFromEVEX4of4(evex) ((evex) & 0x7)
52 #define rFromVEX2of3(vex) (((~(vex)) & 0x80) >> 7)
53 #define xFromVEX2of3(vex) (((~(vex)) & 0x40) >> 6)
54 #define bFromVEX2of3(vex) (((~(vex)) & 0x20) >> 5)
55 #define mmmmmFromVEX2of3(vex) ((vex) & 0x1f)
56 #define wFromVEX3of3(vex) (((vex) & 0x80) >> 7)
57 #define vvvvFromVEX3of3(vex) (((~(vex)) & 0x78) >> 3)
58 #define lFromVEX3of3(vex) (((vex) & 0x4) >> 2)
59 #define ppFromVEX3of3(vex) ((vex) & 0x3)
61 #define rFromVEX2of2(vex) (((~(vex)) & 0x80) >> 7)
62 #define vvvvFromVEX2of2(vex) (((~(vex)) & 0x78) >> 3)
63 #define lFromVEX2of2(vex) (((vex) & 0x4) >> 2)
64 #define ppFromVEX2of2(vex) ((vex) & 0x3)
66 #define rFromXOP2of3(xop) (((~(xop)) & 0x80) >> 7)
67 #define xFromXOP2of3(xop) (((~(xop)) & 0x40) >> 6)
68 #define bFromXOP2of3(xop) (((~(xop)) & 0x20) >> 5)
69 #define mmmmmFromXOP2of3(xop) ((xop) & 0x1f)
70 #define wFromXOP3of3(xop) (((xop) & 0x80) >> 7)
71 #define vvvvFromXOP3of3(vex) (((~(vex)) & 0x78) >> 3)
72 #define lFromXOP3of3(xop) (((xop) & 0x4) >> 2)
73 #define ppFromXOP3of3(xop) ((xop) & 0x3)
75 // These enums represent Intel registers for use by the decoder.
98 #define EA_BASES_16BIT \
134 #define EA_BASES_32BIT \
170 #define EA_BASES_64BIT \
328 #define REGS_SEGMENT \
354 #define REGS_CONTROL \
378 #define ALL_EA_BASES \
383 #define ALL_SIB_BASES \
403 /// All possible values of the base field for effective-address
404 /// computations, a.k.a. the Mod and R/M fields of the ModR/M byte.
405 /// We distinguish between bases (EA_BASE_*) and registers that just happen
406 /// to be referred to when Mod == 0b11 (EA_REG_*).
409 #define ENTRY(x) EA_BASE_##x,
412 #define ENTRY(x) EA_REG_##x,
418 /// All possible values of the SIB index field.
419 /// borrows entries from ALL_EA_BASES with the special case that
420 /// sib is synonymous with NONE.
421 /// Vector SIB: index can be XMM or YMM.
424 #define ENTRY(x) SIB_INDEX_##x,
433 /// All possible values of the SIB base field.
436 #define ENTRY(x) SIB_BASE_##x,
442 /// Possible displacement types for effective-address computations.
450 /// All possible values of the reg field in the ModR/M byte.
452 #define ENTRY(x) MODRM_REG_##x,
458 /// All possible segment overrides.
459 enum SegmentOverride {
470 /// Possible values for the VEX.m-mmmm field
471 enum VEXLeadingOpcodeByte {
478 XOP_MAP_SELECT_8 = 0x8,
479 XOP_MAP_SELECT_9 = 0x9,
480 XOP_MAP_SELECT_A = 0xA
483 /// Possible values for the VEX.pp/EVEX.pp field
485 VEX_PREFIX_NONE = 0x0,
491 enum VectorExtensionType {
492 TYPE_NO_VEX_XOP = 0x0,
499 /// Type for the byte reader that the consumer must provide to
500 /// the decoder. Reads a single byte from the instruction's address space.
501 /// \param arg A baton that the consumer can associate with any internal
502 /// state that it needs.
503 /// \param byte A pointer to a single byte in memory that should be set to
504 /// contain the value at address.
505 /// \param address The address in the instruction's address space that should
507 /// \return -1 if the byte cannot be read for any reason; 0 otherwise.
508 typedef int (*byteReader_t)(const void *arg, uint8_t *byte, uint64_t address);
510 /// Type for the logging function that the consumer can provide to
511 /// get debugging output from the decoder.
512 /// \param arg A baton that the consumer can associate with any internal
513 /// state that it needs.
514 /// \param log A string that contains the message. Will be reused after
515 /// the logger returns.
516 typedef void (*dlog_t)(void *arg, const char *log);
518 /// The specification for how to extract and interpret a full instruction and
520 struct InstructionSpecifier {
524 /// The x86 internal instruction, which is produced by the decoder.
525 struct InternalInstruction {
526 // Reader interface (C)
528 // Opaque value passed to the reader
529 const void* readerArg;
530 // The address of the next byte to read via the reader
531 uint64_t readerCursor;
533 // Logger interface (C)
535 // Opaque value passed to the logger
538 // General instruction information
540 // The mode to disassemble for (64-bit, protected, real)
541 DisassemblerMode mode;
542 // The start of the instruction, usable with the reader
543 uint64_t startLocation;
544 // The length of the instruction, in bytes
549 // The possible mandatory prefix
550 uint8_t mandatoryPrefix;
551 // The value of the vector extension prefix(EVEX/VEX/XOP), if present
552 uint8_t vectorExtensionPrefix[4];
553 // The type of the vector extension prefix
554 VectorExtensionType vectorExtensionType;
555 // The value of the REX prefix, if present
557 // The segment override type
558 SegmentOverride segmentOverride;
559 // 1 if the prefix byte, 0xf2 or 0xf3 is xacquire or xrelease
560 bool xAcquireRelease;
562 // Address-size override
564 // Operand-size override
568 // The repeat prefix if any
569 uint8_t repeatPrefix;
571 // Sizes of various critical pieces of data, in bytes
572 uint8_t registerSize;
574 uint8_t displacementSize;
575 uint8_t immediateSize;
577 // Offsets from the start of the instruction to the pieces of data, which is
578 // needed to find relocation entries for adding symbolic operands.
579 uint8_t displacementOffset;
580 uint8_t immediateOffset;
584 // The last byte of the opcode, not counting any ModR/M extension
589 // The type of opcode, used for indexing into the array of decode tables
590 OpcodeType opcodeType;
591 // The instruction ID, extracted from the decode table
592 uint16_t instructionID;
593 // The specifier for the instruction, from the instruction info table
594 const InstructionSpecifier *spec;
596 // state for additional bytes, consumed during operand decode. Pattern:
597 // consumed___ indicates that the byte was already consumed and does not
598 // need to be consumed again.
600 // The VEX.vvvv field, which contains a third register operand for some AVX
604 // The writemask for AVX-512 instructions which is contained in EVEX.aaa
607 // The ModR/M byte, which contains most register operands and some portion of
608 // all memory operands.
612 // The SIB byte, used for more complex 32- or 64-bit memory operands
616 // The displacement, used for memory operands
617 bool consumedDisplacement;
618 int32_t displacement;
620 // Immediates. There can be two in some cases
621 uint8_t numImmediatesConsumed;
622 uint8_t numImmediatesTranslated;
623 uint64_t immediates[2];
625 // A register or immediate operand encoded into the opcode
628 // Portions of the ModR/M byte
630 // These fields determine the allowable values for the ModR/M fields, which
631 // depend on operand and address widths.
635 // The Mod and R/M fields can encode a base for an effective address, or a
636 // register. These are separated into two fields here.
638 EADisplacement eaDisplacement;
639 // The reg field always encodes a register
643 SIBIndex sibIndexBase;
648 // Embedded rounding control.
651 ArrayRef<OperandSpecifier> operands;
654 /// Decode one instruction and store the decoding results in
655 /// a buffer provided by the consumer.
656 /// \param insn The buffer to store the instruction in. Allocated by the
658 /// \param reader The byteReader_t for the bytes to be read.
659 /// \param readerArg An argument to pass to the reader for storing context
660 /// specific to the consumer. May be NULL.
661 /// \param logger The dlog_t to be used in printing status messages from the
662 /// disassembler. May be NULL.
663 /// \param loggerArg An argument to pass to the logger for storing context
664 /// specific to the logger. May be NULL.
665 /// \param startLoc The address (in the reader's address space) of the first
666 /// byte in the instruction.
667 /// \param mode The mode (16-bit, 32-bit, 64-bit) to decode in.
668 /// \return Nonzero if there was an error during decode, 0 otherwise.
669 int decodeInstruction(InternalInstruction *insn,
671 const void *readerArg,
676 DisassemblerMode mode);
678 /// Print a message to debugs()
679 /// \param file The name of the file printing the debug message.
680 /// \param line The line number that printed the debug message.
681 /// \param s The message to print.
682 void Debug(const char *file, unsigned line, const char *s);
684 StringRef GetInstrName(unsigned Opcode, const void *mii);
686 } // namespace X86Disassembler