1 //===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file includes code for rendering MCInst instances as Intel-style
13 //===----------------------------------------------------------------------===//
15 #include "X86IntelInstPrinter.h"
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "X86InstComments.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/Support/Casting.h"
24 #include "llvm/Support/ErrorHandling.h"
30 #define DEBUG_TYPE "asm-printer"
32 #include "X86GenAsmWriter1.inc"
34 void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
35 OS << getRegisterName(RegNo);
38 void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
40 const MCSubtargetInfo &STI) {
41 printInstFlags(MI, OS);
43 // In 16-bit mode, print data16 as data32.
44 if (MI->getOpcode() == X86::DATA16_PREFIX &&
45 STI.getFeatureBits()[X86::Mode16Bit]) {
48 printInstruction(MI, OS);
50 // Next always print the annotation.
51 printAnnotation(OS, Annot);
53 // If verbose assembly is enabled, we can print some informative comments.
55 EmitAnyX86InstComments(MI, *CommentStream, MII);
58 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
60 const MCOperand &Op = MI->getOperand(OpNo);
62 printRegName(O, Op.getReg());
63 } else if (Op.isImm()) {
64 O << formatImm((int64_t)Op.getImm());
66 assert(Op.isExpr() && "unknown operand kind in printOperand");
68 Op.getExpr()->print(O, &MAI);
72 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
74 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
75 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
76 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
77 const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
79 // If this has a segment register, print it.
80 printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O);
84 bool NeedPlus = false;
85 if (BaseReg.getReg()) {
86 printOperand(MI, Op+X86::AddrBaseReg, O);
90 if (IndexReg.getReg()) {
91 if (NeedPlus) O << " + ";
94 printOperand(MI, Op+X86::AddrIndexReg, O);
98 if (!DispSpec.isImm()) {
99 if (NeedPlus) O << " + ";
100 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
101 DispSpec.getExpr()->print(O, &MAI);
103 int64_t DispVal = DispSpec.getImm();
104 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
113 O << formatImm(DispVal);
120 void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
122 // If this has a segment register, print it.
123 printOptionalSegReg(MI, Op + 1, O);
125 printOperand(MI, Op, O);
129 void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
131 // DI accesses are always ES-based.
133 printOperand(MI, Op, O);
137 void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
139 const MCOperand &DispSpec = MI->getOperand(Op);
141 // If this has a segment register, print it.
142 printOptionalSegReg(MI, Op + 1, O);
146 if (DispSpec.isImm()) {
147 O << formatImm(DispSpec.getImm());
149 assert(DispSpec.isExpr() && "non-immediate displacement?");
150 DispSpec.getExpr()->print(O, &MAI);
156 void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
158 if (MI->getOperand(Op).isExpr())
159 return MI->getOperand(Op).getExpr()->print(O, &MAI);
161 O << formatImm(MI->getOperand(Op).getImm() & 0xff);
164 void X86IntelInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
166 const MCOperand &Op = MI->getOperand(OpNo);
167 unsigned Reg = Op.getReg();
168 // Override the default printing to print st(0) instead st.
172 printRegName(OS, Reg);