1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains small standalone helper functions and enum definitions for
11 // the X86 target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
18 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
20 #include "X86MCTargetDesc.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/Support/DataTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
28 // Enums for memory operand decoding. Each memory operand is represented with
29 // a 5 operand sequence in the form:
30 // [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
31 // These enums help decode this.
38 /// AddrSegmentReg - The operand # of the segment in the memory operand.
41 /// AddrNumOperands - Total number of operands in a memory reference.
45 /// AVX512 static rounding constants. These need to match the values in
47 enum STATIC_ROUNDING {
55 /// The constants to describe instr prefixes if there are
63 NO_SCHED_INFO = 32, // Don't add sched comment to the current instr because
64 // it was already added
67 } // end namespace X86;
69 /// X86II - This namespace holds all of the target specific flags that
70 /// instruction info tracks.
73 /// Target Operand Flag enum.
75 //===------------------------------------------------------------------===//
76 // X86 Specific MachineOperand flags.
80 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
82 /// SYMBOL_LABEL + [. - PICBASELABEL]
83 MO_GOT_ABSOLUTE_ADDRESS,
85 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
86 /// immediate should get the value of the symbol minus the PIC base label:
87 /// SYMBOL_LABEL - PICBASELABEL
90 /// MO_GOT - On a symbol operand this indicates that the immediate is the
91 /// offset to the GOT entry for the symbol name from the base of the GOT.
93 /// See the X86-64 ELF ABI supplement for more details.
97 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
98 /// the offset to the location of the symbol name from the base of the GOT.
100 /// See the X86-64 ELF ABI supplement for more details.
101 /// SYMBOL_LABEL @GOTOFF
104 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
105 /// offset to the GOT entry for the symbol name from the current code
108 /// See the X86-64 ELF ABI supplement for more details.
109 /// SYMBOL_LABEL @GOTPCREL
112 /// MO_PLT - On a symbol operand this indicates that the immediate is
113 /// offset to the PLT entry of symbol name from the current code location.
115 /// See the X86-64 ELF ABI supplement for more details.
116 /// SYMBOL_LABEL @PLT
119 /// MO_TLSGD - On a symbol operand this indicates that the immediate is
120 /// the offset of the GOT entry with the TLS index structure that contains
121 /// the module number and variable offset for the symbol. Used in the
122 /// general dynamic TLS access model.
124 /// See 'ELF Handling for Thread-Local Storage' for more details.
125 /// SYMBOL_LABEL @TLSGD
128 /// MO_TLSLD - On a symbol operand this indicates that the immediate is
129 /// the offset of the GOT entry with the TLS index for the module that
130 /// contains the symbol. When this index is passed to a call to
131 /// __tls_get_addr, the function will return the base address of the TLS
132 /// block for the symbol. Used in the x86-64 local dynamic TLS access model.
134 /// See 'ELF Handling for Thread-Local Storage' for more details.
135 /// SYMBOL_LABEL @TLSLD
138 /// MO_TLSLDM - On a symbol operand this indicates that the immediate is
139 /// the offset of the GOT entry with the TLS index for the module that
140 /// contains the symbol. When this index is passed to a call to
141 /// ___tls_get_addr, the function will return the base address of the TLS
142 /// block for the symbol. Used in the IA32 local dynamic TLS access model.
144 /// See 'ELF Handling for Thread-Local Storage' for more details.
145 /// SYMBOL_LABEL @TLSLDM
148 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
149 /// the offset of the GOT entry with the thread-pointer offset for the
150 /// symbol. Used in the x86-64 initial exec TLS access model.
152 /// See 'ELF Handling for Thread-Local Storage' for more details.
153 /// SYMBOL_LABEL @GOTTPOFF
156 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
157 /// the absolute address of the GOT entry with the negative thread-pointer
158 /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access
161 /// See 'ELF Handling for Thread-Local Storage' for more details.
162 /// SYMBOL_LABEL @INDNTPOFF
165 /// MO_TPOFF - On a symbol operand this indicates that the immediate is
166 /// the thread-pointer offset for the symbol. Used in the x86-64 local
167 /// exec TLS access model.
169 /// See 'ELF Handling for Thread-Local Storage' for more details.
170 /// SYMBOL_LABEL @TPOFF
173 /// MO_DTPOFF - On a symbol operand this indicates that the immediate is
174 /// the offset of the GOT entry with the TLS offset of the symbol. Used
175 /// in the local dynamic TLS access model.
177 /// See 'ELF Handling for Thread-Local Storage' for more details.
178 /// SYMBOL_LABEL @DTPOFF
181 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
182 /// the negative thread-pointer offset for the symbol. Used in the IA32
183 /// local exec TLS access model.
185 /// See 'ELF Handling for Thread-Local Storage' for more details.
186 /// SYMBOL_LABEL @NTPOFF
189 /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is
190 /// the offset of the GOT entry with the negative thread-pointer offset for
191 /// the symbol. Used in the PIC IA32 initial exec TLS access model.
193 /// See 'ELF Handling for Thread-Local Storage' for more details.
194 /// SYMBOL_LABEL @GOTNTPOFF
197 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
198 /// reference is actually to the "__imp_FOO" symbol. This is used for
199 /// dllimport linkage on windows.
202 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
203 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
204 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
207 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
208 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
209 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
210 MO_DARWIN_NONLAZY_PIC_BASE,
212 /// MO_TLVP - On a symbol operand this indicates that the immediate is
215 /// This is the TLS offset for the Darwin TLS mechanism.
218 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
219 /// is some TLS offset from the picbase.
221 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
224 /// MO_SECREL - On a symbol operand this indicates that the immediate is
225 /// the offset from beginning of section.
227 /// This is the TLS offset for the COFF/Windows TLS mechanism.
230 /// MO_ABS8 - On a symbol operand this indicates that the symbol is known
231 /// to be an absolute symbol in range [0,128), so we can use the @ABS8
235 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
236 /// reference is actually to the ".refptr.FOO" symbol. This is used for
237 /// stub symbols on windows.
242 //===------------------------------------------------------------------===//
243 // Instruction encodings. These are the standard/most common forms for X86
247 // PseudoFrm - This represents an instruction that is a pseudo instruction
248 // or one that has not been implemented yet. It is illegal to code generate
249 // it, but tolerated for intermediate implementation stages.
252 /// Raw - This form is for instructions that don't have any operands, so
253 /// they are just a fixed opcode value, like 'leave'.
256 /// AddRegFrm - This form is used for instructions like 'push r32' that have
257 /// their one register operand added to their opcode.
260 /// RawFrmMemOffs - This form is for instructions that store an absolute
261 /// memory offset as an immediate with a possible segment override.
264 /// RawFrmSrc - This form is for instructions that use the source index
265 /// register SI/ESI/RSI with a possible segment override.
268 /// RawFrmDst - This form is for instructions that use the destination index
269 /// register DI/EDI/RDI.
272 /// RawFrmDstSrc - This form is for instructions that use the source index
273 /// register SI/ESI/RSI with a possible segment override, and also the
274 /// destination index register DI/EDI/RDI.
277 /// RawFrmImm8 - This is used for the ENTER instruction, which has two
278 /// immediates, the first of which is a 16-bit immediate (specified by
279 /// the imm encoding) and the second is a 8-bit fixed value.
282 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
283 /// immediates, the first of which is a 16 or 32-bit immediate (specified by
284 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD
285 /// manual, this operand is described as pntr16:32 and pntr16:16
288 /// MRM[0-7][rm] - These forms are used to represent instructions that use
289 /// a Mod/RM byte, and use the middle field to hold extended opcode
290 /// information. In the intel manual these are represented as /0, /1, ...
293 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
294 /// to specify a destination, which in this case is memory.
298 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
299 /// to specify a source, which in this case is memory.
303 /// MRMSrcMem4VOp3 - This form is used for instructions that encode
304 /// operand 3 with VEX.VVVV and load from memory.
308 /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM
309 /// byte to specify the fourth source, which in this case is memory.
313 /// MRMXm - This form is used for instructions that use the Mod/RM byte
314 /// to specify a memory source, but doesn't use the middle field.
316 MRMXm = 39, // Instruction that uses Mod/RM but not the middle field.
318 // Next, instructions that operate on a memory r/m operand...
319 MRM0m = 40, MRM1m = 41, MRM2m = 42, MRM3m = 43, // Format /0 /1 /2 /3
320 MRM4m = 44, MRM5m = 45, MRM6m = 46, MRM7m = 47, // Format /4 /5 /6 /7
322 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
323 /// to specify a destination, which in this case is a register.
327 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
328 /// to specify a source, which in this case is a register.
332 /// MRMSrcReg4VOp3 - This form is used for instructions that encode
333 /// operand 3 with VEX.VVVV and do not load from memory.
337 /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM
338 /// byte to specify the fourth source, which in this case is a register.
342 /// MRMXr - This form is used for instructions that use the Mod/RM byte
343 /// to specify a register source, but doesn't use the middle field.
345 MRMXr = 55, // Instruction that uses Mod/RM but not the middle field.
347 // Instructions that operate on a register r/m operand...
348 MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59, // Format /0 /1 /2 /3
349 MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63, // Format /4 /5 /6 /7
351 /// MRM_XX - A mod/rm byte of exactly 0xXX.
352 MRM_C0 = 64, MRM_C1 = 65, MRM_C2 = 66, MRM_C3 = 67,
353 MRM_C4 = 68, MRM_C5 = 69, MRM_C6 = 70, MRM_C7 = 71,
354 MRM_C8 = 72, MRM_C9 = 73, MRM_CA = 74, MRM_CB = 75,
355 MRM_CC = 76, MRM_CD = 77, MRM_CE = 78, MRM_CF = 79,
356 MRM_D0 = 80, MRM_D1 = 81, MRM_D2 = 82, MRM_D3 = 83,
357 MRM_D4 = 84, MRM_D5 = 85, MRM_D6 = 86, MRM_D7 = 87,
358 MRM_D8 = 88, MRM_D9 = 89, MRM_DA = 90, MRM_DB = 91,
359 MRM_DC = 92, MRM_DD = 93, MRM_DE = 94, MRM_DF = 95,
360 MRM_E0 = 96, MRM_E1 = 97, MRM_E2 = 98, MRM_E3 = 99,
361 MRM_E4 = 100, MRM_E5 = 101, MRM_E6 = 102, MRM_E7 = 103,
362 MRM_E8 = 104, MRM_E9 = 105, MRM_EA = 106, MRM_EB = 107,
363 MRM_EC = 108, MRM_ED = 109, MRM_EE = 110, MRM_EF = 111,
364 MRM_F0 = 112, MRM_F1 = 113, MRM_F2 = 114, MRM_F3 = 115,
365 MRM_F4 = 116, MRM_F5 = 117, MRM_F6 = 118, MRM_F7 = 119,
366 MRM_F8 = 120, MRM_F9 = 121, MRM_FA = 122, MRM_FB = 123,
367 MRM_FC = 124, MRM_FD = 125, MRM_FE = 126, MRM_FF = 127,
371 //===------------------------------------------------------------------===//
374 // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
375 // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
376 // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
377 // prefix in 16-bit mode.
379 OpSizeMask = 0x3 << OpSizeShift,
381 OpSizeFixed = 0 << OpSizeShift,
382 OpSize16 = 1 << OpSizeShift,
383 OpSize32 = 2 << OpSizeShift,
385 // AsSize - AdSizeX implies this instruction determines its need of 0x67
386 // prefix from a normal ModRM memory operand. The other types indicate that
387 // an operand is encoded with a specific width and a prefix is needed if
388 // it differs from the current mode.
389 AdSizeShift = OpSizeShift + 2,
390 AdSizeMask = 0x3 << AdSizeShift,
392 AdSizeX = 0 << AdSizeShift,
393 AdSize16 = 1 << AdSizeShift,
394 AdSize32 = 2 << AdSizeShift,
395 AdSize64 = 3 << AdSizeShift,
397 //===------------------------------------------------------------------===//
398 // OpPrefix - There are several prefix bytes that are used as opcode
399 // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is
402 OpPrefixShift = AdSizeShift + 2,
403 OpPrefixMask = 0x3 << OpPrefixShift,
405 // PD - Prefix code for packed double precision vector floating point
406 // operations performed in the SSE registers.
407 PD = 1 << OpPrefixShift,
409 // XS, XD - These prefix codes are for single and double precision scalar
410 // floating point operations performed in the SSE registers.
411 XS = 2 << OpPrefixShift, XD = 3 << OpPrefixShift,
413 //===------------------------------------------------------------------===//
414 // OpMap - This field determines which opcode map this instruction
415 // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc.
417 OpMapShift = OpPrefixShift + 2,
418 OpMapMask = 0x7 << OpMapShift,
420 // OB - OneByte - Set if this instruction has a one byte opcode.
421 OB = 0 << OpMapShift,
423 // TB - TwoByte - Set if this instruction has a two byte opcode, which
424 // starts with a 0x0F byte before the real opcode.
425 TB = 1 << OpMapShift,
427 // T8, TA - Prefix after the 0x0F prefix.
428 T8 = 2 << OpMapShift, TA = 3 << OpMapShift,
430 // XOP8 - Prefix to include use of imm byte.
431 XOP8 = 4 << OpMapShift,
433 // XOP9 - Prefix to exclude use of imm byte.
434 XOP9 = 5 << OpMapShift,
436 // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
437 XOPA = 6 << OpMapShift,
439 /// ThreeDNow - This indicates that the instruction uses the
440 /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents
441 /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
442 /// storing a classifier in the imm8 field. To simplify our implementation,
443 /// we handle this by storeing the classifier in the opcode field and using
444 /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
445 ThreeDNow = 7 << OpMapShift,
447 //===------------------------------------------------------------------===//
448 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
449 // They are used to specify GPRs and SSE registers, 64-bit operand size,
450 // etc. We only cares about REX.W and REX.R bits and only the former is
451 // statically determined.
453 REXShift = OpMapShift + 3,
454 REX_W = 1 << REXShift,
456 //===------------------------------------------------------------------===//
457 // This three-bit field describes the size of an immediate operand. Zero is
458 // unused so that we can tell if we forgot to set a value.
459 ImmShift = REXShift + 1,
460 ImmMask = 15 << ImmShift,
461 Imm8 = 1 << ImmShift,
462 Imm8PCRel = 2 << ImmShift,
463 Imm8Reg = 3 << ImmShift,
464 Imm16 = 4 << ImmShift,
465 Imm16PCRel = 5 << ImmShift,
466 Imm32 = 6 << ImmShift,
467 Imm32PCRel = 7 << ImmShift,
468 Imm32S = 8 << ImmShift,
469 Imm64 = 9 << ImmShift,
471 //===------------------------------------------------------------------===//
472 // FP Instruction Classification... Zero is non-fp instruction.
474 // FPTypeMask - Mask for all of the FP types...
475 FPTypeShift = ImmShift + 4,
476 FPTypeMask = 7 << FPTypeShift,
478 // NotFP - The default, set for instructions that do not use FP registers.
479 NotFP = 0 << FPTypeShift,
481 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
482 ZeroArgFP = 1 << FPTypeShift,
484 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
485 OneArgFP = 2 << FPTypeShift,
487 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
488 // result back to ST(0). For example, fcos, fsqrt, etc.
490 OneArgFPRW = 3 << FPTypeShift,
492 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
493 // explicit argument, storing the result to either ST(0) or the implicit
494 // argument. For example: fadd, fsub, fmul, etc...
495 TwoArgFP = 4 << FPTypeShift,
497 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
498 // explicit argument, but have no destination. Example: fucom, fucomi, ...
499 CompareFP = 5 << FPTypeShift,
501 // CondMovFP - "2 operand" floating point conditional move instructions.
502 CondMovFP = 6 << FPTypeShift,
504 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
505 SpecialFP = 7 << FPTypeShift,
508 LOCKShift = FPTypeShift + 3,
509 LOCK = 1 << LOCKShift,
512 REPShift = LOCKShift + 1,
515 // Execution domain for SSE instructions.
516 // 0 means normal, non-SSE instruction.
517 SSEDomainShift = REPShift + 1,
520 EncodingShift = SSEDomainShift + 2,
521 EncodingMask = 0x3 << EncodingShift,
523 // VEX - encoding using 0xC4/0xC5
524 VEX = 1 << EncodingShift,
526 /// XOP - Opcode prefix used by XOP instructions.
527 XOP = 2 << EncodingShift,
529 // VEX_EVEX - Specifies that this instruction use EVEX form which provides
530 // syntax support up to 32 512-bit register operands and up to 7 16-bit
531 // mask operands as well as source operand data swizzling/memory operand
532 // conversion, eviction hint, and rounding mode.
533 EVEX = 3 << EncodingShift,
536 OpcodeShift = EncodingShift + 2,
538 /// VEX_W - Has a opcode specific functionality, but is used in the same
539 /// way as REX_W is for regular SSE instructions.
540 VEX_WShift = OpcodeShift + 8,
541 VEX_W = 1ULL << VEX_WShift,
543 /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
544 /// address instructions in SSE are represented as 3 address ones in AVX
545 /// and the additional register is encoded in VEX_VVVV prefix.
546 VEX_4VShift = VEX_WShift + 1,
547 VEX_4V = 1ULL << VEX_4VShift,
549 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
550 /// instruction uses 256-bit wide registers. This is usually auto detected
551 /// if a VR256 register is used, but some AVX instructions also have this
552 /// field marked when using a f256 memory references.
553 VEX_LShift = VEX_4VShift + 1,
554 VEX_L = 1ULL << VEX_LShift,
556 // EVEX_K - Set if this instruction requires masking
557 EVEX_KShift = VEX_LShift + 1,
558 EVEX_K = 1ULL << EVEX_KShift,
560 // EVEX_Z - Set if this instruction has EVEX.Z field set.
561 EVEX_ZShift = EVEX_KShift + 1,
562 EVEX_Z = 1ULL << EVEX_ZShift,
564 // EVEX_L2 - Set if this instruction has EVEX.L' field set.
565 EVEX_L2Shift = EVEX_ZShift + 1,
566 EVEX_L2 = 1ULL << EVEX_L2Shift,
568 // EVEX_B - Set if this instruction has EVEX.B field set.
569 EVEX_BShift = EVEX_L2Shift + 1,
570 EVEX_B = 1ULL << EVEX_BShift,
572 // The scaling factor for the AVX512's 8-bit compressed displacement.
573 CD8_Scale_Shift = EVEX_BShift + 1,
574 CD8_Scale_Mask = 127ULL << CD8_Scale_Shift,
576 /// Explicitly specified rounding control
577 EVEX_RCShift = CD8_Scale_Shift + 7,
578 EVEX_RC = 1ULL << EVEX_RCShift,
581 NoTrackShift = EVEX_RCShift + 1,
582 NOTRACK = 1ULL << NoTrackShift
585 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
586 // specified machine instruction.
588 inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) {
589 return TSFlags >> X86II::OpcodeShift;
592 inline bool hasImm(uint64_t TSFlags) {
593 return (TSFlags & X86II::ImmMask) != 0;
596 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
597 /// of the specified instruction.
598 inline unsigned getSizeOfImm(uint64_t TSFlags) {
599 switch (TSFlags & X86II::ImmMask) {
600 default: llvm_unreachable("Unknown immediate size");
602 case X86II::Imm8PCRel:
603 case X86II::Imm8Reg: return 1;
605 case X86II::Imm16PCRel: return 2;
608 case X86II::Imm32PCRel: return 4;
609 case X86II::Imm64: return 8;
613 /// isImmPCRel - Return true if the immediate of the specified instruction's
614 /// TSFlags indicates that it is pc relative.
615 inline unsigned isImmPCRel(uint64_t TSFlags) {
616 switch (TSFlags & X86II::ImmMask) {
617 default: llvm_unreachable("Unknown immediate size");
618 case X86II::Imm8PCRel:
619 case X86II::Imm16PCRel:
620 case X86II::Imm32PCRel:
632 /// isImmSigned - Return true if the immediate of the specified instruction's
633 /// TSFlags indicates that it is signed.
634 inline unsigned isImmSigned(uint64_t TSFlags) {
635 switch (TSFlags & X86II::ImmMask) {
636 default: llvm_unreachable("Unknown immediate signedness");
640 case X86II::Imm8PCRel:
643 case X86II::Imm16PCRel:
645 case X86II::Imm32PCRel:
651 /// getOperandBias - compute whether all of the def operands are repeated
652 /// in the uses and therefore should be skipped.
653 /// This determines the start of the unique operand list. We need to determine
654 /// if all of the defs have a corresponding tied operand in the uses.
655 /// Unfortunately, the tied operand information is encoded in the uses not
656 /// the defs so we have to use some heuristics to find which operands to
658 inline unsigned getOperandBias(const MCInstrDesc& Desc) {
659 unsigned NumDefs = Desc.getNumDefs();
660 unsigned NumOps = Desc.getNumOperands();
662 default: llvm_unreachable("Unexpected number of defs");
666 // Common two addr case.
667 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
669 // Check for AVX-512 scatter which has a TIED_TO in the second to last
672 Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0)
676 // XCHG/XADD have two destinations and two sources.
677 if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
678 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1)
680 // Check for gather. AVX-512 has the second tied operand early. AVX2
681 // has it as the last op.
682 if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
683 (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 ||
684 Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1) &&
685 "Instruction with 2 defs isn't gather?")
691 /// getMemoryOperandNo - The function returns the MCInst operand # for the
692 /// first field of the memory operand. If the instruction doesn't have a
693 /// memory operand, this returns -1.
695 /// Note that this ignores tied operands. If there is a tied register which
696 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
697 /// counted as one operand.
699 inline int getMemoryOperandNo(uint64_t TSFlags) {
700 bool HasVEX_4V = TSFlags & X86II::VEX_4V;
701 bool HasEVEX_K = TSFlags & X86II::EVEX_K;
703 switch (TSFlags & X86II::FormMask) {
704 default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!");
707 case X86II::AddRegFrm:
708 case X86II::RawFrmImm8:
709 case X86II::RawFrmImm16:
710 case X86II::RawFrmMemOffs:
711 case X86II::RawFrmSrc:
712 case X86II::RawFrmDst:
713 case X86II::RawFrmDstSrc:
715 case X86II::MRMDestMem:
717 case X86II::MRMSrcMem:
718 // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
720 return 1 + HasVEX_4V + HasEVEX_K;
721 case X86II::MRMSrcMem4VOp3:
722 // Skip registers encoded in reg.
723 return 1 + HasEVEX_K;
724 case X86II::MRMSrcMemOp4:
725 // Skip registers encoded in reg, VEX_VVVV, and I8IMM.
727 case X86II::MRMDestReg:
728 case X86II::MRMSrcReg:
729 case X86II::MRMSrcReg4VOp3:
730 case X86II::MRMSrcRegOp4:
732 case X86II::MRM0r: case X86II::MRM1r:
733 case X86II::MRM2r: case X86II::MRM3r:
734 case X86II::MRM4r: case X86II::MRM5r:
735 case X86II::MRM6r: case X86II::MRM7r:
738 case X86II::MRM0m: case X86II::MRM1m:
739 case X86II::MRM2m: case X86II::MRM3m:
740 case X86II::MRM4m: case X86II::MRM5m:
741 case X86II::MRM6m: case X86II::MRM7m:
742 // Start from 0, skip registers encoded in VEX_VVVV or a mask register.
743 return 0 + HasVEX_4V + HasEVEX_K;
744 case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
745 case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5:
746 case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8:
747 case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
748 case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE:
749 case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
750 case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4:
751 case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7:
752 case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA:
753 case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD:
754 case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0:
755 case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3:
756 case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6:
757 case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9:
758 case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
759 case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF:
760 case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2:
761 case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5:
762 case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8:
763 case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB:
764 case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE:
770 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
771 /// higher) register? e.g. r8, xmm8, xmm13, etc.
772 inline bool isX86_64ExtendedReg(unsigned RegNo) {
773 if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) ||
774 (RegNo >= X86::YMM8 && RegNo <= X86::YMM31) ||
775 (RegNo >= X86::ZMM8 && RegNo <= X86::ZMM31))
780 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
781 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
782 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
783 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
784 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
785 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
786 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
787 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
788 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11:
789 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15:
790 case X86::DR8: case X86::DR9: case X86::DR10: case X86::DR11:
791 case X86::DR12: case X86::DR13: case X86::DR14: case X86::DR15:
797 /// is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher)
798 /// registers? e.g. zmm21, etc.
799 static inline bool is32ExtendedReg(unsigned RegNo) {
800 return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) ||
801 (RegNo >= X86::YMM16 && RegNo <= X86::YMM31) ||
802 (RegNo >= X86::ZMM16 && RegNo <= X86::ZMM31));
806 inline bool isX86_64NonExtLowByteReg(unsigned reg) {
807 return (reg == X86::SPL || reg == X86::BPL ||
808 reg == X86::SIL || reg == X86::DIL);
811 /// isKMasked - Is this a masked instruction.
812 inline bool isKMasked(uint64_t TSFlags) {
813 return (TSFlags & X86II::EVEX_K) != 0;
816 /// isKMergedMasked - Is this a merge masked instruction.
817 inline bool isKMergeMasked(uint64_t TSFlags) {
818 return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0;
822 } // end namespace llvm;