1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides X86 specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "X86MCTargetDesc.h"
15 #include "InstPrinter/X86ATTInstPrinter.h"
16 #include "InstPrinter/X86IntelInstPrinter.h"
17 #include "X86MCAsmInfo.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/DebugInfo/CodeView/CodeView.h"
20 #include "llvm/MC/MCInstrAnalysis.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MachineLocation.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/Host.h"
28 #include "llvm/Support/TargetRegistry.h"
36 #define GET_REGINFO_MC_DESC
37 #include "X86GenRegisterInfo.inc"
39 #define GET_INSTRINFO_MC_DESC
40 #include "X86GenInstrInfo.inc"
42 #define GET_SUBTARGETINFO_MC_DESC
43 #include "X86GenSubtargetInfo.inc"
45 std::string X86_MC::ParseX86Triple(const Triple &TT) {
47 if (TT.getArch() == Triple::x86_64)
48 FS = "+64bit-mode,-32bit-mode,-16bit-mode";
49 else if (TT.getEnvironment() != Triple::CODE16)
50 FS = "-64bit-mode,+32bit-mode,-16bit-mode";
52 FS = "-64bit-mode,-32bit-mode,+16bit-mode";
57 unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
58 if (TT.getArch() == Triple::x86_64)
59 return DWARFFlavour::X86_64;
62 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
64 // Unsupported by now, just quick fallback
65 return DWARFFlavour::X86_32_Generic;
66 return DWARFFlavour::X86_32_Generic;
69 void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) {
70 // FIXME: TableGen these.
71 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
72 unsigned SEH = MRI->getEncodingValue(Reg);
73 MRI->mapLLVMRegToSEHReg(Reg, SEH);
76 // Mapping from CodeView to MC register id.
78 codeview::RegisterId CVReg;
81 { codeview::RegisterId::AL, X86::AL},
82 { codeview::RegisterId::CL, X86::CL},
83 { codeview::RegisterId::DL, X86::DL},
84 { codeview::RegisterId::BL, X86::BL},
85 { codeview::RegisterId::AH, X86::AH},
86 { codeview::RegisterId::CH, X86::CH},
87 { codeview::RegisterId::DH, X86::DH},
88 { codeview::RegisterId::BH, X86::BH},
89 { codeview::RegisterId::AX, X86::AX},
90 { codeview::RegisterId::CX, X86::CX},
91 { codeview::RegisterId::DX, X86::DX},
92 { codeview::RegisterId::BX, X86::BX},
93 { codeview::RegisterId::SP, X86::SP},
94 { codeview::RegisterId::BP, X86::BP},
95 { codeview::RegisterId::SI, X86::SI},
96 { codeview::RegisterId::DI, X86::DI},
97 { codeview::RegisterId::EAX, X86::EAX},
98 { codeview::RegisterId::ECX, X86::ECX},
99 { codeview::RegisterId::EDX, X86::EDX},
100 { codeview::RegisterId::EBX, X86::EBX},
101 { codeview::RegisterId::ESP, X86::ESP},
102 { codeview::RegisterId::EBP, X86::EBP},
103 { codeview::RegisterId::ESI, X86::ESI},
104 { codeview::RegisterId::EDI, X86::EDI},
106 { codeview::RegisterId::EFLAGS, X86::EFLAGS},
108 { codeview::RegisterId::ST0, X86::FP0},
109 { codeview::RegisterId::ST1, X86::FP1},
110 { codeview::RegisterId::ST2, X86::FP2},
111 { codeview::RegisterId::ST3, X86::FP3},
112 { codeview::RegisterId::ST4, X86::FP4},
113 { codeview::RegisterId::ST5, X86::FP5},
114 { codeview::RegisterId::ST6, X86::FP6},
115 { codeview::RegisterId::ST7, X86::FP7},
117 { codeview::RegisterId::XMM0, X86::XMM0},
118 { codeview::RegisterId::XMM1, X86::XMM1},
119 { codeview::RegisterId::XMM2, X86::XMM2},
120 { codeview::RegisterId::XMM3, X86::XMM3},
121 { codeview::RegisterId::XMM4, X86::XMM4},
122 { codeview::RegisterId::XMM5, X86::XMM5},
123 { codeview::RegisterId::XMM6, X86::XMM6},
124 { codeview::RegisterId::XMM7, X86::XMM7},
126 { codeview::RegisterId::XMM8, X86::XMM8},
127 { codeview::RegisterId::XMM9, X86::XMM9},
128 { codeview::RegisterId::XMM10, X86::XMM10},
129 { codeview::RegisterId::XMM11, X86::XMM11},
130 { codeview::RegisterId::XMM12, X86::XMM12},
131 { codeview::RegisterId::XMM13, X86::XMM13},
132 { codeview::RegisterId::XMM14, X86::XMM14},
133 { codeview::RegisterId::XMM15, X86::XMM15},
135 { codeview::RegisterId::SIL, X86::SIL},
136 { codeview::RegisterId::DIL, X86::DIL},
137 { codeview::RegisterId::BPL, X86::BPL},
138 { codeview::RegisterId::SPL, X86::SPL},
139 { codeview::RegisterId::RAX, X86::RAX},
140 { codeview::RegisterId::RBX, X86::RBX},
141 { codeview::RegisterId::RCX, X86::RCX},
142 { codeview::RegisterId::RDX, X86::RDX},
143 { codeview::RegisterId::RSI, X86::RSI},
144 { codeview::RegisterId::RDI, X86::RDI},
145 { codeview::RegisterId::RBP, X86::RBP},
146 { codeview::RegisterId::RSP, X86::RSP},
147 { codeview::RegisterId::R8, X86::R8},
148 { codeview::RegisterId::R9, X86::R9},
149 { codeview::RegisterId::R10, X86::R10},
150 { codeview::RegisterId::R11, X86::R11},
151 { codeview::RegisterId::R12, X86::R12},
152 { codeview::RegisterId::R13, X86::R13},
153 { codeview::RegisterId::R14, X86::R14},
154 { codeview::RegisterId::R15, X86::R15},
155 { codeview::RegisterId::R8B, X86::R8B},
156 { codeview::RegisterId::R9B, X86::R9B},
157 { codeview::RegisterId::R10B, X86::R10B},
158 { codeview::RegisterId::R11B, X86::R11B},
159 { codeview::RegisterId::R12B, X86::R12B},
160 { codeview::RegisterId::R13B, X86::R13B},
161 { codeview::RegisterId::R14B, X86::R14B},
162 { codeview::RegisterId::R15B, X86::R15B},
163 { codeview::RegisterId::R8W, X86::R8W},
164 { codeview::RegisterId::R9W, X86::R9W},
165 { codeview::RegisterId::R10W, X86::R10W},
166 { codeview::RegisterId::R11W, X86::R11W},
167 { codeview::RegisterId::R12W, X86::R12W},
168 { codeview::RegisterId::R13W, X86::R13W},
169 { codeview::RegisterId::R14W, X86::R14W},
170 { codeview::RegisterId::R15W, X86::R15W},
171 { codeview::RegisterId::R8D, X86::R8D},
172 { codeview::RegisterId::R9D, X86::R9D},
173 { codeview::RegisterId::R10D, X86::R10D},
174 { codeview::RegisterId::R11D, X86::R11D},
175 { codeview::RegisterId::R12D, X86::R12D},
176 { codeview::RegisterId::R13D, X86::R13D},
177 { codeview::RegisterId::R14D, X86::R14D},
178 { codeview::RegisterId::R15D, X86::R15D},
179 { codeview::RegisterId::AMD64_YMM0, X86::YMM0},
180 { codeview::RegisterId::AMD64_YMM1, X86::YMM1},
181 { codeview::RegisterId::AMD64_YMM2, X86::YMM2},
182 { codeview::RegisterId::AMD64_YMM3, X86::YMM3},
183 { codeview::RegisterId::AMD64_YMM4, X86::YMM4},
184 { codeview::RegisterId::AMD64_YMM5, X86::YMM5},
185 { codeview::RegisterId::AMD64_YMM6, X86::YMM6},
186 { codeview::RegisterId::AMD64_YMM7, X86::YMM7},
187 { codeview::RegisterId::AMD64_YMM8, X86::YMM8},
188 { codeview::RegisterId::AMD64_YMM9, X86::YMM9},
189 { codeview::RegisterId::AMD64_YMM10, X86::YMM10},
190 { codeview::RegisterId::AMD64_YMM11, X86::YMM11},
191 { codeview::RegisterId::AMD64_YMM12, X86::YMM12},
192 { codeview::RegisterId::AMD64_YMM13, X86::YMM13},
193 { codeview::RegisterId::AMD64_YMM14, X86::YMM14},
194 { codeview::RegisterId::AMD64_YMM15, X86::YMM15},
196 for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
197 MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
200 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
201 StringRef CPU, StringRef FS) {
202 std::string ArchFS = X86_MC::ParseX86Triple(TT);
205 ArchFS = (Twine(ArchFS) + "," + FS).str();
210 std::string CPUName = CPU;
214 return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS);
217 static MCInstrInfo *createX86MCInstrInfo() {
218 MCInstrInfo *X = new MCInstrInfo();
219 InitX86MCInstrInfo(X);
223 static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
224 unsigned RA = (TT.getArch() == Triple::x86_64)
225 ? X86::RIP // Should have dwarf #16.
226 : X86::EIP; // Should have dwarf #8.
228 MCRegisterInfo *X = new MCRegisterInfo();
229 InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
230 X86_MC::getDwarfRegFlavour(TT, true), RA);
231 X86_MC::initLLVMToSEHAndCVRegMapping(X);
235 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
236 const Triple &TheTriple) {
237 bool is64Bit = TheTriple.getArch() == Triple::x86_64;
240 if (TheTriple.isOSBinFormatMachO()) {
242 MAI = new X86_64MCAsmInfoDarwin(TheTriple);
244 MAI = new X86MCAsmInfoDarwin(TheTriple);
245 } else if (TheTriple.isOSBinFormatELF()) {
246 // Force the use of an ELF container.
247 MAI = new X86ELFMCAsmInfo(TheTriple);
248 } else if (TheTriple.isWindowsMSVCEnvironment() ||
249 TheTriple.isWindowsCoreCLREnvironment()) {
250 MAI = new X86MCAsmInfoMicrosoft(TheTriple);
251 } else if (TheTriple.isOSCygMing() ||
252 TheTriple.isWindowsItaniumEnvironment()) {
253 MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
255 // The default is ELF.
256 MAI = new X86ELFMCAsmInfo(TheTriple);
259 // Initialize initial frame state.
260 // Calculate amount of bytes used for return address storing
261 int stackGrowth = is64Bit ? -8 : -4;
263 // Initial state of the frame pointer is esp+stackGrowth.
264 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
265 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
266 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
267 MAI->addInitialFrameState(Inst);
269 // Add return address to move list
270 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
271 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
272 nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
273 MAI->addInitialFrameState(Inst2);
278 static MCInstPrinter *createX86MCInstPrinter(const Triple &T,
279 unsigned SyntaxVariant,
280 const MCAsmInfo &MAI,
281 const MCInstrInfo &MII,
282 const MCRegisterInfo &MRI) {
283 if (SyntaxVariant == 0)
284 return new X86ATTInstPrinter(MAI, MII, MRI);
285 if (SyntaxVariant == 1)
286 return new X86IntelInstPrinter(MAI, MII, MRI);
290 static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple,
292 // Default to the stock relocation info.
293 return llvm::createMCRelocationInfo(TheTriple, Ctx);
296 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
297 return new MCInstrAnalysis(Info);
300 // Force static initialization.
301 extern "C" void LLVMInitializeX86TargetMC() {
302 for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) {
303 // Register the MC asm info.
304 RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
306 // Register the MC instruction info.
307 TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);
309 // Register the MC register info.
310 TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo);
312 // Register the MC subtarget info.
313 TargetRegistry::RegisterMCSubtargetInfo(*T,
314 X86_MC::createX86MCSubtargetInfo);
316 // Register the MC instruction analyzer.
317 TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis);
319 // Register the code emitter.
320 TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter);
322 // Register the obj target streamer.
323 TargetRegistry::RegisterObjectTargetStreamer(*T,
324 createX86ObjectTargetStreamer);
326 // Register the asm target streamer.
327 TargetRegistry::RegisterAsmTargetStreamer(*T, createX86AsmTargetStreamer);
329 TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer);
331 // Register the MCInstPrinter.
332 TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter);
334 // Register the MC relocation info.
335 TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo);
338 // Register the asm backend.
339 TargetRegistry::RegisterMCAsmBackend(getTheX86_32Target(),
340 createX86_32AsmBackend);
341 TargetRegistry::RegisterMCAsmBackend(getTheX86_64Target(),
342 createX86_64AsmBackend);
345 unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size,
352 default: return getX86SubSuperRegisterOrZero(Reg, 64);
353 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
355 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
357 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
359 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
361 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
363 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
365 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
367 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
373 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
375 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
377 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
379 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
381 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
383 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
385 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
387 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
389 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
391 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
393 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
395 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
397 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
399 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
401 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
403 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
410 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
412 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
414 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
416 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
418 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
420 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
422 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
424 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
426 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
428 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
430 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
432 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
434 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
436 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
438 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
440 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
446 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
448 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
450 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
452 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
454 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
456 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
458 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
460 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
462 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
464 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
466 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
468 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
470 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
472 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
474 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
476 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
482 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
484 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
486 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
488 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
490 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
492 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
494 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
496 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
498 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
500 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
502 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
504 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
506 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
508 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
510 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
512 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
518 unsigned llvm::getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) {
519 unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High);
520 assert(Res != 0 && "Unexpected register or VT");