1 //===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides X86 specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
15 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/Support/DataTypes.h"
26 class MCObjectTargetWriter;
29 class MCSubtargetInfo;
30 class MCRelocationInfo;
31 class MCTargetOptions;
36 class raw_pwrite_stream;
38 Target &getTheX86_32Target();
39 Target &getTheX86_64Target();
41 /// Flavour of dwarf regnumbers
43 namespace DWARFFlavour {
45 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2
49 /// Native X86 register numbers
53 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
58 std::string ParseX86Triple(const Triple &TT);
60 unsigned getDwarfRegFlavour(const Triple &TT, bool isEH);
62 void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI);
64 /// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc.
65 /// do not need to go through TargetRegistry.
66 MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU,
70 MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
71 const MCRegisterInfo &MRI,
74 MCAsmBackend *createX86_32AsmBackend(const Target &T,
75 const MCSubtargetInfo &STI,
76 const MCRegisterInfo &MRI,
77 const MCTargetOptions &Options);
78 MCAsmBackend *createX86_64AsmBackend(const Target &T,
79 const MCSubtargetInfo &STI,
80 const MCRegisterInfo &MRI,
81 const MCTargetOptions &Options);
83 /// Implements X86-only directives for assembly emission.
84 MCTargetStreamer *createX86AsmTargetStreamer(MCStreamer &S,
85 formatted_raw_ostream &OS,
86 MCInstPrinter *InstPrint,
89 /// Implements X86-only directives for object files.
90 MCTargetStreamer *createX86ObjectTargetStreamer(MCStreamer &OS,
91 const MCSubtargetInfo &STI);
93 /// Construct an X86 Windows COFF machine code streamer which will generate
94 /// PE/COFF format object files.
96 /// Takes ownership of \p AB and \p CE.
97 MCStreamer *createX86WinCOFFStreamer(MCContext &C,
98 std::unique_ptr<MCAsmBackend> &&AB,
99 std::unique_ptr<MCObjectWriter> &&OW,
100 std::unique_ptr<MCCodeEmitter> &&CE,
102 bool IncrementalLinkerCompatible);
104 /// Construct an X86 Mach-O object writer.
105 std::unique_ptr<MCObjectTargetWriter>
106 createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype);
108 /// Construct an X86 ELF object writer.
109 std::unique_ptr<MCObjectTargetWriter>
110 createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine);
111 /// Construct an X86 Win COFF object writer.
112 std::unique_ptr<MCObjectTargetWriter>
113 createX86WinCOFFObjectWriter(bool Is64Bit);
115 /// Returns the sub or super register of a specific X86 register.
116 /// e.g. getX86SubSuperRegister(X86::EAX, 16) returns X86::AX.
118 unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false);
120 /// Returns the sub or super register of a specific X86 register.
121 /// Like getX86SubSuperRegister() but returns 0 on error.
122 unsigned getX86SubSuperRegisterOrZero(unsigned, unsigned,
125 } // End llvm namespace
128 // Defines symbolic names for X86 registers. This defines a mapping from
129 // register name to register number.
131 #define GET_REGINFO_ENUM
132 #include "X86GenRegisterInfo.inc"
134 // Defines symbolic names for the X86 instructions.
136 #define GET_INSTRINFO_ENUM
137 #define GET_INSTRINFO_MC_HELPER_DECLS
138 #include "X86GenInstrInfo.inc"
140 #define GET_SUBTARGETINFO_ENUM
141 #include "X86GenSubtargetInfo.inc"