1 //===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides X86 specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
15 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/Support/DataTypes.h"
28 class MCSubtargetInfo;
29 class MCRelocationInfo;
30 class MCTargetOptions;
35 class raw_pwrite_stream;
37 Target &getTheX86_32Target();
38 Target &getTheX86_64Target();
40 /// Flavour of dwarf regnumbers
42 namespace DWARFFlavour {
44 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2
48 /// Native X86 register numbers
52 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
57 std::string ParseX86Triple(const Triple &TT);
59 unsigned getDwarfRegFlavour(const Triple &TT, bool isEH);
61 void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI);
63 /// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc.
64 /// do not need to go through TargetRegistry.
65 MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU,
69 MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
70 const MCRegisterInfo &MRI,
73 MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
74 const Triple &TT, StringRef CPU,
75 const MCTargetOptions &Options);
76 MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
77 const Triple &TT, StringRef CPU,
78 const MCTargetOptions &Options);
80 /// Construct an X86 Windows COFF machine code streamer which will generate
81 /// PE/COFF format object files.
83 /// Takes ownership of \p AB and \p CE.
84 MCStreamer *createX86WinCOFFStreamer(MCContext &C, MCAsmBackend &AB,
85 raw_pwrite_stream &OS, MCCodeEmitter *CE,
86 bool RelaxAll, bool IncrementalLinkerCompatible);
88 /// Construct an X86 Mach-O object writer.
89 MCObjectWriter *createX86MachObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
93 /// Construct an X86 ELF object writer.
94 MCObjectWriter *createX86ELFObjectWriter(raw_pwrite_stream &OS, bool IsELF64,
95 uint8_t OSABI, uint16_t EMachine);
96 /// Construct an X86 Win COFF object writer.
97 MCObjectWriter *createX86WinCOFFObjectWriter(raw_pwrite_stream &OS,
100 /// Returns the sub or super register of a specific X86 register.
101 /// e.g. getX86SubSuperRegister(X86::EAX, 16) returns X86::AX.
103 unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false);
105 /// Returns the sub or super register of a specific X86 register.
106 /// Like getX86SubSuperRegister() but returns 0 on error.
107 unsigned getX86SubSuperRegisterOrZero(unsigned, unsigned,
110 } // End llvm namespace
113 // Defines symbolic names for X86 registers. This defines a mapping from
114 // register name to register number.
116 #define GET_REGINFO_ENUM
117 #include "X86GenRegisterInfo.inc"
119 // Defines symbolic names for the X86 instructions.
121 #define GET_INSTRINFO_ENUM
122 #include "X86GenInstrInfo.inc"
124 #define GET_SUBTARGETINFO_ENUM
125 #include "X86GenSubtargetInfo.inc"