1 //===-- X86.h - Top-level interface for X86 representation ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the entry points for global functions defined in the x86
11 // target library, as used by the LLVM JIT.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_X86_X86_H
16 #define LLVM_LIB_TARGET_X86_X86_H
18 #include "llvm/Support/CodeGen.h"
24 class InstructionSelector;
26 class X86RegisterBankInfo;
28 class X86TargetMachine;
30 /// This pass converts a legalized DAG into a X86-specific DAG, ready for
31 /// instruction scheduling.
32 FunctionPass *createX86ISelDag(X86TargetMachine &TM,
33 CodeGenOpt::Level OptLevel);
35 /// This pass initializes a global base register for PIC on x86-32.
36 FunctionPass *createX86GlobalBaseRegPass();
38 /// This pass combines multiple accesses to local-dynamic TLS variables so that
39 /// the TLS base address for the module is only fetched once per execution path
40 /// through the function.
41 FunctionPass *createCleanupLocalDynamicTLSPass();
43 /// This function returns a pass which converts floating-point register
44 /// references and pseudo instructions into floating-point stack references and
45 /// physical instructions.
46 FunctionPass *createX86FloatingPointStackifierPass();
48 /// This pass inserts AVX vzeroupper instructions before each call to avoid
49 /// transition penalty between functions encoded with AVX and SSE.
50 FunctionPass *createX86IssueVZeroUpperPass();
52 /// Return a pass that pads short functions with NOOPs.
53 /// This will prevent a stall when returning on the Atom.
54 FunctionPass *createX86PadShortFunctions();
56 /// Return a pass that selectively replaces certain instructions (like add,
57 /// sub, inc, dec, some shifts, and some multiplies) by equivalent LEA
58 /// instructions, in order to eliminate execution delays in some processors.
59 FunctionPass *createX86FixupLEAs();
61 /// Return a pass that removes redundant LEA instructions and redundant address
63 FunctionPass *createX86OptimizeLEAs();
65 /// Return a pass that transforms setcc + movzx pairs into xor + setcc.
66 FunctionPass *createX86FixupSetCC();
68 /// Return a pass that expands WinAlloca pseudo-instructions.
69 FunctionPass *createX86WinAllocaExpander();
71 /// Return a pass that optimizes the code-size of x86 call sequences. This is
72 /// done by replacing esp-relative movs with pushes.
73 FunctionPass *createX86CallFrameOptimization();
75 /// Return an IR pass that inserts EH registration stack objects and explicit
76 /// EH state updates. This pass must run after EH preparation, which does
77 /// Windows-specific but architecture-neutral preparation.
78 FunctionPass *createX86WinEHStatePass();
80 /// Return a Machine IR pass that expands X86-specific pseudo
81 /// instructions into a sequence of actual instructions. This pass
82 /// must run after prologue/epilogue insertion and before lowering
83 /// the MachineInstr to MC.
84 FunctionPass *createX86ExpandPseudoPass();
86 /// This pass converts X86 cmov instructions into branch when profitable.
87 FunctionPass *createX86CmovConverterPass();
89 /// Return a Machine IR pass that selectively replaces
90 /// certain byte and word instructions by equivalent 32 bit instructions,
91 /// in order to eliminate partial register usage, false dependences on
92 /// the upper portions of registers, and to save code size.
93 FunctionPass *createX86FixupBWInsts();
95 /// Return a Machine IR pass that reassigns instruction chains from one domain
96 /// to another, when profitable.
97 FunctionPass *createX86DomainReassignmentPass();
99 void initializeFixupBWInstPassPass(PassRegistry &);
101 /// This pass replaces EVEX encoded of AVX-512 instructiosn by VEX
102 /// encoding when possible in order to reduce code size.
103 FunctionPass *createX86EvexToVexInsts();
105 InstructionSelector *createX86InstructionSelector(const X86TargetMachine &TM,
107 X86RegisterBankInfo &);
109 void initializeEvexToVexInstPassPass(PassRegistry &);
111 } // End llvm namespace