contrib/llvm/lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureX87     : SubtargetFeature<"x87","HasX87", "true",
  35                                       "Enable X87 float instructions">;
  36
  37 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  38                                       "Enable conditional move instructions">;
  39
  40 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  41                                        "Support POPCNT instruction">;
  42
  43 def FeatureFXSR    : SubtargetFeature<"fxsr", "HasFXSR", "true",
  44                                       "Support fxsave/fxrestore instructions">;
  45
  46 def FeatureXSAVE   : SubtargetFeature<"xsave", "HasXSAVE", "true",
  47                                        "Support xsave instructions">;
  48
  49 def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
  50                                        "Support xsaveopt instructions">;
  51
  52 def FeatureXSAVEC  : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
  53                                        "Support xsavec instructions">;
  54
  55 def FeatureXSAVES  : SubtargetFeature<"xsaves", "HasXSAVES", "true",
  56                                        "Support xsaves instructions">;
  57
  58 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  59                                       "Enable SSE instructions",
  60                                       // SSE codegen depends on cmovs, and all
  61                                       // SSE1+ processors support them.
  62                                       [FeatureCMOV]>;
  63 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  64                                       "Enable SSE2 instructions",
  65                                       [FeatureSSE1]>;
  66 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  67                                       "Enable SSE3 instructions",
  68                                       [FeatureSSE2]>;
  69 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  70                                       "Enable SSSE3 instructions",
  71                                       [FeatureSSE3]>;
  72 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  73                                       "Enable SSE 4.1 instructions",
  74                                       [FeatureSSSE3]>;
  75 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  76                                       "Enable SSE 4.2 instructions",
  77                                       [FeatureSSE41]>;
  78 // The MMX subtarget feature is separate from the rest of the SSE features
  79 // because it's important (for odd compatibility reasons) to be able to
  80 // turn it off explicitly while allowing SSE+ to be on.
  81 def FeatureMMX     : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
  82                                       "Enable MMX instructions">;
  83 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  84                                       "Enable 3DNow! instructions",
  85                                       [FeatureMMX]>;
  86 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  87                                       "Enable 3DNow! Athlon instructions",
  88                                       [Feature3DNow]>;
  89 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  90 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  91 // without disabling 64-bit mode.
  92 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  93                                       "Support 64-bit instructions",
  94                                       [FeatureCMOV]>;
  95 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  96                                       "64-bit with cmpxchg16b",
  97                                       [Feature64Bit]>;
  98 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  99                                        "Bit testing of memory is slow">;
 100 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
 101                                        "SHLD instruction is slow">;
 102 def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
 103                                         "PMULLD instruction is slow">;
 104 // FIXME: This should not apply to CPUs that do not have SSE.
 105 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
 106                                 "IsUAMem16Slow", "true",
 107                                 "Slow unaligned 16-byte memory access">;
 108 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
 109                                 "IsUAMem32Slow", "true",
 110                                 "Slow unaligned 32-byte memory access">;
 111 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
 112                                       "Support SSE 4a instructions",
 113                                       [FeatureSSE3]>;
 114
 115 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
 116                                       "Enable AVX instructions",
 117                                       [FeatureSSE42]>;
 118 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 119                                       "Enable AVX2 instructions",
 120                                       [FeatureAVX]>;
 121 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 122                                       "Enable AVX-512 instructions",
 123                                       [FeatureAVX2]>;
 124 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 125                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 126                                       [FeatureAVX512]>;
 127 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 128                       "Enable AVX-512 Conflict Detection Instructions",
 129                                       [FeatureAVX512]>;
 130 def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ",
 131                        "true", "Enable AVX-512 Population Count Instructions",
 132                                       [FeatureAVX512]>;
 133 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 134                       "Enable AVX-512 PreFetch Instructions",
 135                                       [FeatureAVX512]>;
 136 def FeaturePREFETCHWT1  : SubtargetFeature<"prefetchwt1", "HasPFPREFETCHWT1",
 137                                    "true",
 138                                    "Prefetch with Intent to Write and T1 Hint">;
 139 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 140                       "Enable AVX-512 Doubleword and Quadword Instructions",
 141                                       [FeatureAVX512]>;
 142 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 143                       "Enable AVX-512 Byte and Word Instructions",
 144                                       [FeatureAVX512]>;
 145 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 146                       "Enable AVX-512 Vector Length eXtensions",
 147                                       [FeatureAVX512]>;
 148 def FeatureVBMI     : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
 149                       "Enable AVX-512 Vector Byte Manipulation Instructions",
 150                                       [FeatureBWI]>;
 151 def FeatureIFMA     : SubtargetFeature<"avx512ifma", "HasIFMA", "true",
 152                       "Enable AVX-512 Integer Fused Multiple-Add",
 153                                       [FeatureAVX512]>;
 154 def FeaturePKU   : SubtargetFeature<"pku", "HasPKU", "true",
 155                       "Enable protection keys">;
 156 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 157                          "Enable packed carry-less multiplication instructions",
 158                                [FeatureSSE2]>;
 159 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 160                                       "Enable three-operand fused multiple-add",
 161                                       [FeatureAVX]>;
 162 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 163                                       "Enable four-operand fused multiple-add",
 164                                       [FeatureAVX, FeatureSSE4A]>;
 165 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 166                                       "Enable XOP instructions",
 167                                       [FeatureFMA4]>;
 168 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 169                                           "HasSSEUnalignedMem", "true",
 170                       "Allow unaligned memory operands with SSE instructions">;
 171 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 172                                       "Enable AES instructions",
 173                                       [FeatureSSE2]>;
 174 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 175                                       "Enable TBM instructions">;
 176 def FeatureLWP     : SubtargetFeature<"lwp", "HasLWP", "true",
 177                                       "Enable LWP instructions">;
 178 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 179                                       "Support MOVBE instruction">;
 180 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 181                                       "Support RDRAND instruction">;
 182 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 183                        "Support 16-bit floating point conversion instructions",
 184                        [FeatureAVX]>;
 185 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 186                                        "Support FS/GS Base instructions">;
 187 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 188                                       "Support LZCNT instruction">;
 189 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 190                                       "Support BMI instructions">;
 191 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 192                                       "Support BMI2 instructions">;
 193 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 194                                       "Support RTM instructions">;
 195 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 196                                       "Support ADX instructions">;
 197 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 198                                       "Enable SHA instructions",
 199                                       [FeatureSSE2]>;
 200 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 201                                       "Support PRFCHW instructions">;
 202 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 203                                       "Support RDSEED instruction">;
 204 def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
 205                                        "Support LAHF and SAHF instructions">;
 206 def FeatureMWAITX  : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
 207                                       "Enable MONITORX/MWAITX timer functionality">;
 208 def FeatureCLZERO  : SubtargetFeature<"clzero", "HasCLZERO", "true",
 209                                       "Enable Cache Line Zero">;
 210 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
 211                                       "Support MPX instructions">;
 212 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 213                                      "Use LEA for adjusting the stack pointer">;
 214 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 215                                      "HasSlowDivide32", "true",
 216                                      "Use 8-bit divide for positive values less than 256">;
 217 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",
 218                                      "HasSlowDivide64", "true",
 219                                      "Use 32-bit divide for positive values less than 2^32">;
 220 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 221                                      "PadShortFunctions", "true",
 222                                      "Pad short functions">;
 223 def FeatureSGX     : SubtargetFeature<"sgx", "HasSGX", "true",
 224                                       "Enable Software Guard Extensions">;
 225 def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
 226                                       "Flush A Cache Line Optimized">;
 227 def FeatureCLWB    : SubtargetFeature<"clwb", "HasCLWB", "true",
 228                                       "Cache Line Write Back">;
 229 // TODO: This feature ought to be renamed.
 230 // What it really refers to are CPUs for which certain instructions
 231 // (which ones besides the example below?) are microcoded.
 232 // The best examples of this are the memory forms of CALL and PUSH
 233 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
 234 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 235                                      "CallRegIndirect", "true",
 236                                      "Call register indirect">;
 237 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 238                                    "LEA instruction needs inputs at AG stage">;
 239 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 240                                    "LEA instruction with certain arguments is slow">;
 241 def FeatureSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true",
 242                                    "LEA instruction with 3 ops or certain registers is slow">;
 243 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 244                                    "INC and DEC instructions are slower than ADD and SUB">;
 245 def FeatureSoftFloat
 246     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
 247                        "Use software floating point features.">;
 248 // On some X86 processors, there is no performance hazard to writing only the
 249 // lower parts of a YMM or ZMM register without clearing the upper part.
 250 def FeatureFastPartialYMMorZMMWrite
 251     : SubtargetFeature<"fast-partial-ymm-or-zmm-write",
 252                        "HasFastPartialYMMorZMMWrite",
 253                        "true", "Partial writes to YMM/ZMM registers are fast">;
 254 // FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
 255 // than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if
 256 // vector FSQRT has higher throughput than the corresponding NR code.
 257 // The idea is that throughput bound code is likely to be vectorized, so for
 258 // vectorized code we should care about the throughput of SQRT operations.
 259 // But if the code is scalar that probably means that the code has some kind of
 260 // dependency and we should care more about reducing the latency.
 261 def FeatureFastScalarFSQRT
 262     : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
 263                        "true", "Scalar SQRT is fast (disable Newton-Raphson)">;
 264 def FeatureFastVectorFSQRT
 265     : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
 266                        "true", "Vector SQRT is fast (disable Newton-Raphson)">;
 267 // If lzcnt has equivalent latency/throughput to most simple integer ops, it can
 268 // be used to replace test/set sequences.
 269 def FeatureFastLZCNT
 270     : SubtargetFeature<
 271           "fast-lzcnt", "HasFastLZCNT", "true",
 272           "LZCNT instructions are as fast as most simple integer ops">;
 273
 274
 275 // Sandy Bridge and newer processors can use SHLD with the same source on both
 276 // inputs to implement rotate to avoid the partial flag update of the normal
 277 // rotate instructions.
 278 def FeatureFastSHLDRotate
 279     : SubtargetFeature<
 280           "fast-shld-rotate", "HasFastSHLDRotate", "true",
 281           "SHLD can be used as a faster rotate">;
 282
 283 // Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
 284 // "string operations"). See "REP String Enhancement" in the Intel Software
 285 // Development Manual. This feature essentially means that REP MOVSB will copy
 286 // using the largest available size instead of copying bytes one by one, making
 287 // it at least as fast as REPMOVS{W,D,Q}.
 288 def FeatureERMSB
 289     : SubtargetFeature<
 290           "ermsb", "HasERMSB", "true",
 291           "REP MOVS/STOS are fast">;
 292
 293 //===----------------------------------------------------------------------===//
 294 // X86 processors supported.
 295 //===----------------------------------------------------------------------===//
 296
 297 include "X86Schedule.td"
 298
 299 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 300                     "Intel Atom processors">;
 301 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 302                     "Intel Silvermont processors">;
 303 def ProcIntelGLM  : SubtargetFeature<"glm", "X86ProcFamily", "IntelGLM",
 304                     "Intel Goldmont processors">;
 305
 306 class Proc<string Name, list<SubtargetFeature> Features>
 307  : ProcessorModel<Name, GenericModel, Features>;
 308
 309 def : Proc<"generic",         [FeatureX87, FeatureSlowUAMem16]>;
 310 def : Proc<"i386",            [FeatureX87, FeatureSlowUAMem16]>;
 311 def : Proc<"i486",            [FeatureX87, FeatureSlowUAMem16]>;
 312 def : Proc<"i586",            [FeatureX87, FeatureSlowUAMem16]>;
 313 def : Proc<"pentium",         [FeatureX87, FeatureSlowUAMem16]>;
 314 def : Proc<"pentium-mmx",     [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 315 def : Proc<"i686",            [FeatureX87, FeatureSlowUAMem16]>;
 316 def : Proc<"pentiumpro",      [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
 317 def : Proc<"pentium2",        [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 318                                FeatureCMOV, FeatureFXSR]>;
 319 def : Proc<"pentium3",        [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 320                                FeatureSSE1, FeatureFXSR]>;
 321 def : Proc<"pentium3m",       [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 322                                FeatureSSE1, FeatureFXSR, FeatureSlowBTMem]>;
 323
 324 // Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
 325 // The intent is to enable it for pentium4 which is the current default
 326 // processor in a vanilla 32-bit clang compilation when no specific
 327 // architecture is specified.  This generally gives a nice performance
 328 // increase on silvermont, with largely neutral behavior on other
 329 // contemporary large core processors.
 330 // pentium-m, pentium4m, prescott and nocona are included as a preventative
 331 // measure to avoid performance surprises, in case clang's default cpu
 332 // changes slightly.
 333
 334 def : ProcessorModel<"pentium-m", GenericPostRAModel,
 335                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 336                       FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>;
 337
 338 def : ProcessorModel<"pentium4", GenericPostRAModel,
 339                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 340                       FeatureSSE2, FeatureFXSR]>;
 341
 342 def : ProcessorModel<"pentium4m", GenericPostRAModel,
 343                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 344                       FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>;
 345
 346 // Intel Quark.
 347 def : Proc<"lakemont",        []>;
 348
 349 // Intel Core Duo.
 350 def : ProcessorModel<"yonah", SandyBridgeModel,
 351                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
 352                       FeatureFXSR, FeatureSlowBTMem]>;
 353
 354 // NetBurst.
 355 def : ProcessorModel<"prescott", GenericPostRAModel,
 356                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
 357                       FeatureFXSR, FeatureSlowBTMem]>;
 358 def : ProcessorModel<"nocona", GenericPostRAModel, [
 359   FeatureX87,
 360   FeatureSlowUAMem16,
 361   FeatureMMX,
 362   FeatureSSE3,
 363   FeatureFXSR,
 364   FeatureCMPXCHG16B,
 365   FeatureSlowBTMem
 366 ]>;
 367
 368 // Intel Core 2 Solo/Duo.
 369 def : ProcessorModel<"core2", SandyBridgeModel, [
 370   FeatureX87,
 371   FeatureSlowUAMem16,
 372   FeatureMMX,
 373   FeatureSSSE3,
 374   FeatureFXSR,
 375   FeatureCMPXCHG16B,
 376   FeatureSlowBTMem,
 377   FeatureLAHFSAHF
 378 ]>;
 379 def : ProcessorModel<"penryn", SandyBridgeModel, [
 380   FeatureX87,
 381   FeatureSlowUAMem16,
 382   FeatureMMX,
 383   FeatureSSE41,
 384   FeatureFXSR,
 385   FeatureCMPXCHG16B,
 386   FeatureSlowBTMem,
 387   FeatureLAHFSAHF
 388 ]>;
 389
 390 // Atom CPUs.
 391 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 392   ProcIntelAtom,
 393   FeatureX87,
 394   FeatureSlowUAMem16,
 395   FeatureMMX,
 396   FeatureSSSE3,
 397   FeatureFXSR,
 398   FeatureCMPXCHG16B,
 399   FeatureMOVBE,
 400   FeatureSlowBTMem,
 401   FeatureLEAForSP,
 402   FeatureSlowDivide32,
 403   FeatureSlowDivide64,
 404   FeatureCallRegIndirect,
 405   FeatureLEAUsesAG,
 406   FeaturePadShortFunctions,
 407   FeatureLAHFSAHF
 408 ]>;
 409 def : BonnellProc<"bonnell">;
 410 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 411
 412 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 413   ProcIntelSLM,
 414   FeatureX87,
 415   FeatureMMX,
 416   FeatureSSE42,
 417   FeatureFXSR,
 418   FeatureCMPXCHG16B,
 419   FeatureMOVBE,
 420   FeaturePOPCNT,
 421   FeaturePCLMUL,
 422   FeatureAES,
 423   FeatureSlowDivide64,
 424   FeatureCallRegIndirect,
 425   FeaturePRFCHW,
 426   FeatureSlowLEA,
 427   FeatureSlowIncDec,
 428   FeatureSlowBTMem,
 429   FeatureSlowPMULLD,
 430   FeatureLAHFSAHF
 431 ]>;
 432 def : SilvermontProc<"silvermont">;
 433 def : SilvermontProc<"slm">; // Legacy alias.
 434
 435 class GoldmontProc<string Name> : ProcessorModel<Name, SLMModel, [
 436   ProcIntelGLM,
 437   FeatureX87,
 438   FeatureMMX,
 439   FeatureSSE42,
 440   FeatureFXSR,
 441   FeatureCMPXCHG16B,
 442   FeatureMOVBE,
 443   FeaturePOPCNT,
 444   FeaturePCLMUL,
 445   FeatureAES,
 446   FeaturePRFCHW,
 447   FeatureCallRegIndirect,
 448   FeatureSlowLEA,
 449   FeatureSlowIncDec,
 450   FeatureSlowBTMem,
 451   FeatureLAHFSAHF,
 452   FeatureMPX,
 453   FeatureSHA,
 454   FeatureRDRAND,
 455   FeatureRDSEED,
 456   FeatureXSAVE,
 457   FeatureXSAVEOPT,
 458   FeatureXSAVEC,
 459   FeatureXSAVES,
 460   FeatureCLFLUSHOPT
 461 ]>;
 462 def : GoldmontProc<"goldmont">;
 463
 464 // "Arrandale" along with corei3 and corei5
 465 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 466   FeatureX87,
 467   FeatureMMX,
 468   FeatureSSE42,
 469   FeatureFXSR,
 470   FeatureCMPXCHG16B,
 471   FeatureSlowBTMem,
 472   FeaturePOPCNT,
 473   FeatureLAHFSAHF
 474 ]>;
 475 def : NehalemProc<"nehalem">;
 476 def : NehalemProc<"corei7">;
 477
 478 // Westmere is a similar machine to nehalem with some additional features.
 479 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 480 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 481   FeatureX87,
 482   FeatureMMX,
 483   FeatureSSE42,
 484   FeatureFXSR,
 485   FeatureCMPXCHG16B,
 486   FeatureSlowBTMem,
 487   FeaturePOPCNT,
 488   FeatureAES,
 489   FeaturePCLMUL,
 490   FeatureLAHFSAHF
 491 ]>;
 492 def : WestmereProc<"westmere">;
 493
 494 class ProcessorFeatures<list<SubtargetFeature> Inherited,
 495                         list<SubtargetFeature> NewFeatures> {
 496   list<SubtargetFeature> Value = !listconcat(Inherited, NewFeatures);
 497 }
 498
 499 class ProcModel<string Name, SchedMachineModel Model,
 500                 list<SubtargetFeature> ProcFeatures,
 501                 list<SubtargetFeature> OtherFeatures> :
 502   ProcessorModel<Name, Model, !listconcat(ProcFeatures, OtherFeatures)>;
 503
 504 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 505 // rather than a superset.
 506 def SNBFeatures : ProcessorFeatures<[], [
 507   FeatureX87,
 508   FeatureMMX,
 509   FeatureAVX,
 510   FeatureFXSR,
 511   FeatureCMPXCHG16B,
 512   FeaturePOPCNT,
 513   FeatureAES,
 514   FeatureSlowDivide64,
 515   FeaturePCLMUL,
 516   FeatureXSAVE,
 517   FeatureXSAVEOPT,
 518   FeatureLAHFSAHF,
 519   FeatureSlow3OpsLEA,
 520   FeatureFastScalarFSQRT,
 521   FeatureFastSHLDRotate
 522 ]>;
 523
 524 class SandyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
 525                                                SNBFeatures.Value, [
 526   FeatureSlowBTMem,
 527   FeatureSlowUAMem32
 528 ]>;
 529 def : SandyBridgeProc<"sandybridge">;
 530 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 531
 532 def IVBFeatures : ProcessorFeatures<SNBFeatures.Value, [
 533   FeatureRDRAND,
 534   FeatureF16C,
 535   FeatureFSGSBase
 536 ]>;
 537
 538 class IvyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
 539                                              IVBFeatures.Value, [
 540   FeatureSlowBTMem,
 541   FeatureSlowUAMem32
 542 ]>;
 543 def : IvyBridgeProc<"ivybridge">;
 544 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 545
 546 def HSWFeatures : ProcessorFeatures<IVBFeatures.Value, [
 547   FeatureAVX2,
 548   FeatureBMI,
 549   FeatureBMI2,
 550   FeatureERMSB,
 551   FeatureFMA,
 552   FeatureLZCNT,
 553   FeatureMOVBE,
 554   FeatureSlowIncDec
 555 ]>;
 556
 557 class HaswellProc<string Name> : ProcModel<Name, HaswellModel,
 558                                            HSWFeatures.Value, []>;
 559 def : HaswellProc<"haswell">;
 560 def : HaswellProc<"core-avx2">; // Legacy alias.
 561
 562 def BDWFeatures : ProcessorFeatures<HSWFeatures.Value, [
 563   FeatureADX,
 564   FeatureRDSEED
 565 ]>;
 566 class BroadwellProc<string Name> : ProcModel<Name, HaswellModel,
 567                                              BDWFeatures.Value, []>;
 568 def : BroadwellProc<"broadwell">;
 569
 570 def SKLFeatures : ProcessorFeatures<BDWFeatures.Value, [
 571   FeatureMPX,
 572   FeatureRTM,
 573   FeatureXSAVEC,
 574   FeatureXSAVES,
 575   FeatureSGX,
 576   FeatureCLFLUSHOPT,
 577   FeatureFastVectorFSQRT
 578 ]>;
 579
 580 // FIXME: define SKL model
 581 class SkylakeClientProc<string Name> : ProcModel<Name, HaswellModel,
 582                                                  SKLFeatures.Value, []>;
 583 def : SkylakeClientProc<"skylake">;
 584
 585 // FIXME: define KNL model
 586 class KnightsLandingProc<string Name> : ProcModel<Name, HaswellModel,
 587                                                   IVBFeatures.Value, [
 588   FeatureAVX512,
 589   FeatureERI,
 590   FeatureCDI,
 591   FeaturePFI,
 592   FeaturePREFETCHWT1,
 593   FeatureADX,
 594   FeatureRDSEED,
 595   FeatureMOVBE,
 596   FeatureLZCNT,
 597   FeatureBMI,
 598   FeatureBMI2,
 599   FeatureFMA,
 600   FeatureFastPartialYMMorZMMWrite
 601 ]>;
 602 def : KnightsLandingProc<"knl">;
 603
 604 def SKXFeatures : ProcessorFeatures<SKLFeatures.Value, [
 605   FeatureAVX512,
 606   FeatureCDI,
 607   FeatureDQI,
 608   FeatureBWI,
 609   FeatureVLX,
 610   FeaturePKU,
 611   FeatureCLWB
 612 ]>;
 613
 614 // FIXME: define SKX model
 615 class SkylakeServerProc<string Name> : ProcModel<Name, HaswellModel,
 616                                                  SKXFeatures.Value, []>;
 617 def : SkylakeServerProc<"skylake-avx512">;
 618 def : SkylakeServerProc<"skx">; // Legacy alias.
 619
 620 def CNLFeatures : ProcessorFeatures<SKXFeatures.Value, [
 621   FeatureVBMI,
 622   FeatureIFMA,
 623   FeatureSHA
 624 ]>;
 625
 626 class CannonlakeProc<string Name> : ProcModel<Name, HaswellModel,
 627                                               CNLFeatures.Value, []>;
 628 def : CannonlakeProc<"cannonlake">;
 629
 630 // AMD CPUs.
 631
 632 def : Proc<"k6",              [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 633 def : Proc<"k6-2",            [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 634 def : Proc<"k6-3",            [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 635 def : Proc<"athlon",          [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
 636                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 637 def : Proc<"athlon-tbird",    [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
 638                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 639 def : Proc<"athlon-4",        [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
 640                                Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
 641                                FeatureSlowSHLD]>;
 642 def : Proc<"athlon-xp",       [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
 643                                Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
 644                                FeatureSlowSHLD]>;
 645 def : Proc<"athlon-mp",       [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
 646                                Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
 647                                FeatureSlowSHLD]>;
 648 def : Proc<"k8",              [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 649                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 650                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 651 def : Proc<"opteron",         [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 652                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 653                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 654 def : Proc<"athlon64",        [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 655                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 656                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 657 def : Proc<"athlon-fx",       [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 658                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 659                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 660 def : Proc<"k8-sse3",         [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
 661                                Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
 662                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 663 def : Proc<"opteron-sse3",    [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
 664                                Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
 665                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 666 def : Proc<"athlon64-sse3",   [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
 667                                Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
 668                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 669 def : Proc<"amdfam10",        [FeatureX87, FeatureSSE4A, Feature3DNowA,
 670                                FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
 671                                FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD,
 672                                FeatureLAHFSAHF]>;
 673 def : Proc<"barcelona",       [FeatureX87, FeatureSSE4A, Feature3DNowA,
 674                                FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
 675                                FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD,
 676                                FeatureLAHFSAHF]>;
 677
 678 // Bobcat
 679 def : Proc<"btver1", [
 680   FeatureX87,
 681   FeatureMMX,
 682   FeatureSSSE3,
 683   FeatureSSE4A,
 684   FeatureFXSR,
 685   FeatureCMPXCHG16B,
 686   FeaturePRFCHW,
 687   FeatureLZCNT,
 688   FeaturePOPCNT,
 689   FeatureSlowSHLD,
 690   FeatureLAHFSAHF
 691 ]>;
 692
 693 // Jaguar
 694 def : ProcessorModel<"btver2", BtVer2Model, [
 695   FeatureX87,
 696   FeatureMMX,
 697   FeatureAVX,
 698   FeatureFXSR,
 699   FeatureSSE4A,
 700   FeatureCMPXCHG16B,
 701   FeaturePRFCHW,
 702   FeatureAES,
 703   FeaturePCLMUL,
 704   FeatureBMI,
 705   FeatureF16C,
 706   FeatureMOVBE,
 707   FeatureLZCNT,
 708   FeatureFastLZCNT,
 709   FeaturePOPCNT,
 710   FeatureXSAVE,
 711   FeatureXSAVEOPT,
 712   FeatureSlowSHLD,
 713   FeatureLAHFSAHF,
 714   FeatureFastPartialYMMorZMMWrite
 715 ]>;
 716
 717 // Bulldozer
 718 def : Proc<"bdver1", [
 719   FeatureX87,
 720   FeatureXOP,
 721   FeatureFMA4,
 722   FeatureCMPXCHG16B,
 723   FeatureAES,
 724   FeaturePRFCHW,
 725   FeaturePCLMUL,
 726   FeatureMMX,
 727   FeatureAVX,
 728   FeatureFXSR,
 729   FeatureSSE4A,
 730   FeatureLZCNT,
 731   FeaturePOPCNT,
 732   FeatureXSAVE,
 733   FeatureLWP,
 734   FeatureSlowSHLD,
 735   FeatureLAHFSAHF
 736 ]>;
 737 // Piledriver
 738 def : Proc<"bdver2", [
 739   FeatureX87,
 740   FeatureXOP,
 741   FeatureFMA4,
 742   FeatureCMPXCHG16B,
 743   FeatureAES,
 744   FeaturePRFCHW,
 745   FeaturePCLMUL,
 746   FeatureMMX,
 747   FeatureAVX,
 748   FeatureFXSR,
 749   FeatureSSE4A,
 750   FeatureF16C,
 751   FeatureLZCNT,
 752   FeaturePOPCNT,
 753   FeatureXSAVE,
 754   FeatureBMI,
 755   FeatureTBM,
 756   FeatureLWP,
 757   FeatureFMA,
 758   FeatureSlowSHLD,
 759   FeatureLAHFSAHF
 760 ]>;
 761
 762 // Steamroller
 763 def : Proc<"bdver3", [
 764   FeatureX87,
 765   FeatureXOP,
 766   FeatureFMA4,
 767   FeatureCMPXCHG16B,
 768   FeatureAES,
 769   FeaturePRFCHW,
 770   FeaturePCLMUL,
 771   FeatureMMX,
 772   FeatureAVX,
 773   FeatureFXSR,
 774   FeatureSSE4A,
 775   FeatureF16C,
 776   FeatureLZCNT,
 777   FeaturePOPCNT,
 778   FeatureXSAVE,
 779   FeatureBMI,
 780   FeatureTBM,
 781   FeatureLWP,
 782   FeatureFMA,
 783   FeatureXSAVEOPT,
 784   FeatureSlowSHLD,
 785   FeatureFSGSBase,
 786   FeatureLAHFSAHF
 787 ]>;
 788
 789 // Excavator
 790 def : Proc<"bdver4", [
 791   FeatureX87,
 792   FeatureMMX,
 793   FeatureAVX2,
 794   FeatureFXSR,
 795   FeatureXOP,
 796   FeatureFMA4,
 797   FeatureCMPXCHG16B,
 798   FeatureAES,
 799   FeaturePRFCHW,
 800   FeaturePCLMUL,
 801   FeatureF16C,
 802   FeatureLZCNT,
 803   FeaturePOPCNT,
 804   FeatureXSAVE,
 805   FeatureBMI,
 806   FeatureBMI2,
 807   FeatureTBM,
 808   FeatureLWP,
 809   FeatureFMA,
 810   FeatureXSAVEOPT,
 811   FeatureSlowSHLD,
 812   FeatureFSGSBase,
 813   FeatureLAHFSAHF,
 814   FeatureMWAITX
 815 ]>;
 816
 817 // Znver1
 818 def: ProcessorModel<"znver1", Znver1Model, [
 819   FeatureADX,
 820   FeatureAES,
 821   FeatureAVX2,
 822   FeatureBMI,
 823   FeatureBMI2,
 824   FeatureCLFLUSHOPT,
 825   FeatureCLZERO,
 826   FeatureCMPXCHG16B,
 827   FeatureF16C,
 828   FeatureFMA,
 829   FeatureFSGSBase,
 830   FeatureFXSR,
 831   FeatureFastLZCNT,
 832   FeatureLAHFSAHF,
 833   FeatureLZCNT,
 834   FeatureMMX,
 835   FeatureMOVBE,
 836   FeatureMWAITX,
 837   FeaturePCLMUL,
 838   FeaturePOPCNT,
 839   FeaturePRFCHW,
 840   FeatureRDRAND,
 841   FeatureRDSEED,
 842   FeatureSHA,
 843   FeatureSSE4A,
 844   FeatureSlowSHLD,
 845   FeatureX87,
 846   FeatureXSAVE,
 847   FeatureXSAVEC,
 848   FeatureXSAVEOPT,
 849   FeatureXSAVES]>;
 850
 851 def : Proc<"geode",           [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>;
 852
 853 def : Proc<"winchip-c6",      [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 854 def : Proc<"winchip2",        [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 855 def : Proc<"c3",              [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 856 def : Proc<"c3-2",            [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 857                                FeatureSSE1, FeatureFXSR]>;
 858
 859 // We also provide a generic 64-bit specific x86 processor model which tries to
 860 // be good for modern chips without enabling instruction set encodings past the
 861 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 862 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 863 //
 864 // We currently use the Sandy Bridge model as the default scheduling model as
 865 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 866 // covers a huge swath of x86 processors. If there are specific scheduling
 867 // knobs which need to be tuned differently for AMD chips, we might consider
 868 // forming a common base for them.
 869 def : ProcessorModel<"x86-64", SandyBridgeModel,
 870                      [FeatureX87, FeatureMMX, FeatureSSE2, FeatureFXSR,
 871                       Feature64Bit, FeatureSlowBTMem ]>;
 872
 873 //===----------------------------------------------------------------------===//
 874 // Register File Description
 875 //===----------------------------------------------------------------------===//
 876
 877 include "X86RegisterInfo.td"
 878 include "X86RegisterBanks.td"
 879
 880 //===----------------------------------------------------------------------===//
 881 // Instruction Descriptions
 882 //===----------------------------------------------------------------------===//
 883
 884 include "X86InstrInfo.td"
 885
 886 def X86InstrInfo : InstrInfo;
 887
 888 //===----------------------------------------------------------------------===//
 889 // Calling Conventions
 890 //===----------------------------------------------------------------------===//
 891
 892 include "X86CallingConv.td"
 893
 894
 895 //===----------------------------------------------------------------------===//
 896 // Assembly Parser
 897 //===----------------------------------------------------------------------===//
 898
 899 def ATTAsmParserVariant : AsmParserVariant {
 900   int Variant = 0;
 901
 902   // Variant name.
 903   string Name = "att";
 904
 905   // Discard comments in assembly strings.
 906   string CommentDelimiter = "#";
 907
 908   // Recognize hard coded registers.
 909   string RegisterPrefix = "%";
 910 }
 911
 912 def IntelAsmParserVariant : AsmParserVariant {
 913   int Variant = 1;
 914
 915   // Variant name.
 916   string Name = "intel";
 917
 918   // Discard comments in assembly strings.
 919   string CommentDelimiter = ";";
 920
 921   // Recognize hard coded registers.
 922   string RegisterPrefix = "";
 923 }
 924
 925 //===----------------------------------------------------------------------===//
 926 // Assembly Printers
 927 //===----------------------------------------------------------------------===//
 928
 929 // The X86 target supports two different syntaxes for emitting machine code.
 930 // This is controlled by the -x86-asm-syntax={att|intel}
 931 def ATTAsmWriter : AsmWriter {
 932   string AsmWriterClassName  = "ATTInstPrinter";
 933   int Variant = 0;
 934 }
 935 def IntelAsmWriter : AsmWriter {
 936   string AsmWriterClassName  = "IntelInstPrinter";
 937   int Variant = 1;
 938 }
 939
 940 def X86 : Target {
 941   // Information about the instructions...
 942   let InstructionSet = X86InstrInfo;
 943   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 944   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 945 }