contrib/llvm/lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureX87     : SubtargetFeature<"x87","HasX87", "true",
  35                                       "Enable X87 float instructions">;
  36
  37 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  38                                       "Enable conditional move instructions">;
  39
  40 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  41                                        "Support POPCNT instruction">;
  42
  43 def FeatureFXSR    : SubtargetFeature<"fxsr", "HasFXSR", "true",
  44                                       "Support fxsave/fxrestore instructions">;
  45
  46 def FeatureXSAVE   : SubtargetFeature<"xsave", "HasXSAVE", "true",
  47                                        "Support xsave instructions">;
  48
  49 def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
  50                                        "Support xsaveopt instructions">;
  51
  52 def FeatureXSAVEC  : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
  53                                        "Support xsavec instructions">;
  54
  55 def FeatureXSAVES  : SubtargetFeature<"xsaves", "HasXSAVES", "true",
  56                                        "Support xsaves instructions">;
  57
  58 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  59                                       "Enable SSE instructions",
  60                                       // SSE codegen depends on cmovs, and all
  61                                       // SSE1+ processors support them.
  62                                       [FeatureCMOV]>;
  63 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  64                                       "Enable SSE2 instructions",
  65                                       [FeatureSSE1]>;
  66 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  67                                       "Enable SSE3 instructions",
  68                                       [FeatureSSE2]>;
  69 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  70                                       "Enable SSSE3 instructions",
  71                                       [FeatureSSE3]>;
  72 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  73                                       "Enable SSE 4.1 instructions",
  74                                       [FeatureSSSE3]>;
  75 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  76                                       "Enable SSE 4.2 instructions",
  77                                       [FeatureSSE41]>;
  78 // The MMX subtarget feature is separate from the rest of the SSE features
  79 // because it's important (for odd compatibility reasons) to be able to
  80 // turn it off explicitly while allowing SSE+ to be on.
  81 def FeatureMMX     : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
  82                                       "Enable MMX instructions">;
  83 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  84                                       "Enable 3DNow! instructions",
  85                                       [FeatureMMX]>;
  86 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  87                                       "Enable 3DNow! Athlon instructions",
  88                                       [Feature3DNow]>;
  89 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  90 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  91 // without disabling 64-bit mode.
  92 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  93                                       "Support 64-bit instructions",
  94                                       [FeatureCMOV]>;
  95 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  96                                       "64-bit with cmpxchg16b",
  97                                       [Feature64Bit]>;
  98 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  99                                        "Bit testing of memory is slow">;
 100 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
 101                                        "SHLD instruction is slow">;
 102 def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
 103                                         "PMULLD instruction is slow">;
 104 // FIXME: This should not apply to CPUs that do not have SSE.
 105 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
 106                                 "IsUAMem16Slow", "true",
 107                                 "Slow unaligned 16-byte memory access">;
 108 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
 109                                 "IsUAMem32Slow", "true",
 110                                 "Slow unaligned 32-byte memory access">;
 111 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
 112                                       "Support SSE 4a instructions",
 113                                       [FeatureSSE3]>;
 114
 115 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
 116                                       "Enable AVX instructions",
 117                                       [FeatureSSE42]>;
 118 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 119                                       "Enable AVX2 instructions",
 120                                       [FeatureAVX]>;
 121 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 122                                       "Enable AVX-512 instructions",
 123                                       [FeatureAVX2]>;
 124 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 125                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 126                                       [FeatureAVX512]>;
 127 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 128                       "Enable AVX-512 Conflict Detection Instructions",
 129                                       [FeatureAVX512]>;
 130 def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ",
 131                        "true", "Enable AVX-512 Population Count Instructions",
 132                                       [FeatureAVX512]>;
 133 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 134                       "Enable AVX-512 PreFetch Instructions",
 135                                       [FeatureAVX512]>;
 136 def FeaturePREFETCHWT1  : SubtargetFeature<"prefetchwt1", "HasPFPREFETCHWT1",
 137                                    "true",
 138                                    "Prefetch with Intent to Write and T1 Hint">;
 139 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 140                       "Enable AVX-512 Doubleword and Quadword Instructions",
 141                                       [FeatureAVX512]>;
 142 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 143                       "Enable AVX-512 Byte and Word Instructions",
 144                                       [FeatureAVX512]>;
 145 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 146                       "Enable AVX-512 Vector Length eXtensions",
 147                                       [FeatureAVX512]>;
 148 def FeatureVBMI     : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
 149                       "Enable AVX-512 Vector Byte Manipulation Instructions",
 150                                       [FeatureBWI]>;
 151 def FeatureIFMA     : SubtargetFeature<"avx512ifma", "HasIFMA", "true",
 152                       "Enable AVX-512 Integer Fused Multiple-Add",
 153                                       [FeatureAVX512]>;
 154 def FeaturePKU   : SubtargetFeature<"pku", "HasPKU", "true",
 155                       "Enable protection keys">;
 156 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 157                          "Enable packed carry-less multiplication instructions",
 158                                [FeatureSSE2]>;
 159 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 160                                       "Enable three-operand fused multiple-add",
 161                                       [FeatureAVX]>;
 162 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 163                                       "Enable four-operand fused multiple-add",
 164                                       [FeatureAVX, FeatureSSE4A]>;
 165 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 166                                       "Enable XOP instructions",
 167                                       [FeatureFMA4]>;
 168 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 169                                           "HasSSEUnalignedMem", "true",
 170                       "Allow unaligned memory operands with SSE instructions">;
 171 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 172                                       "Enable AES instructions",
 173                                       [FeatureSSE2]>;
 174 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 175                                       "Enable TBM instructions">;
 176 def FeatureLWP     : SubtargetFeature<"lwp", "HasLWP", "true",
 177                                       "Enable LWP instructions">;
 178 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 179                                       "Support MOVBE instruction">;
 180 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 181                                       "Support RDRAND instruction">;
 182 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 183                        "Support 16-bit floating point conversion instructions",
 184                        [FeatureAVX]>;
 185 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 186                                        "Support FS/GS Base instructions">;
 187 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 188                                       "Support LZCNT instruction">;
 189 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 190                                       "Support BMI instructions">;
 191 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 192                                       "Support BMI2 instructions">;
 193 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 194                                       "Support RTM instructions">;
 195 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 196                                       "Support ADX instructions">;
 197 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 198                                       "Enable SHA instructions",
 199                                       [FeatureSSE2]>;
 200 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 201                                       "Support PRFCHW instructions">;
 202 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 203                                       "Support RDSEED instruction">;
 204 def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
 205                                        "Support LAHF and SAHF instructions">;
 206 def FeatureMWAITX  : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
 207                                       "Enable MONITORX/MWAITX timer functionality">;
 208 def FeatureCLZERO  : SubtargetFeature<"clzero", "HasCLZERO", "true",
 209                                       "Enable Cache Line Zero">;
 210 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
 211                                       "Support MPX instructions">;
 212 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 213                                      "Use LEA for adjusting the stack pointer">;
 214 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 215                                      "HasSlowDivide32", "true",
 216                                      "Use 8-bit divide for positive values less than 256">;
 217 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",
 218                                      "HasSlowDivide64", "true",
 219                                      "Use 32-bit divide for positive values less than 2^32">;
 220 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 221                                      "PadShortFunctions", "true",
 222                                      "Pad short functions">;
 223 def FeatureSGX     : SubtargetFeature<"sgx", "HasSGX", "true",
 224                                       "Enable Software Guard Extensions">;
 225 def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
 226                                       "Flush A Cache Line Optimized">;
 227 def FeatureCLWB    : SubtargetFeature<"clwb", "HasCLWB", "true",
 228                                       "Cache Line Write Back">;
 229 // TODO: This feature ought to be renamed.
 230 // What it really refers to are CPUs for which certain instructions
 231 // (which ones besides the example below?) are microcoded.
 232 // The best examples of this are the memory forms of CALL and PUSH
 233 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
 234 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 235                                      "CallRegIndirect", "true",
 236                                      "Call register indirect">;
 237 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 238                                    "LEA instruction needs inputs at AG stage">;
 239 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 240                                    "LEA instruction with certain arguments is slow">;
 241 def FeatureSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true",
 242                                    "LEA instruction with 3 ops or certain registers is slow">;
 243 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 244                                    "INC and DEC instructions are slower than ADD and SUB">;
 245 def FeatureSoftFloat
 246     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
 247                        "Use software floating point features.">;
 248 // On some X86 processors, there is no performance hazard to writing only the
 249 // lower parts of a YMM or ZMM register without clearing the upper part.
 250 def FeatureFastPartialYMMorZMMWrite
 251     : SubtargetFeature<"fast-partial-ymm-or-zmm-write",
 252                        "HasFastPartialYMMorZMMWrite",
 253                        "true", "Partial writes to YMM/ZMM registers are fast">;
 254 // FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
 255 // than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if
 256 // vector FSQRT has higher throughput than the corresponding NR code.
 257 // The idea is that throughput bound code is likely to be vectorized, so for
 258 // vectorized code we should care about the throughput of SQRT operations.
 259 // But if the code is scalar that probably means that the code has some kind of
 260 // dependency and we should care more about reducing the latency.
 261 def FeatureFastScalarFSQRT
 262     : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
 263                        "true", "Scalar SQRT is fast (disable Newton-Raphson)">;
 264 def FeatureFastVectorFSQRT
 265     : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
 266                        "true", "Vector SQRT is fast (disable Newton-Raphson)">;
 267 // If lzcnt has equivalent latency/throughput to most simple integer ops, it can
 268 // be used to replace test/set sequences.
 269 def FeatureFastLZCNT
 270     : SubtargetFeature<
 271           "fast-lzcnt", "HasFastLZCNT", "true",
 272           "LZCNT instructions are as fast as most simple integer ops">;
 273
 274
 275 // Sandy Bridge and newer processors can use SHLD with the same source on both
 276 // inputs to implement rotate to avoid the partial flag update of the normal
 277 // rotate instructions.
 278 def FeatureFastSHLDRotate
 279     : SubtargetFeature<
 280           "fast-shld-rotate", "HasFastSHLDRotate", "true",
 281           "SHLD can be used as a faster rotate">;
 282
 283 // Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
 284 // "string operations"). See "REP String Enhancement" in the Intel Software
 285 // Development Manual. This feature essentially means that REP MOVSB will copy
 286 // using the largest available size instead of copying bytes one by one, making
 287 // it at least as fast as REPMOVS{W,D,Q}.
 288 def FeatureERMSB
 289     : SubtargetFeature<
 290           "ermsb", "HasERMSB", "true",
 291           "REP MOVS/STOS are fast">;
 292
 293 //===----------------------------------------------------------------------===//
 294 // X86 processors supported.
 295 //===----------------------------------------------------------------------===//
 296
 297 include "X86Schedule.td"
 298
 299 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 300                     "Intel Atom processors">;
 301 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 302                     "Intel Silvermont processors">;
 303
 304 class Proc<string Name, list<SubtargetFeature> Features>
 305  : ProcessorModel<Name, GenericModel, Features>;
 306
 307 def : Proc<"generic",         [FeatureX87, FeatureSlowUAMem16]>;
 308 def : Proc<"i386",            [FeatureX87, FeatureSlowUAMem16]>;
 309 def : Proc<"i486",            [FeatureX87, FeatureSlowUAMem16]>;
 310 def : Proc<"i586",            [FeatureX87, FeatureSlowUAMem16]>;
 311 def : Proc<"pentium",         [FeatureX87, FeatureSlowUAMem16]>;
 312 def : Proc<"pentium-mmx",     [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 313 def : Proc<"i686",            [FeatureX87, FeatureSlowUAMem16]>;
 314 def : Proc<"pentiumpro",      [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
 315 def : Proc<"pentium2",        [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 316                                FeatureCMOV, FeatureFXSR]>;
 317 def : Proc<"pentium3",        [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 318                                FeatureSSE1, FeatureFXSR]>;
 319 def : Proc<"pentium3m",       [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 320                                FeatureSSE1, FeatureFXSR, FeatureSlowBTMem]>;
 321
 322 // Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
 323 // The intent is to enable it for pentium4 which is the current default
 324 // processor in a vanilla 32-bit clang compilation when no specific
 325 // architecture is specified.  This generally gives a nice performance
 326 // increase on silvermont, with largely neutral behavior on other
 327 // contemporary large core processors.
 328 // pentium-m, pentium4m, prescott and nocona are included as a preventative
 329 // measure to avoid performance surprises, in case clang's default cpu
 330 // changes slightly.
 331
 332 def : ProcessorModel<"pentium-m", GenericPostRAModel,
 333                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 334                       FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>;
 335
 336 def : ProcessorModel<"pentium4", GenericPostRAModel,
 337                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 338                       FeatureSSE2, FeatureFXSR]>;
 339
 340 def : ProcessorModel<"pentium4m", GenericPostRAModel,
 341                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 342                       FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>;
 343
 344 // Intel Quark.
 345 def : Proc<"lakemont",        []>;
 346
 347 // Intel Core Duo.
 348 def : ProcessorModel<"yonah", SandyBridgeModel,
 349                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
 350                       FeatureFXSR, FeatureSlowBTMem]>;
 351
 352 // NetBurst.
 353 def : ProcessorModel<"prescott", GenericPostRAModel,
 354                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
 355                       FeatureFXSR, FeatureSlowBTMem]>;
 356 def : ProcessorModel<"nocona", GenericPostRAModel, [
 357   FeatureX87,
 358   FeatureSlowUAMem16,
 359   FeatureMMX,
 360   FeatureSSE3,
 361   FeatureFXSR,
 362   FeatureCMPXCHG16B,
 363   FeatureSlowBTMem
 364 ]>;
 365
 366 // Intel Core 2 Solo/Duo.
 367 def : ProcessorModel<"core2", SandyBridgeModel, [
 368   FeatureX87,
 369   FeatureSlowUAMem16,
 370   FeatureMMX,
 371   FeatureSSSE3,
 372   FeatureFXSR,
 373   FeatureCMPXCHG16B,
 374   FeatureSlowBTMem,
 375   FeatureLAHFSAHF
 376 ]>;
 377 def : ProcessorModel<"penryn", SandyBridgeModel, [
 378   FeatureX87,
 379   FeatureSlowUAMem16,
 380   FeatureMMX,
 381   FeatureSSE41,
 382   FeatureFXSR,
 383   FeatureCMPXCHG16B,
 384   FeatureSlowBTMem,
 385   FeatureLAHFSAHF
 386 ]>;
 387
 388 // Atom CPUs.
 389 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 390   ProcIntelAtom,
 391   FeatureX87,
 392   FeatureSlowUAMem16,
 393   FeatureMMX,
 394   FeatureSSSE3,
 395   FeatureFXSR,
 396   FeatureCMPXCHG16B,
 397   FeatureMOVBE,
 398   FeatureSlowBTMem,
 399   FeatureLEAForSP,
 400   FeatureSlowDivide32,
 401   FeatureSlowDivide64,
 402   FeatureCallRegIndirect,
 403   FeatureLEAUsesAG,
 404   FeaturePadShortFunctions,
 405   FeatureLAHFSAHF
 406 ]>;
 407 def : BonnellProc<"bonnell">;
 408 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 409
 410 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 411   ProcIntelSLM,
 412   FeatureX87,
 413   FeatureMMX,
 414   FeatureSSE42,
 415   FeatureFXSR,
 416   FeatureCMPXCHG16B,
 417   FeatureMOVBE,
 418   FeaturePOPCNT,
 419   FeaturePCLMUL,
 420   FeatureAES,
 421   FeatureSlowDivide64,
 422   FeatureCallRegIndirect,
 423   FeaturePRFCHW,
 424   FeatureSlowLEA,
 425   FeatureSlowIncDec,
 426   FeatureSlowBTMem,
 427   FeatureSlowPMULLD,
 428   FeatureLAHFSAHF
 429 ]>;
 430 def : SilvermontProc<"silvermont">;
 431 def : SilvermontProc<"slm">; // Legacy alias.
 432
 433 // "Arrandale" along with corei3 and corei5
 434 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 435   FeatureX87,
 436   FeatureMMX,
 437   FeatureSSE42,
 438   FeatureFXSR,
 439   FeatureCMPXCHG16B,
 440   FeatureSlowBTMem,
 441   FeaturePOPCNT,
 442   FeatureLAHFSAHF
 443 ]>;
 444 def : NehalemProc<"nehalem">;
 445 def : NehalemProc<"corei7">;
 446
 447 // Westmere is a similar machine to nehalem with some additional features.
 448 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 449 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 450   FeatureX87,
 451   FeatureMMX,
 452   FeatureSSE42,
 453   FeatureFXSR,
 454   FeatureCMPXCHG16B,
 455   FeatureSlowBTMem,
 456   FeaturePOPCNT,
 457   FeatureAES,
 458   FeaturePCLMUL,
 459   FeatureLAHFSAHF
 460 ]>;
 461 def : WestmereProc<"westmere">;
 462
 463 class ProcessorFeatures<list<SubtargetFeature> Inherited,
 464                         list<SubtargetFeature> NewFeatures> {
 465   list<SubtargetFeature> Value = !listconcat(Inherited, NewFeatures);
 466 }
 467
 468 class ProcModel<string Name, SchedMachineModel Model,
 469                 list<SubtargetFeature> ProcFeatures,
 470                 list<SubtargetFeature> OtherFeatures> :
 471   ProcessorModel<Name, Model, !listconcat(ProcFeatures, OtherFeatures)>;
 472
 473 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 474 // rather than a superset.
 475 def SNBFeatures : ProcessorFeatures<[], [
 476   FeatureX87,
 477   FeatureMMX,
 478   FeatureAVX,
 479   FeatureFXSR,
 480   FeatureCMPXCHG16B,
 481   FeaturePOPCNT,
 482   FeatureAES,
 483   FeatureSlowDivide64,
 484   FeaturePCLMUL,
 485   FeatureXSAVE,
 486   FeatureXSAVEOPT,
 487   FeatureLAHFSAHF,
 488   FeatureSlow3OpsLEA,
 489   FeatureFastScalarFSQRT,
 490   FeatureFastSHLDRotate
 491 ]>;
 492
 493 class SandyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
 494                                                SNBFeatures.Value, [
 495   FeatureSlowBTMem,
 496   FeatureSlowUAMem32
 497 ]>;
 498 def : SandyBridgeProc<"sandybridge">;
 499 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 500
 501 def IVBFeatures : ProcessorFeatures<SNBFeatures.Value, [
 502   FeatureRDRAND,
 503   FeatureF16C,
 504   FeatureFSGSBase
 505 ]>;
 506
 507 class IvyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
 508                                              IVBFeatures.Value, [
 509   FeatureSlowBTMem,
 510   FeatureSlowUAMem32
 511 ]>;
 512 def : IvyBridgeProc<"ivybridge">;
 513 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 514
 515 def HSWFeatures : ProcessorFeatures<IVBFeatures.Value, [
 516   FeatureAVX2,
 517   FeatureBMI,
 518   FeatureBMI2,
 519   FeatureERMSB,
 520   FeatureFMA,
 521   FeatureLZCNT,
 522   FeatureMOVBE,
 523   FeatureSlowIncDec
 524 ]>;
 525
 526 class HaswellProc<string Name> : ProcModel<Name, HaswellModel,
 527                                            HSWFeatures.Value, []>;
 528 def : HaswellProc<"haswell">;
 529 def : HaswellProc<"core-avx2">; // Legacy alias.
 530
 531 def BDWFeatures : ProcessorFeatures<HSWFeatures.Value, [
 532   FeatureADX,
 533   FeatureRDSEED
 534 ]>;
 535 class BroadwellProc<string Name> : ProcModel<Name, HaswellModel,
 536                                              BDWFeatures.Value, []>;
 537 def : BroadwellProc<"broadwell">;
 538
 539 def SKLFeatures : ProcessorFeatures<BDWFeatures.Value, [
 540   FeatureMPX,
 541   FeatureRTM,
 542   FeatureXSAVEC,
 543   FeatureXSAVES,
 544   FeatureSGX,
 545   FeatureCLFLUSHOPT,
 546   FeatureFastVectorFSQRT
 547 ]>;
 548
 549 // FIXME: define SKL model
 550 class SkylakeClientProc<string Name> : ProcModel<Name, HaswellModel,
 551                                                  SKLFeatures.Value, []>;
 552 def : SkylakeClientProc<"skylake">;
 553
 554 // FIXME: define KNL model
 555 class KnightsLandingProc<string Name> : ProcModel<Name, HaswellModel,
 556                                                   IVBFeatures.Value, [
 557   FeatureAVX512,
 558   FeatureERI,
 559   FeatureCDI,
 560   FeaturePFI,
 561   FeaturePREFETCHWT1,
 562   FeatureADX,
 563   FeatureRDSEED,
 564   FeatureMOVBE,
 565   FeatureLZCNT,
 566   FeatureBMI,
 567   FeatureBMI2,
 568   FeatureFMA,
 569   FeatureFastPartialYMMorZMMWrite
 570 ]>;
 571 def : KnightsLandingProc<"knl">;
 572
 573 def SKXFeatures : ProcessorFeatures<SKLFeatures.Value, [
 574   FeatureAVX512,
 575   FeatureCDI,
 576   FeatureDQI,
 577   FeatureBWI,
 578   FeatureVLX,
 579   FeaturePKU,
 580   FeatureCLWB
 581 ]>;
 582
 583 // FIXME: define SKX model
 584 class SkylakeServerProc<string Name> : ProcModel<Name, HaswellModel,
 585                                                  SKXFeatures.Value, []>;
 586 def : SkylakeServerProc<"skylake-avx512">;
 587 def : SkylakeServerProc<"skx">; // Legacy alias.
 588
 589 def CNLFeatures : ProcessorFeatures<SKXFeatures.Value, [
 590   FeatureVBMI,
 591   FeatureIFMA,
 592   FeatureSHA
 593 ]>;
 594
 595 class CannonlakeProc<string Name> : ProcModel<Name, HaswellModel,
 596                                               CNLFeatures.Value, []>;
 597 def : CannonlakeProc<"cannonlake">;
 598
 599 // AMD CPUs.
 600
 601 def : Proc<"k6",              [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 602 def : Proc<"k6-2",            [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 603 def : Proc<"k6-3",            [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 604 def : Proc<"athlon",          [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
 605                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 606 def : Proc<"athlon-tbird",    [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
 607                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 608 def : Proc<"athlon-4",        [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
 609                                Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
 610                                FeatureSlowSHLD]>;
 611 def : Proc<"athlon-xp",       [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
 612                                Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
 613                                FeatureSlowSHLD]>;
 614 def : Proc<"athlon-mp",       [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
 615                                Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
 616                                FeatureSlowSHLD]>;
 617 def : Proc<"k8",              [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 618                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 619                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 620 def : Proc<"opteron",         [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 621                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 622                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 623 def : Proc<"athlon64",        [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 624                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 625                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 626 def : Proc<"athlon-fx",       [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 627                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 628                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 629 def : Proc<"k8-sse3",         [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
 630                                Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
 631                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 632 def : Proc<"opteron-sse3",    [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
 633                                Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
 634                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 635 def : Proc<"athlon64-sse3",   [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
 636                                Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
 637                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 638 def : Proc<"amdfam10",        [FeatureX87, FeatureSSE4A, Feature3DNowA,
 639                                FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
 640                                FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD,
 641                                FeatureLAHFSAHF]>;
 642 def : Proc<"barcelona",       [FeatureX87, FeatureSSE4A, Feature3DNowA,
 643                                FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
 644                                FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD,
 645                                FeatureLAHFSAHF]>;
 646
 647 // Bobcat
 648 def : Proc<"btver1", [
 649   FeatureX87,
 650   FeatureMMX,
 651   FeatureSSSE3,
 652   FeatureSSE4A,
 653   FeatureFXSR,
 654   FeatureCMPXCHG16B,
 655   FeaturePRFCHW,
 656   FeatureLZCNT,
 657   FeaturePOPCNT,
 658   FeatureSlowSHLD,
 659   FeatureLAHFSAHF
 660 ]>;
 661
 662 // Jaguar
 663 def : ProcessorModel<"btver2", BtVer2Model, [
 664   FeatureX87,
 665   FeatureMMX,
 666   FeatureAVX,
 667   FeatureFXSR,
 668   FeatureSSE4A,
 669   FeatureCMPXCHG16B,
 670   FeaturePRFCHW,
 671   FeatureAES,
 672   FeaturePCLMUL,
 673   FeatureBMI,
 674   FeatureF16C,
 675   FeatureMOVBE,
 676   FeatureLZCNT,
 677   FeatureFastLZCNT,
 678   FeaturePOPCNT,
 679   FeatureXSAVE,
 680   FeatureXSAVEOPT,
 681   FeatureSlowSHLD,
 682   FeatureLAHFSAHF,
 683   FeatureFastPartialYMMorZMMWrite
 684 ]>;
 685
 686 // Bulldozer
 687 def : Proc<"bdver1", [
 688   FeatureX87,
 689   FeatureXOP,
 690   FeatureFMA4,
 691   FeatureCMPXCHG16B,
 692   FeatureAES,
 693   FeaturePRFCHW,
 694   FeaturePCLMUL,
 695   FeatureMMX,
 696   FeatureAVX,
 697   FeatureFXSR,
 698   FeatureSSE4A,
 699   FeatureLZCNT,
 700   FeaturePOPCNT,
 701   FeatureXSAVE,
 702   FeatureLWP,
 703   FeatureSlowSHLD,
 704   FeatureLAHFSAHF
 705 ]>;
 706 // Piledriver
 707 def : Proc<"bdver2", [
 708   FeatureX87,
 709   FeatureXOP,
 710   FeatureFMA4,
 711   FeatureCMPXCHG16B,
 712   FeatureAES,
 713   FeaturePRFCHW,
 714   FeaturePCLMUL,
 715   FeatureMMX,
 716   FeatureAVX,
 717   FeatureFXSR,
 718   FeatureSSE4A,
 719   FeatureF16C,
 720   FeatureLZCNT,
 721   FeaturePOPCNT,
 722   FeatureXSAVE,
 723   FeatureBMI,
 724   FeatureTBM,
 725   FeatureLWP,
 726   FeatureFMA,
 727   FeatureSlowSHLD,
 728   FeatureLAHFSAHF
 729 ]>;
 730
 731 // Steamroller
 732 def : Proc<"bdver3", [
 733   FeatureX87,
 734   FeatureXOP,
 735   FeatureFMA4,
 736   FeatureCMPXCHG16B,
 737   FeatureAES,
 738   FeaturePRFCHW,
 739   FeaturePCLMUL,
 740   FeatureMMX,
 741   FeatureAVX,
 742   FeatureFXSR,
 743   FeatureSSE4A,
 744   FeatureF16C,
 745   FeatureLZCNT,
 746   FeaturePOPCNT,
 747   FeatureXSAVE,
 748   FeatureBMI,
 749   FeatureTBM,
 750   FeatureLWP,
 751   FeatureFMA,
 752   FeatureXSAVEOPT,
 753   FeatureSlowSHLD,
 754   FeatureFSGSBase,
 755   FeatureLAHFSAHF
 756 ]>;
 757
 758 // Excavator
 759 def : Proc<"bdver4", [
 760   FeatureX87,
 761   FeatureMMX,
 762   FeatureAVX2,
 763   FeatureFXSR,
 764   FeatureXOP,
 765   FeatureFMA4,
 766   FeatureCMPXCHG16B,
 767   FeatureAES,
 768   FeaturePRFCHW,
 769   FeaturePCLMUL,
 770   FeatureF16C,
 771   FeatureLZCNT,
 772   FeaturePOPCNT,
 773   FeatureXSAVE,
 774   FeatureBMI,
 775   FeatureBMI2,
 776   FeatureTBM,
 777   FeatureLWP,
 778   FeatureFMA,
 779   FeatureXSAVEOPT,
 780   FeatureSlowSHLD,
 781   FeatureFSGSBase,
 782   FeatureLAHFSAHF,
 783   FeatureMWAITX
 784 ]>;
 785
 786 // TODO: The scheduler model falls to BTVER2 model.
 787 // The znver1 model has to be put in place.
 788 // Zen
 789 def: ProcessorModel<"znver1", BtVer2Model, [
 790   FeatureADX,
 791   FeatureAES,
 792   FeatureAVX2,
 793   FeatureBMI,
 794   FeatureBMI2,
 795   FeatureCLFLUSHOPT,
 796   FeatureCLZERO,
 797   FeatureCMPXCHG16B,
 798   FeatureF16C,
 799   FeatureFMA,
 800   FeatureFSGSBase,
 801   FeatureFXSR,
 802   FeatureFastLZCNT,
 803   FeatureLAHFSAHF,
 804   FeatureLZCNT,
 805   FeatureMMX,
 806   FeatureMOVBE,
 807   FeatureMWAITX,
 808   FeaturePCLMUL,
 809   FeaturePOPCNT,
 810   FeaturePRFCHW,
 811   FeatureRDRAND,
 812   FeatureRDSEED,
 813   FeatureSHA,
 814   FeatureSSE4A,
 815   FeatureSlowSHLD,
 816   FeatureX87,
 817   FeatureXSAVE,
 818   FeatureXSAVEC,
 819   FeatureXSAVEOPT,
 820   FeatureXSAVES]>;
 821
 822 def : Proc<"geode",           [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>;
 823
 824 def : Proc<"winchip-c6",      [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 825 def : Proc<"winchip2",        [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 826 def : Proc<"c3",              [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 827 def : Proc<"c3-2",            [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 828                                FeatureSSE1, FeatureFXSR]>;
 829
 830 // We also provide a generic 64-bit specific x86 processor model which tries to
 831 // be good for modern chips without enabling instruction set encodings past the
 832 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 833 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 834 //
 835 // We currently use the Sandy Bridge model as the default scheduling model as
 836 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 837 // covers a huge swath of x86 processors. If there are specific scheduling
 838 // knobs which need to be tuned differently for AMD chips, we might consider
 839 // forming a common base for them.
 840 def : ProcessorModel<"x86-64", SandyBridgeModel,
 841                      [FeatureX87, FeatureMMX, FeatureSSE2, FeatureFXSR,
 842                       Feature64Bit, FeatureSlowBTMem ]>;
 843
 844 //===----------------------------------------------------------------------===//
 845 // Register File Description
 846 //===----------------------------------------------------------------------===//
 847
 848 include "X86RegisterInfo.td"
 849 include "X86RegisterBanks.td"
 850
 851 //===----------------------------------------------------------------------===//
 852 // Instruction Descriptions
 853 //===----------------------------------------------------------------------===//
 854
 855 include "X86InstrInfo.td"
 856
 857 def X86InstrInfo : InstrInfo;
 858
 859 //===----------------------------------------------------------------------===//
 860 // Calling Conventions
 861 //===----------------------------------------------------------------------===//
 862
 863 include "X86CallingConv.td"
 864
 865
 866 //===----------------------------------------------------------------------===//
 867 // Assembly Parser
 868 //===----------------------------------------------------------------------===//
 869
 870 def ATTAsmParserVariant : AsmParserVariant {
 871   int Variant = 0;
 872
 873   // Variant name.
 874   string Name = "att";
 875
 876   // Discard comments in assembly strings.
 877   string CommentDelimiter = "#";
 878
 879   // Recognize hard coded registers.
 880   string RegisterPrefix = "%";
 881 }
 882
 883 def IntelAsmParserVariant : AsmParserVariant {
 884   int Variant = 1;
 885
 886   // Variant name.
 887   string Name = "intel";
 888
 889   // Discard comments in assembly strings.
 890   string CommentDelimiter = ";";
 891
 892   // Recognize hard coded registers.
 893   string RegisterPrefix = "";
 894 }
 895
 896 //===----------------------------------------------------------------------===//
 897 // Assembly Printers
 898 //===----------------------------------------------------------------------===//
 899
 900 // The X86 target supports two different syntaxes for emitting machine code.
 901 // This is controlled by the -x86-asm-syntax={att|intel}
 902 def ATTAsmWriter : AsmWriter {
 903   string AsmWriterClassName  = "ATTInstPrinter";
 904   int Variant = 0;
 905 }
 906 def IntelAsmWriter : AsmWriter {
 907   string AsmWriterClassName  = "IntelInstPrinter";
 908   int Variant = 1;
 909 }
 910
 911 def X86 : Target {
 912   // Information about the instructions...
 913   let InstructionSet = X86InstrInfo;
 914   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 915   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 916 }