contrib/llvm/lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureX87     : SubtargetFeature<"x87","HasX87", "true",
  35                                       "Enable X87 float instructions">;
  36
  37 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  38                                       "Enable conditional move instructions">;
  39
  40 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  41                                        "Support POPCNT instruction">;
  42
  43 def FeatureFXSR    : SubtargetFeature<"fxsr", "HasFXSR", "true",
  44                                       "Support fxsave/fxrestore instructions">;
  45
  46 def FeatureXSAVE   : SubtargetFeature<"xsave", "HasXSAVE", "true",
  47                                        "Support xsave instructions">;
  48
  49 def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
  50                                        "Support xsaveopt instructions">;
  51
  52 def FeatureXSAVEC  : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
  53                                        "Support xsavec instructions">;
  54
  55 def FeatureXSAVES  : SubtargetFeature<"xsaves", "HasXSAVES", "true",
  56                                        "Support xsaves instructions">;
  57
  58 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  59                                       "Enable SSE instructions",
  60                                       // SSE codegen depends on cmovs, and all
  61                                       // SSE1+ processors support them.
  62                                       [FeatureCMOV]>;
  63 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  64                                       "Enable SSE2 instructions",
  65                                       [FeatureSSE1]>;
  66 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  67                                       "Enable SSE3 instructions",
  68                                       [FeatureSSE2]>;
  69 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  70                                       "Enable SSSE3 instructions",
  71                                       [FeatureSSE3]>;
  72 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  73                                       "Enable SSE 4.1 instructions",
  74                                       [FeatureSSSE3]>;
  75 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  76                                       "Enable SSE 4.2 instructions",
  77                                       [FeatureSSE41]>;
  78 // The MMX subtarget feature is separate from the rest of the SSE features
  79 // because it's important (for odd compatibility reasons) to be able to
  80 // turn it off explicitly while allowing SSE+ to be on.
  81 def FeatureMMX     : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
  82                                       "Enable MMX instructions">;
  83 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  84                                       "Enable 3DNow! instructions",
  85                                       [FeatureMMX]>;
  86 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  87                                       "Enable 3DNow! Athlon instructions",
  88                                       [Feature3DNow]>;
  89 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  90 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  91 // without disabling 64-bit mode.
  92 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  93                                       "Support 64-bit instructions",
  94                                       [FeatureCMOV]>;
  95 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  96                                       "64-bit with cmpxchg16b",
  97                                       [Feature64Bit]>;
  98 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  99                                        "Bit testing of memory is slow">;
 100 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
 101                                        "SHLD instruction is slow">;
 102 def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
 103                                         "PMULLD instruction is slow">;
 104 // FIXME: This should not apply to CPUs that do not have SSE.
 105 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
 106                                 "IsUAMem16Slow", "true",
 107                                 "Slow unaligned 16-byte memory access">;
 108 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
 109                                 "IsUAMem32Slow", "true",
 110                                 "Slow unaligned 32-byte memory access">;
 111 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
 112                                       "Support SSE 4a instructions",
 113                                       [FeatureSSE3]>;
 114
 115 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
 116                                       "Enable AVX instructions",
 117                                       [FeatureSSE42]>;
 118 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 119                                       "Enable AVX2 instructions",
 120                                       [FeatureAVX]>;
 121 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 122                                       "Enable AVX-512 instructions",
 123                                       [FeatureAVX2]>;
 124 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 125                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 126                                       [FeatureAVX512]>;
 127 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 128                       "Enable AVX-512 Conflict Detection Instructions",
 129                                       [FeatureAVX512]>;
 130 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 131                       "Enable AVX-512 PreFetch Instructions",
 132                                       [FeatureAVX512]>;
 133 def FeaturePREFETCHWT1  : SubtargetFeature<"prefetchwt1", "HasPFPREFETCHWT1",
 134                                    "true",
 135                                    "Prefetch with Intent to Write and T1 Hint">;
 136 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 137                       "Enable AVX-512 Doubleword and Quadword Instructions",
 138                                       [FeatureAVX512]>;
 139 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 140                       "Enable AVX-512 Byte and Word Instructions",
 141                                       [FeatureAVX512]>;
 142 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 143                       "Enable AVX-512 Vector Length eXtensions",
 144                                       [FeatureAVX512]>;
 145 def FeatureVBMI     : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
 146                       "Enable AVX-512 Vector Byte Manipulation Instructions",
 147                                       [FeatureBWI]>;
 148 def FeatureIFMA     : SubtargetFeature<"avx512ifma", "HasIFMA", "true",
 149                       "Enable AVX-512 Integer Fused Multiple-Add",
 150                                       [FeatureAVX512]>;
 151 def FeaturePKU   : SubtargetFeature<"pku", "HasPKU", "true",
 152                       "Enable protection keys">;
 153 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 154                          "Enable packed carry-less multiplication instructions",
 155                                [FeatureSSE2]>;
 156 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 157                                       "Enable three-operand fused multiple-add",
 158                                       [FeatureAVX]>;
 159 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 160                                       "Enable four-operand fused multiple-add",
 161                                       [FeatureAVX, FeatureSSE4A]>;
 162 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 163                                       "Enable XOP instructions",
 164                                       [FeatureFMA4]>;
 165 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 166                                           "HasSSEUnalignedMem", "true",
 167                       "Allow unaligned memory operands with SSE instructions">;
 168 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 169                                       "Enable AES instructions",
 170                                       [FeatureSSE2]>;
 171 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 172                                       "Enable TBM instructions">;
 173 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 174                                       "Support MOVBE instruction">;
 175 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 176                                       "Support RDRAND instruction">;
 177 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 178                        "Support 16-bit floating point conversion instructions",
 179                        [FeatureAVX]>;
 180 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 181                                        "Support FS/GS Base instructions">;
 182 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 183                                       "Support LZCNT instruction">;
 184 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 185                                       "Support BMI instructions">;
 186 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 187                                       "Support BMI2 instructions">;
 188 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 189                                       "Support RTM instructions">;
 190 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
 191                                       "Support HLE">;
 192 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 193                                       "Support ADX instructions">;
 194 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 195                                       "Enable SHA instructions",
 196                                       [FeatureSSE2]>;
 197 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 198                                       "Support PRFCHW instructions">;
 199 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 200                                       "Support RDSEED instruction">;
 201 def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
 202                                        "Support LAHF and SAHF instructions">;
 203 def FeatureMWAITX  : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
 204                                       "Enable MONITORX/MWAITX timer functionality">;
 205 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
 206                                       "Support MPX instructions">;
 207 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 208                                      "Use LEA for adjusting the stack pointer">;
 209 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 210                                      "HasSlowDivide32", "true",
 211                                      "Use 8-bit divide for positive values less than 256">;
 212 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
 213                                      "HasSlowDivide64", "true",
 214                                      "Use 16-bit divide for positive values less than 65536">;
 215 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 216                                      "PadShortFunctions", "true",
 217                                      "Pad short functions">;
 218 def FeatureINVPCID : SubtargetFeature<"invpcid", "HasInvPCId", "true",
 219                                       "Invalidate Process-Context Identifier">;
 220 def FeatureVMFUNC  : SubtargetFeature<"vmfunc", "HasVMFUNC", "true",
 221                                       "VM Functions">;
 222 def FeatureSMAP    : SubtargetFeature<"smap", "HasSMAP", "true",
 223                                       "Supervisor Mode Access Protection">;
 224 def FeatureSGX     : SubtargetFeature<"sgx", "HasSGX", "true",
 225                                       "Enable Software Guard Extensions">;
 226 def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
 227                                       "Flush A Cache Line Optimized">;
 228 def FeaturePCOMMIT : SubtargetFeature<"pcommit", "HasPCOMMIT", "true",
 229                                       "Enable Persistent Commit">;
 230 def FeatureCLWB    : SubtargetFeature<"clwb", "HasCLWB", "true",
 231                                       "Cache Line Write Back">;
 232 // TODO: This feature ought to be renamed.
 233 // What it really refers to are CPUs for which certain instructions
 234 // (which ones besides the example below?) are microcoded.
 235 // The best examples of this are the memory forms of CALL and PUSH
 236 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
 237 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 238                                      "CallRegIndirect", "true",
 239                                      "Call register indirect">;
 240 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 241                                    "LEA instruction needs inputs at AG stage">;
 242 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 243                                    "LEA instruction with certain arguments is slow">;
 244 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 245                                    "INC and DEC instructions are slower than ADD and SUB">;
 246 def FeatureSoftFloat
 247     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
 248                        "Use software floating point features.">;
 249 // On at least some AMD processors, there is no performance hazard to writing
 250 // only the lower parts of a YMM register without clearing the upper part.
 251 def FeatureFastPartialYMMWrite
 252     : SubtargetFeature<"fast-partial-ymm-write", "HasFastPartialYMMWrite",
 253                        "true", "Partial writes to YMM registers are fast">;
 254 // FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
 255 // than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if
 256 // vector FSQRT has higher throughput than the corresponding NR code.
 257 // The idea is that throughput bound code is likely to be vectorized, so for
 258 // vectorized code we should care about the throughput of SQRT operations.
 259 // But if the code is scalar that probably means that the code has some kind of
 260 // dependency and we should care more about reducing the latency.
 261 def FeatureFastScalarFSQRT
 262     : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
 263                        "true", "Scalar SQRT is fast (disable Newton-Raphson)">;
 264 def FeatureFastVectorFSQRT
 265     : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
 266                        "true", "Vector SQRT is fast (disable Newton-Raphson)">;
 267 // If lzcnt has equivalent latency/throughput to most simple integer ops, it can
 268 // be used to replace test/set sequences.
 269 def FeatureFastLZCNT
 270     : SubtargetFeature<
 271           "fast-lzcnt", "HasFastLZCNT", "true",
 272           "LZCNT instructions are as fast as most simple integer ops">;
 273
 274 //===----------------------------------------------------------------------===//
 275 // X86 processors supported.
 276 //===----------------------------------------------------------------------===//
 277
 278 include "X86Schedule.td"
 279
 280 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 281                     "Intel Atom processors">;
 282 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 283                     "Intel Silvermont processors">;
 284
 285 class Proc<string Name, list<SubtargetFeature> Features>
 286  : ProcessorModel<Name, GenericModel, Features>;
 287
 288 def : Proc<"generic",         [FeatureX87, FeatureSlowUAMem16]>;
 289 def : Proc<"i386",            [FeatureX87, FeatureSlowUAMem16]>;
 290 def : Proc<"i486",            [FeatureX87, FeatureSlowUAMem16]>;
 291 def : Proc<"i586",            [FeatureX87, FeatureSlowUAMem16]>;
 292 def : Proc<"pentium",         [FeatureX87, FeatureSlowUAMem16]>;
 293 def : Proc<"pentium-mmx",     [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 294 def : Proc<"i686",            [FeatureX87, FeatureSlowUAMem16]>;
 295 def : Proc<"pentiumpro",      [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
 296 def : Proc<"pentium2",        [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 297                                FeatureCMOV, FeatureFXSR]>;
 298 def : Proc<"pentium3",        [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 299                                FeatureSSE1, FeatureFXSR]>;
 300 def : Proc<"pentium3m",       [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 301                                FeatureSSE1, FeatureFXSR, FeatureSlowBTMem]>;
 302
 303 // Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
 304 // The intent is to enable it for pentium4 which is the current default
 305 // processor in a vanilla 32-bit clang compilation when no specific
 306 // architecture is specified.  This generally gives a nice performance
 307 // increase on silvermont, with largely neutral behavior on other
 308 // contemporary large core processors.
 309 // pentium-m, pentium4m, prescott and nocona are included as a preventative
 310 // measure to avoid performance surprises, in case clang's default cpu
 311 // changes slightly.
 312
 313 def : ProcessorModel<"pentium-m", GenericPostRAModel,
 314                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 315                       FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>;
 316
 317 def : ProcessorModel<"pentium4", GenericPostRAModel,
 318                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 319                       FeatureSSE2, FeatureFXSR]>;
 320
 321 def : ProcessorModel<"pentium4m", GenericPostRAModel,
 322                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 323                       FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>;
 324
 325 // Intel Quark.
 326 def : Proc<"lakemont",        []>;
 327
 328 // Intel Core Duo.
 329 def : ProcessorModel<"yonah", SandyBridgeModel,
 330                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
 331                       FeatureFXSR, FeatureSlowBTMem]>;
 332
 333 // NetBurst.
 334 def : ProcessorModel<"prescott", GenericPostRAModel,
 335                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
 336                       FeatureFXSR, FeatureSlowBTMem]>;
 337 def : ProcessorModel<"nocona", GenericPostRAModel, [
 338   FeatureX87,
 339   FeatureSlowUAMem16,
 340   FeatureMMX,
 341   FeatureSSE3,
 342   FeatureFXSR,
 343   FeatureCMPXCHG16B,
 344   FeatureSlowBTMem
 345 ]>;
 346
 347 // Intel Core 2 Solo/Duo.
 348 def : ProcessorModel<"core2", SandyBridgeModel, [
 349   FeatureX87,
 350   FeatureSlowUAMem16,
 351   FeatureMMX,
 352   FeatureSSSE3,
 353   FeatureFXSR,
 354   FeatureCMPXCHG16B,
 355   FeatureSlowBTMem,
 356   FeatureLAHFSAHF
 357 ]>;
 358 def : ProcessorModel<"penryn", SandyBridgeModel, [
 359   FeatureX87,
 360   FeatureSlowUAMem16,
 361   FeatureMMX,
 362   FeatureSSE41,
 363   FeatureFXSR,
 364   FeatureCMPXCHG16B,
 365   FeatureSlowBTMem,
 366   FeatureLAHFSAHF
 367 ]>;
 368
 369 // Atom CPUs.
 370 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 371   ProcIntelAtom,
 372   FeatureX87,
 373   FeatureSlowUAMem16,
 374   FeatureMMX,
 375   FeatureSSSE3,
 376   FeatureFXSR,
 377   FeatureCMPXCHG16B,
 378   FeatureMOVBE,
 379   FeatureSlowBTMem,
 380   FeatureLEAForSP,
 381   FeatureSlowDivide32,
 382   FeatureSlowDivide64,
 383   FeatureCallRegIndirect,
 384   FeatureLEAUsesAG,
 385   FeaturePadShortFunctions,
 386   FeatureLAHFSAHF
 387 ]>;
 388 def : BonnellProc<"bonnell">;
 389 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 390
 391 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 392   ProcIntelSLM,
 393   FeatureX87,
 394   FeatureMMX,
 395   FeatureSSE42,
 396   FeatureFXSR,
 397   FeatureCMPXCHG16B,
 398   FeatureMOVBE,
 399   FeaturePOPCNT,
 400   FeaturePCLMUL,
 401   FeatureAES,
 402   FeatureSlowDivide64,
 403   FeatureCallRegIndirect,
 404   FeaturePRFCHW,
 405   FeatureSlowLEA,
 406   FeatureSlowIncDec,
 407   FeatureSlowBTMem,
 408   FeatureSlowPMULLD,
 409   FeatureLAHFSAHF
 410 ]>;
 411 def : SilvermontProc<"silvermont">;
 412 def : SilvermontProc<"slm">; // Legacy alias.
 413
 414 // "Arrandale" along with corei3 and corei5
 415 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 416   FeatureX87,
 417   FeatureMMX,
 418   FeatureSSE42,
 419   FeatureFXSR,
 420   FeatureCMPXCHG16B,
 421   FeatureSlowBTMem,
 422   FeaturePOPCNT,
 423   FeatureLAHFSAHF
 424 ]>;
 425 def : NehalemProc<"nehalem">;
 426 def : NehalemProc<"corei7">;
 427
 428 // Westmere is a similar machine to nehalem with some additional features.
 429 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 430 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 431   FeatureX87,
 432   FeatureMMX,
 433   FeatureSSE42,
 434   FeatureFXSR,
 435   FeatureCMPXCHG16B,
 436   FeatureSlowBTMem,
 437   FeaturePOPCNT,
 438   FeatureAES,
 439   FeaturePCLMUL,
 440   FeatureLAHFSAHF
 441 ]>;
 442 def : WestmereProc<"westmere">;
 443
 444 class ProcessorFeatures<list<SubtargetFeature> Inherited,
 445                         list<SubtargetFeature> NewFeatures> {
 446   list<SubtargetFeature> Value = !listconcat(Inherited, NewFeatures);
 447 }
 448
 449 class ProcModel<string Name, SchedMachineModel Model,
 450                 list<SubtargetFeature> ProcFeatures,
 451                 list<SubtargetFeature> OtherFeatures> :
 452   ProcessorModel<Name, Model, !listconcat(ProcFeatures, OtherFeatures)>;
 453
 454 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 455 // rather than a superset.
 456 def SNBFeatures : ProcessorFeatures<[], [
 457   FeatureX87,
 458   FeatureMMX,
 459   FeatureAVX,
 460   FeatureFXSR,
 461   FeatureCMPXCHG16B,
 462   FeaturePOPCNT,
 463   FeatureAES,
 464   FeaturePCLMUL,
 465   FeatureXSAVE,
 466   FeatureXSAVEOPT,
 467   FeatureLAHFSAHF,
 468   FeatureFastScalarFSQRT
 469 ]>;
 470
 471 class SandyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
 472                                                SNBFeatures.Value, [
 473   FeatureSlowBTMem,
 474   FeatureSlowUAMem32
 475 ]>;
 476 def : SandyBridgeProc<"sandybridge">;
 477 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 478
 479 def IVBFeatures : ProcessorFeatures<SNBFeatures.Value, [
 480   FeatureRDRAND,
 481   FeatureF16C,
 482   FeatureFSGSBase
 483 ]>;
 484
 485 class IvyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
 486                                              IVBFeatures.Value, [
 487   FeatureSlowBTMem,
 488   FeatureSlowUAMem32
 489 ]>;
 490 def : IvyBridgeProc<"ivybridge">;
 491 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 492
 493 def HSWFeatures : ProcessorFeatures<IVBFeatures.Value, [
 494   FeatureAVX2,
 495   FeatureBMI,
 496   FeatureBMI2,
 497   FeatureFMA,
 498   FeatureLZCNT,
 499   FeatureMOVBE,
 500   FeatureINVPCID,
 501   FeatureVMFUNC,
 502   FeatureRTM,
 503   FeatureHLE,
 504   FeatureSlowIncDec
 505 ]>;
 506
 507 class HaswellProc<string Name> : ProcModel<Name, HaswellModel,
 508                                            HSWFeatures.Value, []>;
 509 def : HaswellProc<"haswell">;
 510 def : HaswellProc<"core-avx2">; // Legacy alias.
 511
 512 def BDWFeatures : ProcessorFeatures<HSWFeatures.Value, [
 513   FeatureADX,
 514   FeatureRDSEED,
 515   FeatureSMAP
 516 ]>;
 517 class BroadwellProc<string Name> : ProcModel<Name, HaswellModel,
 518                                              BDWFeatures.Value, []>;
 519 def : BroadwellProc<"broadwell">;
 520
 521 def SKLFeatures : ProcessorFeatures<BDWFeatures.Value, [
 522   FeatureMPX,
 523   FeatureXSAVEC,
 524   FeatureXSAVES,
 525   FeatureSGX,
 526   FeatureCLFLUSHOPT,
 527   FeatureFastVectorFSQRT
 528 ]>;
 529
 530 // FIXME: define SKL model
 531 class SkylakeClientProc<string Name> : ProcModel<Name, HaswellModel,
 532                                                  SKLFeatures.Value, []>;
 533 def : SkylakeClientProc<"skylake">;
 534
 535 // FIXME: define KNL model
 536 class KnightsLandingProc<string Name> : ProcModel<Name, HaswellModel,
 537                                                   IVBFeatures.Value, [
 538   FeatureAVX512,
 539   FeatureERI,
 540   FeatureCDI,
 541   FeaturePFI,
 542   FeaturePREFETCHWT1,
 543   FeatureADX,
 544   FeatureRDSEED,
 545   FeatureMOVBE,
 546   FeatureLZCNT,
 547   FeatureBMI,
 548   FeatureBMI2,
 549   FeatureFMA
 550 ]>;
 551 def : KnightsLandingProc<"knl">;
 552
 553 def SKXFeatures : ProcessorFeatures<SKLFeatures.Value, [
 554   FeatureAVX512,
 555   FeatureCDI,
 556   FeatureDQI,
 557   FeatureBWI,
 558   FeatureVLX,
 559   FeaturePKU,
 560   FeaturePCOMMIT,
 561   FeatureCLWB
 562 ]>;
 563
 564 // FIXME: define SKX model
 565 class SkylakeServerProc<string Name> : ProcModel<Name, HaswellModel,
 566                                                  SKXFeatures.Value, []>;
 567 def : SkylakeServerProc<"skylake-avx512">;
 568 def : SkylakeServerProc<"skx">; // Legacy alias.
 569
 570 def CNLFeatures : ProcessorFeatures<SKXFeatures.Value, [
 571   FeatureVBMI,
 572   FeatureIFMA,
 573   FeatureSHA
 574 ]>;
 575
 576 class CannonlakeProc<string Name> : ProcModel<Name, HaswellModel,
 577                                               CNLFeatures.Value, []>;
 578 def : CannonlakeProc<"cannonlake">;
 579
 580 // AMD CPUs.
 581
 582 def : Proc<"k6",              [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 583 def : Proc<"k6-2",            [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 584 def : Proc<"k6-3",            [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 585 def : Proc<"athlon",          [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
 586                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 587 def : Proc<"athlon-tbird",    [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
 588                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 589 def : Proc<"athlon-4",        [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
 590                                Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
 591                                FeatureSlowSHLD]>;
 592 def : Proc<"athlon-xp",       [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
 593                                Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
 594                                FeatureSlowSHLD]>;
 595 def : Proc<"athlon-mp",       [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
 596                                Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
 597                                FeatureSlowSHLD]>;
 598 def : Proc<"k8",              [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 599                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 600                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 601 def : Proc<"opteron",         [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 602                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 603                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 604 def : Proc<"athlon64",        [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 605                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 606                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 607 def : Proc<"athlon-fx",       [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 608                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 609                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 610 def : Proc<"k8-sse3",         [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
 611                                Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
 612                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 613 def : Proc<"opteron-sse3",    [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
 614                                Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
 615                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 616 def : Proc<"athlon64-sse3",   [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
 617                                Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
 618                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 619 def : Proc<"amdfam10",        [FeatureX87, FeatureSSE4A, Feature3DNowA,
 620                                FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
 621                                FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD,
 622                                FeatureLAHFSAHF]>;
 623 def : Proc<"barcelona",       [FeatureX87, FeatureSSE4A, Feature3DNowA,
 624                                FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
 625                                FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD,
 626                                FeatureLAHFSAHF]>;
 627
 628 // Bobcat
 629 def : Proc<"btver1", [
 630   FeatureX87,
 631   FeatureMMX,
 632   FeatureSSSE3,
 633   FeatureSSE4A,
 634   FeatureFXSR,
 635   FeatureCMPXCHG16B,
 636   FeaturePRFCHW,
 637   FeatureLZCNT,
 638   FeaturePOPCNT,
 639   FeatureSlowSHLD,
 640   FeatureLAHFSAHF
 641 ]>;
 642
 643 // Jaguar
 644 def : ProcessorModel<"btver2", BtVer2Model, [
 645   FeatureX87,
 646   FeatureMMX,
 647   FeatureAVX,
 648   FeatureFXSR,
 649   FeatureSSE4A,
 650   FeatureCMPXCHG16B,
 651   FeaturePRFCHW,
 652   FeatureAES,
 653   FeaturePCLMUL,
 654   FeatureBMI,
 655   FeatureF16C,
 656   FeatureMOVBE,
 657   FeatureLZCNT,
 658   FeatureFastLZCNT,
 659   FeaturePOPCNT,
 660   FeatureXSAVE,
 661   FeatureXSAVEOPT,
 662   FeatureSlowSHLD,
 663   FeatureLAHFSAHF,
 664   FeatureFastPartialYMMWrite
 665 ]>;
 666
 667 // Bulldozer
 668 def : Proc<"bdver1", [
 669   FeatureX87,
 670   FeatureXOP,
 671   FeatureFMA4,
 672   FeatureCMPXCHG16B,
 673   FeatureAES,
 674   FeaturePRFCHW,
 675   FeaturePCLMUL,
 676   FeatureMMX,
 677   FeatureAVX,
 678   FeatureFXSR,
 679   FeatureSSE4A,
 680   FeatureLZCNT,
 681   FeaturePOPCNT,
 682   FeatureXSAVE,
 683   FeatureSlowSHLD,
 684   FeatureLAHFSAHF
 685 ]>;
 686 // Piledriver
 687 def : Proc<"bdver2", [
 688   FeatureX87,
 689   FeatureXOP,
 690   FeatureFMA4,
 691   FeatureCMPXCHG16B,
 692   FeatureAES,
 693   FeaturePRFCHW,
 694   FeaturePCLMUL,
 695   FeatureMMX,
 696   FeatureAVX,
 697   FeatureFXSR,
 698   FeatureSSE4A,
 699   FeatureF16C,
 700   FeatureLZCNT,
 701   FeaturePOPCNT,
 702   FeatureXSAVE,
 703   FeatureBMI,
 704   FeatureTBM,
 705   FeatureFMA,
 706   FeatureSlowSHLD,
 707   FeatureLAHFSAHF
 708 ]>;
 709
 710 // Steamroller
 711 def : Proc<"bdver3", [
 712   FeatureX87,
 713   FeatureXOP,
 714   FeatureFMA4,
 715   FeatureCMPXCHG16B,
 716   FeatureAES,
 717   FeaturePRFCHW,
 718   FeaturePCLMUL,
 719   FeatureMMX,
 720   FeatureAVX,
 721   FeatureFXSR,
 722   FeatureSSE4A,
 723   FeatureF16C,
 724   FeatureLZCNT,
 725   FeaturePOPCNT,
 726   FeatureXSAVE,
 727   FeatureBMI,
 728   FeatureTBM,
 729   FeatureFMA,
 730   FeatureXSAVEOPT,
 731   FeatureSlowSHLD,
 732   FeatureFSGSBase,
 733   FeatureLAHFSAHF
 734 ]>;
 735
 736 // Excavator
 737 def : Proc<"bdver4", [
 738   FeatureX87,
 739   FeatureMMX,
 740   FeatureAVX2,
 741   FeatureFXSR,
 742   FeatureXOP,
 743   FeatureFMA4,
 744   FeatureCMPXCHG16B,
 745   FeatureAES,
 746   FeaturePRFCHW,
 747   FeaturePCLMUL,
 748   FeatureF16C,
 749   FeatureLZCNT,
 750   FeaturePOPCNT,
 751   FeatureXSAVE,
 752   FeatureBMI,
 753   FeatureBMI2,
 754   FeatureTBM,
 755   FeatureFMA,
 756   FeatureXSAVEOPT,
 757   FeatureSlowSHLD,
 758   FeatureFSGSBase,
 759   FeatureLAHFSAHF,
 760   FeatureMWAITX
 761 ]>;
 762
 763 def : Proc<"geode",           [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>;
 764
 765 def : Proc<"winchip-c6",      [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 766 def : Proc<"winchip2",        [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 767 def : Proc<"c3",              [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 768 def : Proc<"c3-2",            [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 769                                FeatureSSE1, FeatureFXSR]>;
 770
 771 // We also provide a generic 64-bit specific x86 processor model which tries to
 772 // be good for modern chips without enabling instruction set encodings past the
 773 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 774 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 775 //
 776 // We currently use the Sandy Bridge model as the default scheduling model as
 777 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 778 // covers a huge swath of x86 processors. If there are specific scheduling
 779 // knobs which need to be tuned differently for AMD chips, we might consider
 780 // forming a common base for them.
 781 def : ProcessorModel<"x86-64", SandyBridgeModel,
 782                      [FeatureX87, FeatureMMX, FeatureSSE2, FeatureFXSR,
 783                       Feature64Bit, FeatureSlowBTMem ]>;
 784
 785 //===----------------------------------------------------------------------===//
 786 // Register File Description
 787 //===----------------------------------------------------------------------===//
 788
 789 include "X86RegisterInfo.td"
 790
 791 //===----------------------------------------------------------------------===//
 792 // Instruction Descriptions
 793 //===----------------------------------------------------------------------===//
 794
 795 include "X86InstrInfo.td"
 796
 797 def X86InstrInfo : InstrInfo;
 798
 799 //===----------------------------------------------------------------------===//
 800 // Calling Conventions
 801 //===----------------------------------------------------------------------===//
 802
 803 include "X86CallingConv.td"
 804
 805
 806 //===----------------------------------------------------------------------===//
 807 // Assembly Parser
 808 //===----------------------------------------------------------------------===//
 809
 810 def ATTAsmParserVariant : AsmParserVariant {
 811   int Variant = 0;
 812
 813   // Variant name.
 814   string Name = "att";
 815
 816   // Discard comments in assembly strings.
 817   string CommentDelimiter = "#";
 818
 819   // Recognize hard coded registers.
 820   string RegisterPrefix = "%";
 821 }
 822
 823 def IntelAsmParserVariant : AsmParserVariant {
 824   int Variant = 1;
 825
 826   // Variant name.
 827   string Name = "intel";
 828
 829   // Discard comments in assembly strings.
 830   string CommentDelimiter = ";";
 831
 832   // Recognize hard coded registers.
 833   string RegisterPrefix = "";
 834 }
 835
 836 //===----------------------------------------------------------------------===//
 837 // Assembly Printers
 838 //===----------------------------------------------------------------------===//
 839
 840 // The X86 target supports two different syntaxes for emitting machine code.
 841 // This is controlled by the -x86-asm-syntax={att|intel}
 842 def ATTAsmWriter : AsmWriter {
 843   string AsmWriterClassName  = "ATTInstPrinter";
 844   int Variant = 0;
 845 }
 846 def IntelAsmWriter : AsmWriter {
 847   string AsmWriterClassName  = "IntelInstPrinter";
 848   int Variant = 1;
 849 }
 850
 851 def X86 : Target {
 852   // Information about the instructions...
 853   let InstructionSet = X86InstrInfo;
 854   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 855   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 856 }