contrib/llvm/lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureX87     : SubtargetFeature<"x87","HasX87", "true",
  35                                       "Enable X87 float instructions">;
  36
  37 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  38                                       "Enable conditional move instructions">;
  39
  40 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  41                                        "Support POPCNT instruction">;
  42
  43 def FeatureFXSR    : SubtargetFeature<"fxsr", "HasFXSR", "true",
  44                                       "Support fxsave/fxrestore instructions">;
  45
  46 def FeatureXSAVE   : SubtargetFeature<"xsave", "HasXSAVE", "true",
  47                                        "Support xsave instructions">;
  48
  49 def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
  50                                        "Support xsaveopt instructions">;
  51
  52 def FeatureXSAVEC  : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
  53                                        "Support xsavec instructions">;
  54
  55 def FeatureXSAVES  : SubtargetFeature<"xsaves", "HasXSAVES", "true",
  56                                        "Support xsaves instructions">;
  57
  58 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  59                                       "Enable SSE instructions",
  60                                       // SSE codegen depends on cmovs, and all
  61                                       // SSE1+ processors support them.
  62                                       [FeatureCMOV]>;
  63 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  64                                       "Enable SSE2 instructions",
  65                                       [FeatureSSE1]>;
  66 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  67                                       "Enable SSE3 instructions",
  68                                       [FeatureSSE2]>;
  69 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  70                                       "Enable SSSE3 instructions",
  71                                       [FeatureSSE3]>;
  72 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  73                                       "Enable SSE 4.1 instructions",
  74                                       [FeatureSSSE3]>;
  75 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  76                                       "Enable SSE 4.2 instructions",
  77                                       [FeatureSSE41]>;
  78 // The MMX subtarget feature is separate from the rest of the SSE features
  79 // because it's important (for odd compatibility reasons) to be able to
  80 // turn it off explicitly while allowing SSE+ to be on.
  81 def FeatureMMX     : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
  82                                       "Enable MMX instructions">;
  83 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  84                                       "Enable 3DNow! instructions",
  85                                       [FeatureMMX]>;
  86 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  87                                       "Enable 3DNow! Athlon instructions",
  88                                       [Feature3DNow]>;
  89 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  90 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  91 // without disabling 64-bit mode.
  92 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  93                                       "Support 64-bit instructions",
  94                                       [FeatureCMOV]>;
  95 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  96                                       "64-bit with cmpxchg16b",
  97                                       [Feature64Bit]>;
  98 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  99                                        "Bit testing of memory is slow">;
 100 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
 101                                        "SHLD instruction is slow">;
 102 def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
 103                                         "PMULLD instruction is slow">;
 104 // FIXME: This should not apply to CPUs that do not have SSE.
 105 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
 106                                 "IsUAMem16Slow", "true",
 107                                 "Slow unaligned 16-byte memory access">;
 108 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
 109                                 "IsUAMem32Slow", "true",
 110                                 "Slow unaligned 32-byte memory access">;
 111 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
 112                                       "Support SSE 4a instructions",
 113                                       [FeatureSSE3]>;
 114
 115 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
 116                                       "Enable AVX instructions",
 117                                       [FeatureSSE42]>;
 118 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 119                                       "Enable AVX2 instructions",
 120                                       [FeatureAVX]>;
 121 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 122                                       "Enable AVX-512 instructions",
 123                                       [FeatureAVX2]>;
 124 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 125                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 126                                       [FeatureAVX512]>;
 127 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 128                       "Enable AVX-512 Conflict Detection Instructions",
 129                                       [FeatureAVX512]>;
 130 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 131                       "Enable AVX-512 PreFetch Instructions",
 132                                       [FeatureAVX512]>;
 133 def FeaturePREFETCHWT1  : SubtargetFeature<"prefetchwt1", "HasPFPREFETCHWT1",
 134                                    "true",
 135                                    "Prefetch with Intent to Write and T1 Hint">;
 136 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 137                       "Enable AVX-512 Doubleword and Quadword Instructions",
 138                                       [FeatureAVX512]>;
 139 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 140                       "Enable AVX-512 Byte and Word Instructions",
 141                                       [FeatureAVX512]>;
 142 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 143                       "Enable AVX-512 Vector Length eXtensions",
 144                                       [FeatureAVX512]>;
 145 def FeatureVBMI     : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
 146                       "Enable AVX-512 Vector Byte Manipulation Instructions",
 147                                       [FeatureBWI]>;
 148 def FeatureIFMA     : SubtargetFeature<"avx512ifma", "HasIFMA", "true",
 149                       "Enable AVX-512 Integer Fused Multiple-Add",
 150                                       [FeatureAVX512]>;
 151 def FeaturePKU   : SubtargetFeature<"pku", "HasPKU", "true",
 152                       "Enable protection keys">;
 153 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 154                          "Enable packed carry-less multiplication instructions",
 155                                [FeatureSSE2]>;
 156 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 157                                       "Enable three-operand fused multiple-add",
 158                                       [FeatureAVX]>;
 159 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 160                                       "Enable four-operand fused multiple-add",
 161                                       [FeatureAVX, FeatureSSE4A]>;
 162 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 163                                       "Enable XOP instructions",
 164                                       [FeatureFMA4]>;
 165 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 166                                           "HasSSEUnalignedMem", "true",
 167                       "Allow unaligned memory operands with SSE instructions">;
 168 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 169                                       "Enable AES instructions",
 170                                       [FeatureSSE2]>;
 171 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 172                                       "Enable TBM instructions">;
 173 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 174                                       "Support MOVBE instruction">;
 175 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 176                                       "Support RDRAND instruction">;
 177 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 178                        "Support 16-bit floating point conversion instructions",
 179                        [FeatureAVX]>;
 180 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 181                                        "Support FS/GS Base instructions">;
 182 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 183                                       "Support LZCNT instruction">;
 184 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 185                                       "Support BMI instructions">;
 186 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 187                                       "Support BMI2 instructions">;
 188 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 189                                       "Support RTM instructions">;
 190 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 191                                       "Support ADX instructions">;
 192 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 193                                       "Enable SHA instructions",
 194                                       [FeatureSSE2]>;
 195 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 196                                       "Support PRFCHW instructions">;
 197 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 198                                       "Support RDSEED instruction">;
 199 def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
 200                                        "Support LAHF and SAHF instructions">;
 201 def FeatureMWAITX  : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
 202                                       "Enable MONITORX/MWAITX timer functionality">;
 203 def FeatureCLZERO  : SubtargetFeature<"clzero", "HasCLZERO", "true",
 204                                       "Enable Cache Line Zero">;
 205 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
 206                                       "Support MPX instructions">;
 207 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 208                                      "Use LEA for adjusting the stack pointer">;
 209 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 210                                      "HasSlowDivide32", "true",
 211                                      "Use 8-bit divide for positive values less than 256">;
 212 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",
 213                                      "HasSlowDivide64", "true",
 214                                      "Use 32-bit divide for positive values less than 2^32">;
 215 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 216                                      "PadShortFunctions", "true",
 217                                      "Pad short functions">;
 218 def FeatureSGX     : SubtargetFeature<"sgx", "HasSGX", "true",
 219                                       "Enable Software Guard Extensions">;
 220 def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
 221                                       "Flush A Cache Line Optimized">;
 222 def FeatureCLWB    : SubtargetFeature<"clwb", "HasCLWB", "true",
 223                                       "Cache Line Write Back">;
 224 // TODO: This feature ought to be renamed.
 225 // What it really refers to are CPUs for which certain instructions
 226 // (which ones besides the example below?) are microcoded.
 227 // The best examples of this are the memory forms of CALL and PUSH
 228 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
 229 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 230                                      "CallRegIndirect", "true",
 231                                      "Call register indirect">;
 232 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 233                                    "LEA instruction needs inputs at AG stage">;
 234 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 235                                    "LEA instruction with certain arguments is slow">;
 236 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 237                                    "INC and DEC instructions are slower than ADD and SUB">;
 238 def FeatureSoftFloat
 239     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
 240                        "Use software floating point features.">;
 241 // On some X86 processors, there is no performance hazard to writing only the
 242 // lower parts of a YMM or ZMM register without clearing the upper part.
 243 def FeatureFastPartialYMMorZMMWrite
 244     : SubtargetFeature<"fast-partial-ymm-or-zmm-write",
 245                        "HasFastPartialYMMorZMMWrite",
 246                        "true", "Partial writes to YMM/ZMM registers are fast">;
 247 // FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
 248 // than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if
 249 // vector FSQRT has higher throughput than the corresponding NR code.
 250 // The idea is that throughput bound code is likely to be vectorized, so for
 251 // vectorized code we should care about the throughput of SQRT operations.
 252 // But if the code is scalar that probably means that the code has some kind of
 253 // dependency and we should care more about reducing the latency.
 254 def FeatureFastScalarFSQRT
 255     : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
 256                        "true", "Scalar SQRT is fast (disable Newton-Raphson)">;
 257 def FeatureFastVectorFSQRT
 258     : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
 259                        "true", "Vector SQRT is fast (disable Newton-Raphson)">;
 260 // If lzcnt has equivalent latency/throughput to most simple integer ops, it can
 261 // be used to replace test/set sequences.
 262 def FeatureFastLZCNT
 263     : SubtargetFeature<
 264           "fast-lzcnt", "HasFastLZCNT", "true",
 265           "LZCNT instructions are as fast as most simple integer ops">;
 266
 267
 268 // Sandy Bridge and newer processors can use SHLD with the same source on both
 269 // inputs to implement rotate to avoid the partial flag update of the normal
 270 // rotate instructions.
 271 def FeatureFastSHLDRotate
 272     : SubtargetFeature<
 273           "fast-shld-rotate", "HasFastSHLDRotate", "true",
 274           "SHLD can be used as a faster rotate">;
 275
 276 //===----------------------------------------------------------------------===//
 277 // X86 processors supported.
 278 //===----------------------------------------------------------------------===//
 279
 280 include "X86Schedule.td"
 281
 282 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 283                     "Intel Atom processors">;
 284 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 285                     "Intel Silvermont processors">;
 286
 287 class Proc<string Name, list<SubtargetFeature> Features>
 288  : ProcessorModel<Name, GenericModel, Features>;
 289
 290 def : Proc<"generic",         [FeatureX87, FeatureSlowUAMem16]>;
 291 def : Proc<"i386",            [FeatureX87, FeatureSlowUAMem16]>;
 292 def : Proc<"i486",            [FeatureX87, FeatureSlowUAMem16]>;
 293 def : Proc<"i586",            [FeatureX87, FeatureSlowUAMem16]>;
 294 def : Proc<"pentium",         [FeatureX87, FeatureSlowUAMem16]>;
 295 def : Proc<"pentium-mmx",     [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 296 def : Proc<"i686",            [FeatureX87, FeatureSlowUAMem16]>;
 297 def : Proc<"pentiumpro",      [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
 298 def : Proc<"pentium2",        [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 299                                FeatureCMOV, FeatureFXSR]>;
 300 def : Proc<"pentium3",        [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 301                                FeatureSSE1, FeatureFXSR]>;
 302 def : Proc<"pentium3m",       [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 303                                FeatureSSE1, FeatureFXSR, FeatureSlowBTMem]>;
 304
 305 // Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
 306 // The intent is to enable it for pentium4 which is the current default
 307 // processor in a vanilla 32-bit clang compilation when no specific
 308 // architecture is specified.  This generally gives a nice performance
 309 // increase on silvermont, with largely neutral behavior on other
 310 // contemporary large core processors.
 311 // pentium-m, pentium4m, prescott and nocona are included as a preventative
 312 // measure to avoid performance surprises, in case clang's default cpu
 313 // changes slightly.
 314
 315 def : ProcessorModel<"pentium-m", GenericPostRAModel,
 316                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 317                       FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>;
 318
 319 def : ProcessorModel<"pentium4", GenericPostRAModel,
 320                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 321                       FeatureSSE2, FeatureFXSR]>;
 322
 323 def : ProcessorModel<"pentium4m", GenericPostRAModel,
 324                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 325                       FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>;
 326
 327 // Intel Quark.
 328 def : Proc<"lakemont",        []>;
 329
 330 // Intel Core Duo.
 331 def : ProcessorModel<"yonah", SandyBridgeModel,
 332                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
 333                       FeatureFXSR, FeatureSlowBTMem]>;
 334
 335 // NetBurst.
 336 def : ProcessorModel<"prescott", GenericPostRAModel,
 337                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
 338                       FeatureFXSR, FeatureSlowBTMem]>;
 339 def : ProcessorModel<"nocona", GenericPostRAModel, [
 340   FeatureX87,
 341   FeatureSlowUAMem16,
 342   FeatureMMX,
 343   FeatureSSE3,
 344   FeatureFXSR,
 345   FeatureCMPXCHG16B,
 346   FeatureSlowBTMem
 347 ]>;
 348
 349 // Intel Core 2 Solo/Duo.
 350 def : ProcessorModel<"core2", SandyBridgeModel, [
 351   FeatureX87,
 352   FeatureSlowUAMem16,
 353   FeatureMMX,
 354   FeatureSSSE3,
 355   FeatureFXSR,
 356   FeatureCMPXCHG16B,
 357   FeatureSlowBTMem,
 358   FeatureLAHFSAHF
 359 ]>;
 360 def : ProcessorModel<"penryn", SandyBridgeModel, [
 361   FeatureX87,
 362   FeatureSlowUAMem16,
 363   FeatureMMX,
 364   FeatureSSE41,
 365   FeatureFXSR,
 366   FeatureCMPXCHG16B,
 367   FeatureSlowBTMem,
 368   FeatureLAHFSAHF
 369 ]>;
 370
 371 // Atom CPUs.
 372 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 373   ProcIntelAtom,
 374   FeatureX87,
 375   FeatureSlowUAMem16,
 376   FeatureMMX,
 377   FeatureSSSE3,
 378   FeatureFXSR,
 379   FeatureCMPXCHG16B,
 380   FeatureMOVBE,
 381   FeatureSlowBTMem,
 382   FeatureLEAForSP,
 383   FeatureSlowDivide32,
 384   FeatureSlowDivide64,
 385   FeatureCallRegIndirect,
 386   FeatureLEAUsesAG,
 387   FeaturePadShortFunctions,
 388   FeatureLAHFSAHF
 389 ]>;
 390 def : BonnellProc<"bonnell">;
 391 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 392
 393 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 394   ProcIntelSLM,
 395   FeatureX87,
 396   FeatureMMX,
 397   FeatureSSE42,
 398   FeatureFXSR,
 399   FeatureCMPXCHG16B,
 400   FeatureMOVBE,
 401   FeaturePOPCNT,
 402   FeaturePCLMUL,
 403   FeatureAES,
 404   FeatureSlowDivide64,
 405   FeatureCallRegIndirect,
 406   FeaturePRFCHW,
 407   FeatureSlowLEA,
 408   FeatureSlowIncDec,
 409   FeatureSlowBTMem,
 410   FeatureSlowPMULLD,
 411   FeatureLAHFSAHF
 412 ]>;
 413 def : SilvermontProc<"silvermont">;
 414 def : SilvermontProc<"slm">; // Legacy alias.
 415
 416 // "Arrandale" along with corei3 and corei5
 417 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 418   FeatureX87,
 419   FeatureMMX,
 420   FeatureSSE42,
 421   FeatureFXSR,
 422   FeatureCMPXCHG16B,
 423   FeatureSlowBTMem,
 424   FeaturePOPCNT,
 425   FeatureLAHFSAHF
 426 ]>;
 427 def : NehalemProc<"nehalem">;
 428 def : NehalemProc<"corei7">;
 429
 430 // Westmere is a similar machine to nehalem with some additional features.
 431 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 432 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 433   FeatureX87,
 434   FeatureMMX,
 435   FeatureSSE42,
 436   FeatureFXSR,
 437   FeatureCMPXCHG16B,
 438   FeatureSlowBTMem,
 439   FeaturePOPCNT,
 440   FeatureAES,
 441   FeaturePCLMUL,
 442   FeatureLAHFSAHF
 443 ]>;
 444 def : WestmereProc<"westmere">;
 445
 446 class ProcessorFeatures<list<SubtargetFeature> Inherited,
 447                         list<SubtargetFeature> NewFeatures> {
 448   list<SubtargetFeature> Value = !listconcat(Inherited, NewFeatures);
 449 }
 450
 451 class ProcModel<string Name, SchedMachineModel Model,
 452                 list<SubtargetFeature> ProcFeatures,
 453                 list<SubtargetFeature> OtherFeatures> :
 454   ProcessorModel<Name, Model, !listconcat(ProcFeatures, OtherFeatures)>;
 455
 456 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 457 // rather than a superset.
 458 def SNBFeatures : ProcessorFeatures<[], [
 459   FeatureX87,
 460   FeatureMMX,
 461   FeatureAVX,
 462   FeatureFXSR,
 463   FeatureCMPXCHG16B,
 464   FeaturePOPCNT,
 465   FeatureAES,
 466   FeatureSlowDivide64,
 467   FeaturePCLMUL,
 468   FeatureXSAVE,
 469   FeatureXSAVEOPT,
 470   FeatureLAHFSAHF,
 471   FeatureFastScalarFSQRT,
 472   FeatureFastSHLDRotate
 473 ]>;
 474
 475 class SandyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
 476                                                SNBFeatures.Value, [
 477   FeatureSlowBTMem,
 478   FeatureSlowUAMem32
 479 ]>;
 480 def : SandyBridgeProc<"sandybridge">;
 481 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 482
 483 def IVBFeatures : ProcessorFeatures<SNBFeatures.Value, [
 484   FeatureRDRAND,
 485   FeatureF16C,
 486   FeatureFSGSBase
 487 ]>;
 488
 489 class IvyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
 490                                              IVBFeatures.Value, [
 491   FeatureSlowBTMem,
 492   FeatureSlowUAMem32
 493 ]>;
 494 def : IvyBridgeProc<"ivybridge">;
 495 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 496
 497 def HSWFeatures : ProcessorFeatures<IVBFeatures.Value, [
 498   FeatureAVX2,
 499   FeatureBMI,
 500   FeatureBMI2,
 501   FeatureFMA,
 502   FeatureLZCNT,
 503   FeatureMOVBE,
 504   FeatureSlowIncDec
 505 ]>;
 506
 507 class HaswellProc<string Name> : ProcModel<Name, HaswellModel,
 508                                            HSWFeatures.Value, []>;
 509 def : HaswellProc<"haswell">;
 510 def : HaswellProc<"core-avx2">; // Legacy alias.
 511
 512 def BDWFeatures : ProcessorFeatures<HSWFeatures.Value, [
 513   FeatureADX,
 514   FeatureRDSEED
 515 ]>;
 516 class BroadwellProc<string Name> : ProcModel<Name, HaswellModel,
 517                                              BDWFeatures.Value, []>;
 518 def : BroadwellProc<"broadwell">;
 519
 520 def SKLFeatures : ProcessorFeatures<BDWFeatures.Value, [
 521   FeatureMPX,
 522   FeatureRTM,
 523   FeatureXSAVEC,
 524   FeatureXSAVES,
 525   FeatureSGX,
 526   FeatureCLFLUSHOPT,
 527   FeatureFastVectorFSQRT
 528 ]>;
 529
 530 // FIXME: define SKL model
 531 class SkylakeClientProc<string Name> : ProcModel<Name, HaswellModel,
 532                                                  SKLFeatures.Value, []>;
 533 def : SkylakeClientProc<"skylake">;
 534
 535 // FIXME: define KNL model
 536 class KnightsLandingProc<string Name> : ProcModel<Name, HaswellModel,
 537                                                   IVBFeatures.Value, [
 538   FeatureAVX512,
 539   FeatureERI,
 540   FeatureCDI,
 541   FeaturePFI,
 542   FeaturePREFETCHWT1,
 543   FeatureADX,
 544   FeatureRDSEED,
 545   FeatureMOVBE,
 546   FeatureLZCNT,
 547   FeatureBMI,
 548   FeatureBMI2,
 549   FeatureFMA,
 550   FeatureFastPartialYMMorZMMWrite
 551 ]>;
 552 def : KnightsLandingProc<"knl">;
 553
 554 def SKXFeatures : ProcessorFeatures<SKLFeatures.Value, [
 555   FeatureAVX512,
 556   FeatureCDI,
 557   FeatureDQI,
 558   FeatureBWI,
 559   FeatureVLX,
 560   FeaturePKU,
 561   FeatureCLWB
 562 ]>;
 563
 564 // FIXME: define SKX model
 565 class SkylakeServerProc<string Name> : ProcModel<Name, HaswellModel,
 566                                                  SKXFeatures.Value, []>;
 567 def : SkylakeServerProc<"skylake-avx512">;
 568 def : SkylakeServerProc<"skx">; // Legacy alias.
 569
 570 def CNLFeatures : ProcessorFeatures<SKXFeatures.Value, [
 571   FeatureVBMI,
 572   FeatureIFMA,
 573   FeatureSHA
 574 ]>;
 575
 576 class CannonlakeProc<string Name> : ProcModel<Name, HaswellModel,
 577                                               CNLFeatures.Value, []>;
 578 def : CannonlakeProc<"cannonlake">;
 579
 580 // AMD CPUs.
 581
 582 def : Proc<"k6",              [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 583 def : Proc<"k6-2",            [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 584 def : Proc<"k6-3",            [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 585 def : Proc<"athlon",          [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
 586                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 587 def : Proc<"athlon-tbird",    [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
 588                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 589 def : Proc<"athlon-4",        [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
 590                                Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
 591                                FeatureSlowSHLD]>;
 592 def : Proc<"athlon-xp",       [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
 593                                Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
 594                                FeatureSlowSHLD]>;
 595 def : Proc<"athlon-mp",       [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
 596                                Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
 597                                FeatureSlowSHLD]>;
 598 def : Proc<"k8",              [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 599                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 600                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 601 def : Proc<"opteron",         [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 602                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 603                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 604 def : Proc<"athlon64",        [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 605                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 606                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 607 def : Proc<"athlon-fx",       [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 608                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 609                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 610 def : Proc<"k8-sse3",         [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
 611                                Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
 612                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 613 def : Proc<"opteron-sse3",    [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
 614                                Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
 615                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 616 def : Proc<"athlon64-sse3",   [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
 617                                Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
 618                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 619 def : Proc<"amdfam10",        [FeatureX87, FeatureSSE4A, Feature3DNowA,
 620                                FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
 621                                FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD,
 622                                FeatureLAHFSAHF]>;
 623 def : Proc<"barcelona",       [FeatureX87, FeatureSSE4A, Feature3DNowA,
 624                                FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
 625                                FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD,
 626                                FeatureLAHFSAHF]>;
 627
 628 // Bobcat
 629 def : Proc<"btver1", [
 630   FeatureX87,
 631   FeatureMMX,
 632   FeatureSSSE3,
 633   FeatureSSE4A,
 634   FeatureFXSR,
 635   FeatureCMPXCHG16B,
 636   FeaturePRFCHW,
 637   FeatureLZCNT,
 638   FeaturePOPCNT,
 639   FeatureSlowSHLD,
 640   FeatureLAHFSAHF
 641 ]>;
 642
 643 // Jaguar
 644 def : ProcessorModel<"btver2", BtVer2Model, [
 645   FeatureX87,
 646   FeatureMMX,
 647   FeatureAVX,
 648   FeatureFXSR,
 649   FeatureSSE4A,
 650   FeatureCMPXCHG16B,
 651   FeaturePRFCHW,
 652   FeatureAES,
 653   FeaturePCLMUL,
 654   FeatureBMI,
 655   FeatureF16C,
 656   FeatureMOVBE,
 657   FeatureLZCNT,
 658   FeatureFastLZCNT,
 659   FeaturePOPCNT,
 660   FeatureXSAVE,
 661   FeatureXSAVEOPT,
 662   FeatureSlowSHLD,
 663   FeatureLAHFSAHF,
 664   FeatureFastPartialYMMorZMMWrite
 665 ]>;
 666
 667 // Bulldozer
 668 def : Proc<"bdver1", [
 669   FeatureX87,
 670   FeatureXOP,
 671   FeatureFMA4,
 672   FeatureCMPXCHG16B,
 673   FeatureAES,
 674   FeaturePRFCHW,
 675   FeaturePCLMUL,
 676   FeatureMMX,
 677   FeatureAVX,
 678   FeatureFXSR,
 679   FeatureSSE4A,
 680   FeatureLZCNT,
 681   FeaturePOPCNT,
 682   FeatureXSAVE,
 683   FeatureSlowSHLD,
 684   FeatureLAHFSAHF
 685 ]>;
 686 // Piledriver
 687 def : Proc<"bdver2", [
 688   FeatureX87,
 689   FeatureXOP,
 690   FeatureFMA4,
 691   FeatureCMPXCHG16B,
 692   FeatureAES,
 693   FeaturePRFCHW,
 694   FeaturePCLMUL,
 695   FeatureMMX,
 696   FeatureAVX,
 697   FeatureFXSR,
 698   FeatureSSE4A,
 699   FeatureF16C,
 700   FeatureLZCNT,
 701   FeaturePOPCNT,
 702   FeatureXSAVE,
 703   FeatureBMI,
 704   FeatureTBM,
 705   FeatureFMA,
 706   FeatureSlowSHLD,
 707   FeatureLAHFSAHF
 708 ]>;
 709
 710 // Steamroller
 711 def : Proc<"bdver3", [
 712   FeatureX87,
 713   FeatureXOP,
 714   FeatureFMA4,
 715   FeatureCMPXCHG16B,
 716   FeatureAES,
 717   FeaturePRFCHW,
 718   FeaturePCLMUL,
 719   FeatureMMX,
 720   FeatureAVX,
 721   FeatureFXSR,
 722   FeatureSSE4A,
 723   FeatureF16C,
 724   FeatureLZCNT,
 725   FeaturePOPCNT,
 726   FeatureXSAVE,
 727   FeatureBMI,
 728   FeatureTBM,
 729   FeatureFMA,
 730   FeatureXSAVEOPT,
 731   FeatureSlowSHLD,
 732   FeatureFSGSBase,
 733   FeatureLAHFSAHF
 734 ]>;
 735
 736 // Excavator
 737 def : Proc<"bdver4", [
 738   FeatureX87,
 739   FeatureMMX,
 740   FeatureAVX2,
 741   FeatureFXSR,
 742   FeatureXOP,
 743   FeatureFMA4,
 744   FeatureCMPXCHG16B,
 745   FeatureAES,
 746   FeaturePRFCHW,
 747   FeaturePCLMUL,
 748   FeatureF16C,
 749   FeatureLZCNT,
 750   FeaturePOPCNT,
 751   FeatureXSAVE,
 752   FeatureBMI,
 753   FeatureBMI2,
 754   FeatureTBM,
 755   FeatureFMA,
 756   FeatureXSAVEOPT,
 757   FeatureSlowSHLD,
 758   FeatureFSGSBase,
 759   FeatureLAHFSAHF,
 760   FeatureMWAITX
 761 ]>;
 762
 763 // TODO: The scheduler model falls to BTVER2 model.
 764 // The znver1 model has to be put in place.
 765 // Zen
 766 def: ProcessorModel<"znver1", BtVer2Model, [
 767   FeatureADX,
 768   FeatureAES,
 769   FeatureAVX2,
 770   FeatureBMI,
 771   FeatureBMI2,
 772   FeatureCLFLUSHOPT,
 773   FeatureCLZERO,
 774   FeatureCMPXCHG16B,
 775   FeatureF16C,
 776   FeatureFMA,
 777   FeatureFSGSBase,
 778   FeatureFXSR,
 779   FeatureFastLZCNT,
 780   FeatureLAHFSAHF,
 781   FeatureLZCNT,
 782   FeatureMMX,
 783   FeatureMOVBE,
 784   FeatureMWAITX,
 785   FeaturePCLMUL,
 786   FeaturePOPCNT,
 787   FeaturePRFCHW,
 788   FeatureRDRAND,
 789   FeatureRDSEED,
 790   FeatureSHA,
 791   FeatureSSE4A,
 792   FeatureSlowSHLD,
 793   FeatureX87,
 794   FeatureXSAVE,
 795   FeatureXSAVEC,
 796   FeatureXSAVEOPT,
 797   FeatureXSAVES]>;
 798
 799 def : Proc<"geode",           [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>;
 800
 801 def : Proc<"winchip-c6",      [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 802 def : Proc<"winchip2",        [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 803 def : Proc<"c3",              [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 804 def : Proc<"c3-2",            [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 805                                FeatureSSE1, FeatureFXSR]>;
 806
 807 // We also provide a generic 64-bit specific x86 processor model which tries to
 808 // be good for modern chips without enabling instruction set encodings past the
 809 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 810 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 811 //
 812 // We currently use the Sandy Bridge model as the default scheduling model as
 813 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 814 // covers a huge swath of x86 processors. If there are specific scheduling
 815 // knobs which need to be tuned differently for AMD chips, we might consider
 816 // forming a common base for them.
 817 def : ProcessorModel<"x86-64", SandyBridgeModel,
 818                      [FeatureX87, FeatureMMX, FeatureSSE2, FeatureFXSR,
 819                       Feature64Bit, FeatureSlowBTMem ]>;
 820
 821 //===----------------------------------------------------------------------===//
 822 // Register File Description
 823 //===----------------------------------------------------------------------===//
 824
 825 include "X86RegisterInfo.td"
 826 include "X86RegisterBanks.td"
 827
 828 //===----------------------------------------------------------------------===//
 829 // Instruction Descriptions
 830 //===----------------------------------------------------------------------===//
 831
 832 include "X86InstrInfo.td"
 833
 834 def X86InstrInfo : InstrInfo;
 835
 836 //===----------------------------------------------------------------------===//
 837 // Calling Conventions
 838 //===----------------------------------------------------------------------===//
 839
 840 include "X86CallingConv.td"
 841
 842
 843 //===----------------------------------------------------------------------===//
 844 // Assembly Parser
 845 //===----------------------------------------------------------------------===//
 846
 847 def ATTAsmParserVariant : AsmParserVariant {
 848   int Variant = 0;
 849
 850   // Variant name.
 851   string Name = "att";
 852
 853   // Discard comments in assembly strings.
 854   string CommentDelimiter = "#";
 855
 856   // Recognize hard coded registers.
 857   string RegisterPrefix = "%";
 858 }
 859
 860 def IntelAsmParserVariant : AsmParserVariant {
 861   int Variant = 1;
 862
 863   // Variant name.
 864   string Name = "intel";
 865
 866   // Discard comments in assembly strings.
 867   string CommentDelimiter = ";";
 868
 869   // Recognize hard coded registers.
 870   string RegisterPrefix = "";
 871 }
 872
 873 //===----------------------------------------------------------------------===//
 874 // Assembly Printers
 875 //===----------------------------------------------------------------------===//
 876
 877 // The X86 target supports two different syntaxes for emitting machine code.
 878 // This is controlled by the -x86-asm-syntax={att|intel}
 879 def ATTAsmWriter : AsmWriter {
 880   string AsmWriterClassName  = "ATTInstPrinter";
 881   int Variant = 0;
 882 }
 883 def IntelAsmWriter : AsmWriter {
 884   string AsmWriterClassName  = "IntelInstPrinter";
 885   int Variant = 1;
 886 }
 887
 888 def X86 : Target {
 889   // Information about the instructions...
 890   let InstructionSet = X86InstrInfo;
 891   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 892   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 893 }