1 //===----- X86CallFrameOptimization.cpp - Optimize x86 call sequences -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pass that optimizes call sequences on x86.
11 // Currently, it converts movs of function parameters onto the stack into
12 // pushes. This is beneficial for two main reasons:
13 // 1) The push instruction encoding is much smaller than a stack-ptr-based mov.
14 // 2) It is possible to push memory arguments directly. So, if the
15 // the transformation is performed pre-reg-alloc, it can help relieve
18 //===----------------------------------------------------------------------===//
20 #include "MCTargetDesc/X86BaseInfo.h"
21 #include "X86FrameLowering.h"
22 #include "X86InstrInfo.h"
23 #include "X86MachineFunctionInfo.h"
24 #include "X86RegisterInfo.h"
25 #include "X86Subtarget.h"
26 #include "llvm/ADT/DenseSet.h"
27 #include "llvm/ADT/SmallVector.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/CodeGen/MachineBasicBlock.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineInstr.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineOperand.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/TargetInstrInfo.h"
38 #include "llvm/CodeGen/TargetRegisterInfo.h"
39 #include "llvm/IR/DebugLoc.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/MC/MCDwarf.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/MathExtras.h"
52 #define DEBUG_TYPE "x86-cf-opt"
55 NoX86CFOpt("no-x86-call-frame-opt",
56 cl::desc("Avoid optimizing x86 call frames for size"),
57 cl::init(false), cl::Hidden);
61 class X86CallFrameOptimization : public MachineFunctionPass {
63 X86CallFrameOptimization() : MachineFunctionPass(ID) {
64 initializeX86CallFrameOptimizationPass(
65 *PassRegistry::getPassRegistry());
68 bool runOnMachineFunction(MachineFunction &MF) override;
73 // Information we know about a particular call site
75 CallContext() : FrameSetup(nullptr), ArgStoreVector(4, nullptr) {}
77 // Iterator referring to the frame setup instruction
78 MachineBasicBlock::iterator FrameSetup;
80 // Actual call instruction
81 MachineInstr *Call = nullptr;
83 // A copy of the stack pointer
84 MachineInstr *SPCopy = nullptr;
86 // The total displacement of all passed parameters
87 int64_t ExpectedDist = 0;
89 // The sequence of storing instructions used to pass the parameters
90 SmallVector<MachineInstr *, 4> ArgStoreVector;
92 // True if this call site has no stack parameters
93 bool NoStackParams = false;
95 // True if this call site can use push instructions
99 typedef SmallVector<CallContext, 8> ContextVector;
101 bool isLegal(MachineFunction &MF);
103 bool isProfitable(MachineFunction &MF, ContextVector &CallSeqMap);
105 void collectCallInfo(MachineFunction &MF, MachineBasicBlock &MBB,
106 MachineBasicBlock::iterator I, CallContext &Context);
108 void adjustCallSequence(MachineFunction &MF, const CallContext &Context);
110 MachineInstr *canFoldIntoRegPush(MachineBasicBlock::iterator FrameSetup,
113 enum InstClassification { Convert, Skip, Exit };
115 InstClassification classifyInstruction(MachineBasicBlock &MBB,
116 MachineBasicBlock::iterator MI,
117 const X86RegisterInfo &RegInfo,
118 DenseSet<unsigned int> &UsedRegs);
120 StringRef getPassName() const override { return "X86 Optimize Call Frame"; }
122 const X86InstrInfo *TII;
123 const X86FrameLowering *TFL;
124 const X86Subtarget *STI;
125 MachineRegisterInfo *MRI;
127 unsigned Log2SlotSize;
130 } // end anonymous namespace
131 char X86CallFrameOptimization::ID = 0;
132 INITIALIZE_PASS(X86CallFrameOptimization, DEBUG_TYPE,
133 "X86 Call Frame Optimization", false, false)
135 // This checks whether the transformation is legal.
136 // Also returns false in cases where it's potentially legal, but
137 // we don't even want to try.
138 bool X86CallFrameOptimization::isLegal(MachineFunction &MF) {
139 if (NoX86CFOpt.getValue())
142 // We can't encode multiple DW_CFA_GNU_args_size or DW_CFA_def_cfa_offset
143 // in the compact unwind encoding that Darwin uses. So, bail if there
144 // is a danger of that being generated.
145 if (STI->isTargetDarwin() &&
146 (!MF.getLandingPads().empty() ||
147 (MF.getFunction().needsUnwindTableEntry() && !TFL->hasFP(MF))))
150 // It is not valid to change the stack pointer outside the prolog/epilog
151 // on 64-bit Windows.
152 if (STI->isTargetWin64())
155 // You would expect straight-line code between call-frame setup and
156 // call-frame destroy. You would be wrong. There are circumstances (e.g.
157 // CMOV_GR8 expansion of a select that feeds a function call!) where we can
158 // end up with the setup and the destroy in different basic blocks.
159 // This is bad, and breaks SP adjustment.
160 // So, check that all of the frames in the function are closed inside
161 // the same block, and, for good measure, that there are no nested frames.
162 unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
163 unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
164 for (MachineBasicBlock &BB : MF) {
165 bool InsideFrameSequence = false;
166 for (MachineInstr &MI : BB) {
167 if (MI.getOpcode() == FrameSetupOpcode) {
168 if (InsideFrameSequence)
170 InsideFrameSequence = true;
171 } else if (MI.getOpcode() == FrameDestroyOpcode) {
172 if (!InsideFrameSequence)
174 InsideFrameSequence = false;
178 if (InsideFrameSequence)
185 // Check whether this transformation is profitable for a particular
186 // function - in terms of code size.
187 bool X86CallFrameOptimization::isProfitable(MachineFunction &MF,
188 ContextVector &CallSeqVector) {
189 // This transformation is always a win when we do not expect to have
190 // a reserved call frame. Under other circumstances, it may be either
191 // a win or a loss, and requires a heuristic.
192 bool CannotReserveFrame = MF.getFrameInfo().hasVarSizedObjects();
193 if (CannotReserveFrame)
196 unsigned StackAlign = TFL->getStackAlignment();
198 int64_t Advantage = 0;
199 for (auto CC : CallSeqVector) {
200 // Call sites where no parameters are passed on the stack
201 // do not affect the cost, since there needs to be no
203 if (CC.NoStackParams)
207 // If we don't use pushes for a particular call site,
208 // we pay for not having a reserved call frame with an
209 // additional sub/add esp pair. The cost is ~3 bytes per instruction,
210 // depending on the size of the constant.
211 // TODO: Callee-pop functions should have a smaller penalty, because
212 // an add is needed even with a reserved call frame.
215 // We can use pushes. First, account for the fixed costs.
216 // We'll need a add after the call.
218 // If we have to realign the stack, we'll also need a sub before
219 if (CC.ExpectedDist % StackAlign)
221 // Now, for each push, we save ~3 bytes. For small constants, we actually,
222 // save more (up to 5 bytes), but 3 should be a good approximation.
223 Advantage += (CC.ExpectedDist >> Log2SlotSize) * 3;
227 return Advantage >= 0;
230 bool X86CallFrameOptimization::runOnMachineFunction(MachineFunction &MF) {
231 STI = &MF.getSubtarget<X86Subtarget>();
232 TII = STI->getInstrInfo();
233 TFL = STI->getFrameLowering();
234 MRI = &MF.getRegInfo();
236 const X86RegisterInfo &RegInfo =
237 *static_cast<const X86RegisterInfo *>(STI->getRegisterInfo());
238 SlotSize = RegInfo.getSlotSize();
239 assert(isPowerOf2_32(SlotSize) && "Expect power of 2 stack slot size");
240 Log2SlotSize = Log2_32(SlotSize);
242 if (skipFunction(MF.getFunction()) || !isLegal(MF))
245 unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
247 bool Changed = false;
249 ContextVector CallSeqVector;
253 if (MI.getOpcode() == FrameSetupOpcode) {
255 collectCallInfo(MF, MBB, MI, Context);
256 CallSeqVector.push_back(Context);
259 if (!isProfitable(MF, CallSeqVector))
262 for (auto CC : CallSeqVector) {
264 adjustCallSequence(MF, CC);
272 X86CallFrameOptimization::InstClassification
273 X86CallFrameOptimization::classifyInstruction(
274 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
275 const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) {
279 // The instructions we actually care about are movs onto the stack or special
280 // cases of constant-stores to stack
281 switch (MI->getOpcode()) {
284 case X86::AND64mi8: {
285 MachineOperand ImmOp = MI->getOperand(X86::AddrNumOperands);
286 return ImmOp.getImm() == 0 ? Convert : Exit;
291 MachineOperand ImmOp = MI->getOperand(X86::AddrNumOperands);
292 return ImmOp.getImm() == -1 ? Convert : Exit;
301 // Not all calling conventions have only stack MOVs between the stack
302 // adjust and the call.
304 // We want to tolerate other instructions, to cover more cases.
306 // a) PCrel calls, where we expect an additional COPY of the basereg.
307 // b) Passing frame-index addresses.
308 // c) Calling conventions that have inreg parameters. These generate
309 // both copies and movs into registers.
310 // To avoid creating lots of special cases, allow any instruction
311 // that does not write into memory, does not def or use the stack
312 // pointer, and does not def any register that was used by a preceding
314 // (Reading from memory is allowed, even if referenced through a
315 // frame index, since these will get adjusted properly in PEI)
317 // The reason for the last condition is that the pushes can't replace
318 // the movs in place, because the order must be reversed.
319 // So if we have a MOV32mr that uses EDX, then an instruction that defs
320 // EDX, and then the call, after the transformation the push will use
321 // the modified version of EDX, and not the original one.
322 // Since we are still in SSA form at this point, we only need to
323 // make sure we don't clobber any *physical* registers that were
324 // used by an earlier mov that will become a push.
326 if (MI->isCall() || MI->mayStore())
329 for (const MachineOperand &MO : MI->operands()) {
332 unsigned int Reg = MO.getReg();
333 if (!RegInfo.isPhysicalRegister(Reg))
335 if (RegInfo.regsOverlap(Reg, RegInfo.getStackRegister()))
338 for (unsigned int U : UsedRegs)
339 if (RegInfo.regsOverlap(Reg, U))
347 void X86CallFrameOptimization::collectCallInfo(MachineFunction &MF,
348 MachineBasicBlock &MBB,
349 MachineBasicBlock::iterator I,
350 CallContext &Context) {
351 // Check that this particular call sequence is amenable to the
353 const X86RegisterInfo &RegInfo =
354 *static_cast<const X86RegisterInfo *>(STI->getRegisterInfo());
356 // We expect to enter this at the beginning of a call sequence
357 assert(I->getOpcode() == TII->getCallFrameSetupOpcode());
358 MachineBasicBlock::iterator FrameSetup = I++;
359 Context.FrameSetup = FrameSetup;
361 // How much do we adjust the stack? This puts an upper bound on
362 // the number of parameters actually passed on it.
363 unsigned int MaxAdjust = TII->getFrameSize(*FrameSetup) >> Log2SlotSize;
365 // A zero adjustment means no stack parameters
367 Context.NoStackParams = true;
371 // Skip over DEBUG_VALUE.
372 // For globals in PIC mode, we can have some LEAs here. Skip them as well.
373 // TODO: Extend this to something that covers more cases.
374 while (I->getOpcode() == X86::LEA32r || I->isDebugInstr())
377 unsigned StackPtr = RegInfo.getStackRegister();
378 auto StackPtrCopyInst = MBB.end();
379 // SelectionDAG (but not FastISel) inserts a copy of ESP into a virtual
380 // register. If it's there, use that virtual register as stack pointer
381 // instead. Also, we need to locate this instruction so that we can later
382 // safely ignore it while doing the conservative processing of the call chain.
383 // The COPY can be located anywhere between the call-frame setup
384 // instruction and its first use. We use the call instruction as a boundary
385 // because it is usually cheaper to check if an instruction is a call than
386 // checking if an instruction uses a register.
387 for (auto J = I; !J->isCall(); ++J)
388 if (J->isCopy() && J->getOperand(0).isReg() && J->getOperand(1).isReg() &&
389 J->getOperand(1).getReg() == StackPtr) {
390 StackPtrCopyInst = J;
391 Context.SPCopy = &*J++;
392 StackPtr = Context.SPCopy->getOperand(0).getReg();
396 // Scan the call setup sequence for the pattern we're looking for.
397 // We only handle a simple case - a sequence of store instructions that
398 // push a sequence of stack-slot-aligned values onto the stack, with
399 // no gaps between them.
401 Context.ArgStoreVector.resize(MaxAdjust, nullptr);
403 DenseSet<unsigned int> UsedRegs;
405 for (InstClassification Classification = Skip; Classification != Exit; ++I) {
406 // If this is the COPY of the stack pointer, it's ok to ignore.
407 if (I == StackPtrCopyInst)
409 Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs);
410 if (Classification != Convert)
412 // We know the instruction has a supported store opcode.
413 // We only want movs of the form:
414 // mov imm/reg, k(%StackPtr)
415 // If we run into something else, bail.
416 // Note that AddrBaseReg may, counter to its name, not be a register,
417 // but rather a frame index.
418 // TODO: Support the fi case. This should probably work now that we
419 // have the infrastructure to track the stack pointer within a call
421 if (!I->getOperand(X86::AddrBaseReg).isReg() ||
422 (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) ||
423 !I->getOperand(X86::AddrScaleAmt).isImm() ||
424 (I->getOperand(X86::AddrScaleAmt).getImm() != 1) ||
425 (I->getOperand(X86::AddrIndexReg).getReg() != X86::NoRegister) ||
426 (I->getOperand(X86::AddrSegmentReg).getReg() != X86::NoRegister) ||
427 !I->getOperand(X86::AddrDisp).isImm())
430 int64_t StackDisp = I->getOperand(X86::AddrDisp).getImm();
431 assert(StackDisp >= 0 &&
432 "Negative stack displacement when passing parameters");
434 // We really don't want to consider the unaligned case.
435 if (StackDisp & (SlotSize - 1))
437 StackDisp >>= Log2SlotSize;
439 assert((size_t)StackDisp < Context.ArgStoreVector.size() &&
440 "Function call has more parameters than the stack is adjusted for.");
442 // If the same stack slot is being filled twice, something's fishy.
443 if (Context.ArgStoreVector[StackDisp] != nullptr)
445 Context.ArgStoreVector[StackDisp] = &*I;
447 for (const MachineOperand &MO : I->uses()) {
450 unsigned int Reg = MO.getReg();
451 if (RegInfo.isPhysicalRegister(Reg))
452 UsedRegs.insert(Reg);
458 // We now expect the end of the sequence. If we stopped early,
459 // or reached the end of the block without finding a call, bail.
460 if (I == MBB.end() || !I->isCall())
464 if ((++I)->getOpcode() != TII->getCallFrameDestroyOpcode())
467 // Now, go through the vector, and see that we don't have any gaps,
468 // but only a series of storing instructions.
469 auto MMI = Context.ArgStoreVector.begin(), MME = Context.ArgStoreVector.end();
470 for (; MMI != MME; ++MMI, Context.ExpectedDist += SlotSize)
474 // If the call had no parameters, do nothing
475 if (MMI == Context.ArgStoreVector.begin())
478 // We are either at the last parameter, or a gap.
479 // Make sure it's not a gap
480 for (; MMI != MME; ++MMI)
484 Context.UsePush = true;
487 void X86CallFrameOptimization::adjustCallSequence(MachineFunction &MF,
488 const CallContext &Context) {
489 // Ok, we can in fact do the transformation for this call.
490 // Do not remove the FrameSetup instruction, but adjust the parameters.
491 // PEI will end up finalizing the handling of this.
492 MachineBasicBlock::iterator FrameSetup = Context.FrameSetup;
493 MachineBasicBlock &MBB = *(FrameSetup->getParent());
494 TII->setFrameAdjustment(*FrameSetup, Context.ExpectedDist);
496 DebugLoc DL = FrameSetup->getDebugLoc();
497 bool Is64Bit = STI->is64Bit();
498 // Now, iterate through the vector in reverse order, and replace the store to
499 // stack with pushes. MOVmi/MOVmr doesn't have any defs, so no need to
501 for (int Idx = (Context.ExpectedDist >> Log2SlotSize) - 1; Idx >= 0; --Idx) {
502 MachineBasicBlock::iterator Store = *Context.ArgStoreVector[Idx];
503 MachineOperand PushOp = Store->getOperand(X86::AddrNumOperands);
504 MachineBasicBlock::iterator Push = nullptr;
506 switch (Store->getOpcode()) {
508 llvm_unreachable("Unexpected Opcode!");
517 PushOpcode = Is64Bit ? X86::PUSH64i32 : X86::PUSHi32;
518 // If the operand is a small (8-bit) immediate, we can use a
519 // PUSH instruction with a shorter encoding.
520 // Note that isImm() may fail even though this is a MOVmi, because
521 // the operand can also be a symbol.
522 if (PushOp.isImm()) {
523 int64_t Val = PushOp.getImm();
525 PushOpcode = Is64Bit ? X86::PUSH64i8 : X86::PUSH32i8;
527 Push = BuildMI(MBB, Context.Call, DL, TII->get(PushOpcode)).add(PushOp);
531 unsigned int Reg = PushOp.getReg();
533 // If storing a 32-bit vreg on 64-bit targets, extend to a 64-bit vreg
534 // in preparation for the PUSH64. The upper 32 bits can be undef.
535 if (Is64Bit && Store->getOpcode() == X86::MOV32mr) {
536 unsigned UndefReg = MRI->createVirtualRegister(&X86::GR64RegClass);
537 Reg = MRI->createVirtualRegister(&X86::GR64RegClass);
538 BuildMI(MBB, Context.Call, DL, TII->get(X86::IMPLICIT_DEF), UndefReg);
539 BuildMI(MBB, Context.Call, DL, TII->get(X86::INSERT_SUBREG), Reg)
542 .addImm(X86::sub_32bit);
545 // If PUSHrmm is not slow on this target, try to fold the source of the
546 // push into the instruction.
547 bool SlowPUSHrmm = STI->isAtom() || STI->isSLM();
549 // Check that this is legal to fold. Right now, we're extremely
550 // conservative about that.
551 MachineInstr *DefMov = nullptr;
552 if (!SlowPUSHrmm && (DefMov = canFoldIntoRegPush(FrameSetup, Reg))) {
553 PushOpcode = Is64Bit ? X86::PUSH64rmm : X86::PUSH32rmm;
554 Push = BuildMI(MBB, Context.Call, DL, TII->get(PushOpcode));
556 unsigned NumOps = DefMov->getDesc().getNumOperands();
557 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
558 Push->addOperand(DefMov->getOperand(i));
560 DefMov->eraseFromParent();
562 PushOpcode = Is64Bit ? X86::PUSH64r : X86::PUSH32r;
563 Push = BuildMI(MBB, Context.Call, DL, TII->get(PushOpcode))
571 // For debugging, when using SP-based CFA, we need to adjust the CFA
572 // offset after each push.
573 // TODO: This is needed only if we require precise CFA.
576 MBB, std::next(Push), DL,
577 MCCFIInstruction::createAdjustCfaOffset(nullptr, SlotSize));
582 // The stack-pointer copy is no longer used in the call sequences.
583 // There should not be any other users, but we can't commit to that, so:
584 if (Context.SPCopy && MRI->use_empty(Context.SPCopy->getOperand(0).getReg()))
585 Context.SPCopy->eraseFromParent();
587 // Once we've done this, we need to make sure PEI doesn't assume a reserved
589 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
590 FuncInfo->setHasPushSequences(true);
593 MachineInstr *X86CallFrameOptimization::canFoldIntoRegPush(
594 MachineBasicBlock::iterator FrameSetup, unsigned Reg) {
595 // Do an extremely restricted form of load folding.
596 // ISel will often create patterns like:
597 // movl 4(%edi), %eax
598 // movl 8(%edi), %ecx
599 // movl 12(%edi), %edx
600 // movl %edx, 8(%esp)
601 // movl %ecx, 4(%esp)
604 // Get rid of those with prejudice.
605 if (!TargetRegisterInfo::isVirtualRegister(Reg))
608 // Make sure this is the only use of Reg.
609 if (!MRI->hasOneNonDBGUse(Reg))
612 MachineInstr &DefMI = *MRI->getVRegDef(Reg);
614 // Make sure the def is a MOV from memory.
615 // If the def is in another block, give up.
616 if ((DefMI.getOpcode() != X86::MOV32rm &&
617 DefMI.getOpcode() != X86::MOV64rm) ||
618 DefMI.getParent() != FrameSetup->getParent())
621 // Make sure we don't have any instructions between DefMI and the
622 // push that make folding the load illegal.
623 for (MachineBasicBlock::iterator I = DefMI; I != FrameSetup; ++I)
624 if (I->isLoadFoldBarrier())
630 FunctionPass *llvm::createX86CallFrameOptimization() {
631 return new X86CallFrameOptimization();