1 //===- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file implements the lowering of LLVM calls to machine code calls for
14 //===----------------------------------------------------------------------===//
16 #include "X86CallLowering.h"
17 #include "X86CallingConv.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86RegisterInfo.h"
21 #include "X86Subtarget.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
27 #include "llvm/CodeGen/GlobalISel/Utils.h"
28 #include "llvm/CodeGen/LowLevelType.h"
29 #include "llvm/CodeGen/MachineBasicBlock.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineMemOperand.h"
34 #include "llvm/CodeGen/MachineOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/MachineValueType.h"
37 #include "llvm/CodeGen/TargetInstrInfo.h"
38 #include "llvm/CodeGen/TargetSubtargetInfo.h"
39 #include "llvm/CodeGen/ValueTypes.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/Value.h"
44 #include "llvm/MC/MCRegisterInfo.h"
45 #include "llvm/Support/LowLevelTypeImpl.h"
51 #include "X86GenCallingConv.inc"
53 X86CallLowering::X86CallLowering(const X86TargetLowering &TLI)
54 : CallLowering(&TLI) {}
56 bool X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
57 SmallVectorImpl<ArgInfo> &SplitArgs,
59 MachineRegisterInfo &MRI,
60 SplitArgTy PerformArgSplit) const {
61 const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
62 LLVMContext &Context = OrigArg.Ty->getContext();
64 SmallVector<EVT, 4> SplitVTs;
65 SmallVector<uint64_t, 4> Offsets;
66 ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
68 if (SplitVTs.size() != 1) {
69 // TODO: support struct/array split
74 unsigned NumParts = TLI.getNumRegisters(Context, VT);
77 // replace the original type ( pointer -> GPR ).
78 SplitArgs.emplace_back(OrigArg.Reg, VT.getTypeForEVT(Context),
79 OrigArg.Flags, OrigArg.IsFixed);
83 SmallVector<unsigned, 8> SplitRegs;
85 EVT PartVT = TLI.getRegisterType(Context, VT);
86 Type *PartTy = PartVT.getTypeForEVT(Context);
88 for (unsigned i = 0; i < NumParts; ++i) {
90 ArgInfo{MRI.createGenericVirtualRegister(getLLTForType(*PartTy, DL)),
91 PartTy, OrigArg.Flags};
92 SplitArgs.push_back(Info);
93 SplitRegs.push_back(Info.Reg);
96 PerformArgSplit(SplitRegs);
102 struct OutgoingValueHandler : public CallLowering::ValueHandler {
103 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
104 MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
105 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
106 DL(MIRBuilder.getMF().getDataLayout()),
107 STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {}
109 unsigned getStackAddress(uint64_t Size, int64_t Offset,
110 MachinePointerInfo &MPO) override {
111 LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
112 LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
113 unsigned SPReg = MRI.createGenericVirtualRegister(p0);
114 MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister());
116 unsigned OffsetReg = MRI.createGenericVirtualRegister(SType);
117 MIRBuilder.buildConstant(OffsetReg, Offset);
119 unsigned AddrReg = MRI.createGenericVirtualRegister(p0);
120 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
122 MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
126 void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
127 CCValAssign &VA) override {
128 MIB.addUse(PhysReg, RegState::Implicit);
129 unsigned ExtReg = extendRegister(ValVReg, VA);
130 MIRBuilder.buildCopy(PhysReg, ExtReg);
133 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
134 MachinePointerInfo &MPO, CCValAssign &VA) override {
135 unsigned ExtReg = extendRegister(ValVReg, VA);
136 auto MMO = MIRBuilder.getMF().getMachineMemOperand(
137 MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(),
139 MIRBuilder.buildStore(ExtReg, Addr, *MMO);
142 bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
143 CCValAssign::LocInfo LocInfo,
144 const CallLowering::ArgInfo &Info, CCState &State) override {
145 bool Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State);
146 StackSize = State.getNextStackOffset();
148 static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2,
149 X86::XMM3, X86::XMM4, X86::XMM5,
150 X86::XMM6, X86::XMM7};
152 NumXMMRegs = State.getFirstUnallocated(XMMArgRegs);
157 uint64_t getStackSize() { return StackSize; }
158 uint64_t getNumXmmRegs() { return NumXMMRegs; }
161 MachineInstrBuilder &MIB;
162 uint64_t StackSize = 0;
163 const DataLayout &DL;
164 const X86Subtarget &STI;
165 unsigned NumXMMRegs = 0;
168 } // end anonymous namespace
170 bool X86CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
171 const Value *Val, unsigned VReg) const {
172 assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
174 auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
177 MachineFunction &MF = MIRBuilder.getMF();
178 MachineRegisterInfo &MRI = MF.getRegInfo();
179 auto &DL = MF.getDataLayout();
180 const Function &F = MF.getFunction();
182 ArgInfo OrigArg{VReg, Val->getType()};
183 setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F);
185 SmallVector<ArgInfo, 8> SplitArgs;
186 if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
187 [&](ArrayRef<unsigned> Regs) {
188 MIRBuilder.buildUnmerge(Regs, VReg);
192 OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86);
193 if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
197 MIRBuilder.insertInstr(MIB);
203 struct IncomingValueHandler : public CallLowering::ValueHandler {
204 IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
205 CCAssignFn *AssignFn)
206 : ValueHandler(MIRBuilder, MRI, AssignFn),
207 DL(MIRBuilder.getMF().getDataLayout()) {}
209 unsigned getStackAddress(uint64_t Size, int64_t Offset,
210 MachinePointerInfo &MPO) override {
211 auto &MFI = MIRBuilder.getMF().getFrameInfo();
212 int FI = MFI.CreateFixedObject(Size, Offset, true);
213 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
215 unsigned AddrReg = MRI.createGenericVirtualRegister(
216 LLT::pointer(0, DL.getPointerSizeInBits(0)));
217 MIRBuilder.buildFrameIndex(AddrReg, FI);
221 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
222 MachinePointerInfo &MPO, CCValAssign &VA) override {
223 auto MMO = MIRBuilder.getMF().getMachineMemOperand(
224 MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size,
226 MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
229 void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
230 CCValAssign &VA) override {
231 markPhysRegUsed(PhysReg);
232 switch (VA.getLocInfo()) {
234 MIRBuilder.buildCopy(ValVReg, PhysReg);
236 case CCValAssign::LocInfo::SExt:
237 case CCValAssign::LocInfo::ZExt:
238 case CCValAssign::LocInfo::AExt: {
239 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
240 MIRBuilder.buildTrunc(ValVReg, Copy);
246 /// How the physical register gets marked varies between formal
247 /// parameters (it's a basic-block live-in), and a call instruction
248 /// (it's an implicit-def of the BL).
249 virtual void markPhysRegUsed(unsigned PhysReg) = 0;
252 const DataLayout &DL;
255 struct FormalArgHandler : public IncomingValueHandler {
256 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
257 CCAssignFn *AssignFn)
258 : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
260 void markPhysRegUsed(unsigned PhysReg) override {
261 MIRBuilder.getMBB().addLiveIn(PhysReg);
265 struct CallReturnHandler : public IncomingValueHandler {
266 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
267 CCAssignFn *AssignFn, MachineInstrBuilder &MIB)
268 : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
270 void markPhysRegUsed(unsigned PhysReg) override {
271 MIB.addDef(PhysReg, RegState::Implicit);
275 MachineInstrBuilder &MIB;
278 } // end anonymous namespace
280 bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
282 ArrayRef<unsigned> VRegs) const {
286 // TODO: handle variadic function
290 MachineFunction &MF = MIRBuilder.getMF();
291 MachineRegisterInfo &MRI = MF.getRegInfo();
292 auto DL = MF.getDataLayout();
294 SmallVector<ArgInfo, 8> SplitArgs;
296 for (auto &Arg : F.args()) {
298 // TODO: handle not simple cases.
299 if (Arg.hasAttribute(Attribute::ByVal) ||
300 Arg.hasAttribute(Attribute::InReg) ||
301 Arg.hasAttribute(Attribute::StructRet) ||
302 Arg.hasAttribute(Attribute::SwiftSelf) ||
303 Arg.hasAttribute(Attribute::SwiftError) ||
304 Arg.hasAttribute(Attribute::Nest))
307 ArgInfo OrigArg(VRegs[Idx], Arg.getType());
308 setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F);
309 if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
310 [&](ArrayRef<unsigned> Regs) {
311 MIRBuilder.buildMerge(VRegs[Idx], Regs);
317 MachineBasicBlock &MBB = MIRBuilder.getMBB();
319 MIRBuilder.setInstr(*MBB.begin());
321 FormalArgHandler Handler(MIRBuilder, MRI, CC_X86);
322 if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
325 // Move back to the end of the basic block.
326 MIRBuilder.setMBB(MBB);
331 bool X86CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
332 CallingConv::ID CallConv,
333 const MachineOperand &Callee,
334 const ArgInfo &OrigRet,
335 ArrayRef<ArgInfo> OrigArgs) const {
336 MachineFunction &MF = MIRBuilder.getMF();
337 const Function &F = MF.getFunction();
338 MachineRegisterInfo &MRI = MF.getRegInfo();
339 auto &DL = F.getParent()->getDataLayout();
340 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
341 const TargetInstrInfo &TII = *STI.getInstrInfo();
342 auto TRI = STI.getRegisterInfo();
344 // Handle only Linux C, X86_64_SysV calling conventions for now.
345 if (!STI.isTargetLinux() ||
346 !(CallConv == CallingConv::C || CallConv == CallingConv::X86_64_SysV))
349 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
350 auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
352 // Create a temporarily-floating call instruction so we can add the implicit
353 // uses of arg registers.
354 bool Is64Bit = STI.is64Bit();
355 unsigned CallOpc = Callee.isReg()
356 ? (Is64Bit ? X86::CALL64r : X86::CALL32r)
357 : (Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32);
359 auto MIB = MIRBuilder.buildInstrNoInsert(CallOpc).add(Callee).addRegMask(
360 TRI->getCallPreservedMask(MF, CallConv));
362 SmallVector<ArgInfo, 8> SplitArgs;
363 for (const auto &OrigArg : OrigArgs) {
365 // TODO: handle not simple cases.
366 if (OrigArg.Flags.isByVal())
369 if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
370 [&](ArrayRef<unsigned> Regs) {
371 MIRBuilder.buildUnmerge(Regs, OrigArg.Reg);
375 // Do the actual argument marshalling.
376 OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, CC_X86);
377 if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
380 bool IsFixed = OrigArgs.empty() ? true : OrigArgs.back().IsFixed;
381 if (STI.is64Bit() && !IsFixed && !STI.isCallingConvWin64(CallConv)) {
382 // From AMD64 ABI document:
383 // For calls that may call functions that use varargs or stdargs
384 // (prototype-less calls or calls to functions containing ellipsis (...) in
385 // the declaration) %al is used as hidden argument to specify the number
386 // of SSE registers used. The contents of %al do not need to match exactly
387 // the number of registers, but must be an ubound on the number of SSE
388 // registers used and is in the range 0 - 8 inclusive.
390 MIRBuilder.buildInstr(X86::MOV8ri)
392 .addImm(Handler.getNumXmmRegs());
393 MIB.addUse(X86::AL, RegState::Implicit);
396 // Now we can add the actual call instruction to the correct basic block.
397 MIRBuilder.insertInstr(MIB);
399 // If Callee is a reg, since it is used by a target specific
400 // instruction, it must have a register class matching the
401 // constraint of that instruction.
403 MIB->getOperand(0).setReg(constrainOperandRegClass(
404 MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
405 *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(),
406 Callee.getReg(), 0));
408 // Finally we can copy the returned value back into its virtual-register. In
409 // symmetry with the arguments, the physical register must be an
410 // implicit-define of the call instruction.
414 SmallVector<unsigned, 8> NewRegs;
416 if (!splitToValueTypes(OrigRet, SplitArgs, DL, MRI,
417 [&](ArrayRef<unsigned> Regs) {
418 NewRegs.assign(Regs.begin(), Regs.end());
422 CallReturnHandler Handler(MIRBuilder, MRI, RetCC_X86, MIB);
423 if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
426 if (!NewRegs.empty())
427 MIRBuilder.buildMerge(OrigRet.Reg, NewRegs);
430 CallSeqStart.addImm(Handler.getStackSize())
431 .addImm(0 /* see getFrameTotalSize */)
432 .addImm(0 /* see getFrameAdjustment */);
434 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
435 MIRBuilder.buildInstr(AdjStackUp)
436 .addImm(Handler.getStackSize())
437 .addImm(0 /* NumBytesForCalleeToPop */);