1 //===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("static_cast<const X86Subtarget&>"
18 "(State.getMachineFunction().getSubtarget()).", F),
21 // Register classes for RegCall
22 class RC_X86_RegCall {
23 list<Register> GPR_8 = [];
24 list<Register> GPR_16 = [];
25 list<Register> GPR_32 = [];
26 list<Register> GPR_64 = [];
27 list<Register> FP_CALL = [FP0];
28 list<Register> FP_RET = [FP0, FP1];
29 list<Register> XMM = [];
30 list<Register> YMM = [];
31 list<Register> ZMM = [];
34 // RegCall register classes for 32 bits
35 def RC_X86_32_RegCall : RC_X86_RegCall {
36 let GPR_8 = [AL, CL, DL, DIL, SIL];
37 let GPR_16 = [AX, CX, DX, DI, SI];
38 let GPR_32 = [EAX, ECX, EDX, EDI, ESI];
39 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle []
40 ///< \todo Fix AssignToReg to enable empty lists
41 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7];
42 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7];
43 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7];
46 class RC_X86_64_RegCall : RC_X86_RegCall {
47 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
48 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15];
49 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
50 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15];
51 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7,
52 ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15];
55 def RC_X86_64_RegCall_Win : RC_X86_64_RegCall {
56 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R10B, R11B, R12B, R14B, R15B];
57 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R10W, R11W, R12W, R14W, R15W];
58 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R10D, R11D, R12D, R14D, R15D];
59 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
62 def RC_X86_64_RegCall_SysV : RC_X86_64_RegCall {
63 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R12B, R13B, R14B, R15B];
64 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R12W, R13W, R14W, R15W];
65 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R12D, R13D, R14D, R15D];
66 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
69 // X86-64 Intel regcall calling convention.
70 multiclass X86_RegCall_base<RC_X86_RegCall RC> {
71 def CC_#NAME : CallingConv<[
72 // Handles byval parameters.
73 CCIfSubtarget<"is64Bit()", CCIfByVal<CCPassByVal<8, 8>>>,
74 CCIfByVal<CCPassByVal<4, 4>>,
76 // Promote i1/i8/i16/v1i1 arguments to i32.
77 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
79 // Promote v8i1/v16i1/v32i1 arguments to i32.
80 CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType<i32>>,
82 // bool, char, int, enum, long, pointer --> GPR
83 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>,
85 // long long, __int64 --> GPR
86 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>,
88 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32)
89 CCIfType<[v64i1], CCPromoteToType<i64>>,
90 CCIfSubtarget<"is64Bit()", CCIfType<[i64],
91 CCAssignToReg<RC.GPR_64>>>,
92 CCIfSubtarget<"is32Bit()", CCIfType<[i64],
93 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>,
95 // float, double, float128 --> XMM
96 // In the case of SSE disabled --> save to stack
97 CCIfType<[f32, f64, f128],
98 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
100 // long double --> FP
101 CCIfType<[f80], CCAssignToReg<RC.FP_CALL>>,
103 // __m128, __m128i, __m128d --> XMM
104 // In the case of SSE disabled --> save to stack
105 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
106 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
108 // __m256, __m256i, __m256d --> YMM
109 // In the case of SSE disabled --> save to stack
110 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
111 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>,
113 // __m512, __m512i, __m512d --> ZMM
114 // In the case of SSE disabled --> save to stack
115 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
116 CCIfSubtarget<"hasAVX512()",CCAssignToReg<RC.ZMM>>>,
118 // If no register was found -> assign to stack
120 // In 64 bit, assign 64/32 bit values to 8 byte stack
121 CCIfSubtarget<"is64Bit()", CCIfType<[i32, i64, f32, f64],
122 CCAssignToStack<8, 8>>>,
124 // In 32 bit, assign 64/32 bit values to 8/4 byte stack
125 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
126 CCIfType<[i64, f64], CCAssignToStack<8, 4>>,
128 // MMX type gets 8 byte slot in stack , while alignment depends on target
129 CCIfSubtarget<"is64Bit()", CCIfType<[x86mmx], CCAssignToStack<8, 8>>>,
130 CCIfType<[x86mmx], CCAssignToStack<8, 4>>,
132 // float 128 get stack slots whose size and alignment depends
134 CCIfType<[f80, f128], CCAssignToStack<0, 0>>,
136 // Vectors get 16-byte stack slots that are 16-byte aligned.
137 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
138 CCAssignToStack<16, 16>>,
140 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
141 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
142 CCAssignToStack<32, 32>>,
144 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
145 CCIfType<[v16i32, v8i64, v16f32, v8f64], CCAssignToStack<64, 64>>
148 def RetCC_#NAME : CallingConv<[
149 // Promote i1, v1i1, v8i1 arguments to i8.
150 CCIfType<[i1, v1i1, v8i1], CCPromoteToType<i8>>,
152 // Promote v16i1 arguments to i16.
153 CCIfType<[v16i1], CCPromoteToType<i16>>,
155 // Promote v32i1 arguments to i32.
156 CCIfType<[v32i1], CCPromoteToType<i32>>,
158 // bool, char, int, enum, long, pointer --> GPR
159 CCIfType<[i8], CCAssignToReg<RC.GPR_8>>,
160 CCIfType<[i16], CCAssignToReg<RC.GPR_16>>,
161 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>,
163 // long long, __int64 --> GPR
164 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>,
166 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32)
167 CCIfType<[v64i1], CCPromoteToType<i64>>,
168 CCIfSubtarget<"is64Bit()", CCIfType<[i64],
169 CCAssignToReg<RC.GPR_64>>>,
170 CCIfSubtarget<"is32Bit()", CCIfType<[i64],
171 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>,
173 // long double --> FP
174 CCIfType<[f80], CCAssignToReg<RC.FP_RET>>,
176 // float, double, float128 --> XMM
177 CCIfType<[f32, f64, f128],
178 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
180 // __m128, __m128i, __m128d --> XMM
181 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
182 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
184 // __m256, __m256i, __m256d --> YMM
185 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
186 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>,
188 // __m512, __m512i, __m512d --> ZMM
189 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
190 CCIfSubtarget<"hasAVX512()", CCAssignToReg<RC.ZMM>>>
194 //===----------------------------------------------------------------------===//
195 // Return Value Calling Conventions
196 //===----------------------------------------------------------------------===//
198 // Return-value conventions common to all X86 CC's.
199 def RetCC_X86Common : CallingConv<[
200 // Scalar values are returned in AX first, then DX. For i8, the ABI
201 // requires the values to be in AL and AH, however this code uses AL and DL
202 // instead. This is because using AH for the second register conflicts with
203 // the way LLVM does multiple return values -- a return of {i16,i8} would end
204 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI
205 // for functions that return two i8 values are currently expected to pack the
206 // values into an i16 (which uses AX, and thus AL:AH).
208 // For code that doesn't care about the ABI, we allow returning more than two
209 // integer values in registers.
210 CCIfType<[v1i1], CCPromoteToType<i8>>,
211 CCIfType<[i1], CCPromoteToType<i8>>,
212 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>,
213 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
214 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
215 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
217 // Boolean vectors of AVX-512 are returned in SIMD registers.
218 // The call from AVX to AVX-512 function should work,
219 // since the boolean types in AVX/AVX2 are promoted by default.
220 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
221 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
222 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
223 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
224 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
225 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
227 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3
228 // can only be used by ABI non-compliant code. If the target doesn't have XMM
229 // registers, it won't have vector types.
230 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
231 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
233 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3
234 // can only be used by ABI non-compliant code. This vector type is only
235 // supported while using the AVX target feature.
236 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
237 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
239 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3
240 // can only be used by ABI non-compliant code. This vector type is only
241 // supported while using the AVX-512 target feature.
242 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
243 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
245 // MMX vector types are always returned in MM0. If the target doesn't have
246 // MM0, it doesn't support these vector types.
247 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>,
249 // Long double types are always returned in FP0 (even with SSE).
250 CCIfType<[f80], CCAssignToReg<[FP0, FP1]>>
253 // X86-32 C return-value convention.
254 def RetCC_X86_32_C : CallingConv<[
255 // The X86-32 calling convention returns FP values in FP0, unless marked
256 // with "inreg" (used here to distinguish one kind of reg from another,
257 // weirdly; this is really the sse-regparm calling convention) in which
258 // case they use XMM0, otherwise it is the same as the common X86 calling
260 CCIfInReg<CCIfSubtarget<"hasSSE2()",
261 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
262 CCIfType<[f32,f64], CCAssignToReg<[FP0, FP1]>>,
263 CCDelegateTo<RetCC_X86Common>
266 // X86-32 FastCC return-value convention.
267 def RetCC_X86_32_Fast : CallingConv<[
268 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
270 // This can happen when a float, 2 x float, or 3 x float vector is split by
271 // target lowering, and is returned in 1-3 sse regs.
272 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
273 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
275 // For integers, ECX can be used as an extra return register
276 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,
277 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
278 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
280 // Otherwise, it is the same as the common X86 calling convention.
281 CCDelegateTo<RetCC_X86Common>
284 // Intel_OCL_BI return-value convention.
285 def RetCC_Intel_OCL_BI : CallingConv<[
286 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3.
287 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
288 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
290 // 256-bit FP vectors
291 // No more than 4 registers
292 CCIfType<[v8f32, v4f64, v8i32, v4i64],
293 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
295 // 512-bit FP vectors
296 CCIfType<[v16f32, v8f64, v16i32, v8i64],
297 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
299 // i32, i64 in the standard way
300 CCDelegateTo<RetCC_X86Common>
303 // X86-32 HiPE return-value convention.
304 def RetCC_X86_32_HiPE : CallingConv<[
305 // Promote all types to i32
306 CCIfType<[i8, i16], CCPromoteToType<i32>>,
308 // Return: HP, P, VAL1, VAL2
309 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>>
312 // X86-32 Vectorcall return-value convention.
313 def RetCC_X86_32_VectorCall : CallingConv<[
314 // Floating Point types are returned in XMM0,XMM1,XMMM2 and XMM3.
315 CCIfType<[f32, f64, f128],
316 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
318 // Return integers in the standard way.
319 CCDelegateTo<RetCC_X86Common>
322 // X86-64 C return-value convention.
323 def RetCC_X86_64_C : CallingConv<[
324 // The X86-64 calling convention always returns FP values in XMM0.
325 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
326 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
327 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1]>>,
329 // MMX vector types are always returned in XMM0.
330 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>,
332 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
334 CCDelegateTo<RetCC_X86Common>
337 // X86-Win64 C return-value convention.
338 def RetCC_X86_Win64_C : CallingConv<[
339 // The X86-Win64 calling convention always returns __m64 values in RAX.
340 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
342 // Otherwise, everything is the same as 'normal' X86-64 C CC.
343 CCDelegateTo<RetCC_X86_64_C>
346 // X86-64 vectorcall return-value convention.
347 def RetCC_X86_64_Vectorcall : CallingConv<[
348 // Vectorcall calling convention always returns FP values in XMMs.
349 CCIfType<[f32, f64, f128],
350 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
352 // Otherwise, everything is the same as Windows X86-64 C CC.
353 CCDelegateTo<RetCC_X86_Win64_C>
356 // X86-64 HiPE return-value convention.
357 def RetCC_X86_64_HiPE : CallingConv<[
358 // Promote all types to i64
359 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
361 // Return: HP, P, VAL1, VAL2
362 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
365 // X86-64 WebKit_JS return-value convention.
366 def RetCC_X86_64_WebKit_JS : CallingConv<[
367 // Promote all types to i64
368 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
371 CCIfType<[i64], CCAssignToReg<[RAX]>>
374 def RetCC_X86_64_Swift : CallingConv<[
376 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
378 // For integers, ECX, R8D can be used as extra return registers.
379 CCIfType<[v1i1], CCPromoteToType<i8>>,
380 CCIfType<[i1], CCPromoteToType<i8>>,
381 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL, R8B]>>,
382 CCIfType<[i16], CCAssignToReg<[AX, DX, CX, R8W]>>,
383 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX, R8D]>>,
384 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>,
386 // XMM0, XMM1, XMM2 and XMM3 can be used to return FP values.
387 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
388 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
389 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
391 // MMX vector types are returned in XMM0, XMM1, XMM2 and XMM3.
392 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
393 CCDelegateTo<RetCC_X86Common>
396 // X86-64 AnyReg return-value convention. No explicit register is specified for
397 // the return-value. The register allocator is allowed and expected to choose
398 // any free register.
400 // This calling convention is currently only supported by the stackmap and
401 // patchpoint intrinsics. All other uses will result in an assert on Debug
402 // builds. On Release builds we fallback to the X86 C calling convention.
403 def RetCC_X86_64_AnyReg : CallingConv<[
404 CCCustom<"CC_X86_AnyReg_Error">
407 // X86-64 HHVM return-value convention.
408 def RetCC_X86_64_HHVM: CallingConv<[
409 // Promote all types to i64
410 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
412 // Return: could return in any GP register save RSP and R12.
413 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
414 RAX, R10, R11, R13, R14, R15]>>
418 defm X86_32_RegCall :
419 X86_RegCall_base<RC_X86_32_RegCall>;
420 defm X86_Win64_RegCall :
421 X86_RegCall_base<RC_X86_64_RegCall_Win>;
422 defm X86_SysV64_RegCall :
423 X86_RegCall_base<RC_X86_64_RegCall_SysV>;
425 // This is the root return-value convention for the X86-32 backend.
426 def RetCC_X86_32 : CallingConv<[
427 // If FastCC, use RetCC_X86_32_Fast.
428 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
429 // If HiPE, use RetCC_X86_32_HiPE.
430 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>,
431 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_32_VectorCall>>,
432 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_32_RegCall>>,
434 // Otherwise, use RetCC_X86_32_C.
435 CCDelegateTo<RetCC_X86_32_C>
438 // This is the root return-value convention for the X86-64 backend.
439 def RetCC_X86_64 : CallingConv<[
440 // HiPE uses RetCC_X86_64_HiPE
441 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>,
443 // Handle JavaScript calls.
444 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<RetCC_X86_64_WebKit_JS>>,
445 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_X86_64_AnyReg>>,
447 // Handle Swift calls.
448 CCIfCC<"CallingConv::Swift", CCDelegateTo<RetCC_X86_64_Swift>>,
450 // Handle explicit CC selection
451 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<RetCC_X86_Win64_C>>,
452 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>,
454 // Handle Vectorcall CC
455 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_64_Vectorcall>>,
457 // Handle HHVM calls.
458 CCIfCC<"CallingConv::HHVM", CCDelegateTo<RetCC_X86_64_HHVM>>,
460 CCIfCC<"CallingConv::X86_RegCall",
461 CCIfSubtarget<"isTargetWin64()",
462 CCDelegateTo<RetCC_X86_Win64_RegCall>>>,
463 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_SysV64_RegCall>>,
465 // Mingw64 and native Win64 use Win64 CC
466 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
468 // Otherwise, drop to normal X86-64 CC
469 CCDelegateTo<RetCC_X86_64_C>
472 // This is the return-value convention used for the entire X86 backend.
473 def RetCC_X86 : CallingConv<[
475 // Check if this is the Intel OpenCL built-ins calling convention
476 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>,
478 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
479 CCDelegateTo<RetCC_X86_32>
482 //===----------------------------------------------------------------------===//
483 // X86-64 Argument Calling Conventions
484 //===----------------------------------------------------------------------===//
486 def CC_X86_64_C : CallingConv<[
487 // Handles byval parameters.
488 CCIfByVal<CCPassByVal<8, 8>>,
490 // Promote i1/i8/i16/v1i1 arguments to i32.
491 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
493 // The 'nest' parameter, if any, is passed in R10.
494 CCIfNest<CCIfSubtarget<"isTarget64BitILP32()", CCAssignToReg<[R10D]>>>,
495 CCIfNest<CCAssignToReg<[R10]>>,
497 // Pass SwiftSelf in a callee saved register.
498 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>,
500 // A SwiftError is passed in R12.
501 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
503 // For Swift Calling Convention, pass sret in %RAX.
504 CCIfCC<"CallingConv::Swift",
505 CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>,
507 // The first 6 integer arguments are passed in integer registers.
508 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
509 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
511 // The first 8 MMX vector arguments are passed in XMM registers on Darwin.
513 CCIfSubtarget<"isTargetDarwin()",
514 CCIfSubtarget<"hasSSE2()",
515 CCPromoteToType<v2i64>>>>,
517 // Boolean vectors of AVX-512 are passed in SIMD registers.
518 // The call from AVX to AVX-512 function should work,
519 // since the boolean types in AVX/AVX2 are promoted by default.
520 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
521 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
522 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
523 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
524 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
525 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
527 // The first 8 FP/Vector arguments are passed in XMM registers.
528 CCIfType<[f32, f64, f128, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
529 CCIfSubtarget<"hasSSE1()",
530 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
532 // The first 8 256-bit vector arguments are passed in YMM registers, unless
533 // this is a vararg function.
534 // FIXME: This isn't precisely correct; the x86-64 ABI document says that
535 // fixed arguments to vararg functions are supposed to be passed in
536 // registers. Actually modeling that would be a lot of work, though.
537 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
538 CCIfSubtarget<"hasFp256()",
539 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3,
540 YMM4, YMM5, YMM6, YMM7]>>>>,
542 // The first 8 512-bit vector arguments are passed in ZMM registers.
543 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
544 CCIfSubtarget<"hasAVX512()",
545 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>,
547 // Integer/FP values get stored in stack slots that are 8 bytes in size and
548 // 8-byte aligned if there are no more registers to hold them.
549 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
551 // Long doubles get stack slots whose size and alignment depends on the
553 CCIfType<[f80, f128], CCAssignToStack<0, 0>>,
555 // Vectors get 16-byte stack slots that are 16-byte aligned.
556 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
558 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
559 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
560 CCAssignToStack<32, 32>>,
562 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
563 CCIfType<[v16i32, v8i64, v16f32, v8f64],
564 CCAssignToStack<64, 64>>
567 // Calling convention for X86-64 HHVM.
568 def CC_X86_64_HHVM : CallingConv<[
569 // Use all/any GP registers for args, except RSP.
570 CCIfType<[i64], CCAssignToReg<[RBX, R12, RBP, R15,
571 RDI, RSI, RDX, RCX, R8, R9,
572 RAX, R10, R11, R13, R14]>>
575 // Calling convention for helper functions in HHVM.
576 def CC_X86_64_HHVM_C : CallingConv<[
577 // Pass the first argument in RBP.
578 CCIfType<[i64], CCAssignToReg<[RBP]>>,
580 // Otherwise it's the same as the regular C calling convention.
581 CCDelegateTo<CC_X86_64_C>
584 // Calling convention used on Win64
585 def CC_X86_Win64_C : CallingConv<[
586 // FIXME: Handle byval stuff.
587 // FIXME: Handle varargs.
589 // Promote i1/i8/i16/v1i1 arguments to i32.
590 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
592 // The 'nest' parameter, if any, is passed in R10.
593 CCIfNest<CCAssignToReg<[R10]>>,
595 // 128 bit vectors are passed by pointer
596 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
599 // 256 bit vectors are passed by pointer
600 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
602 // 512 bit vectors are passed by pointer
603 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
605 // The first 4 MMX vector arguments are passed in GPRs.
606 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
608 // The first 4 integer arguments are passed in integer registers.
609 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
610 [XMM0, XMM1, XMM2, XMM3]>>,
612 // Do not pass the sret argument in RCX, the Win64 thiscall calling
613 // convention requires "this" to be passed in RCX.
614 CCIfCC<"CallingConv::X86_ThisCall",
615 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
616 [XMM1, XMM2, XMM3]>>>>,
618 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
619 [XMM0, XMM1, XMM2, XMM3]>>,
621 // The first 4 FP/Vector arguments are passed in XMM registers.
622 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
623 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
624 [RCX , RDX , R8 , R9 ]>>,
626 // Integer/FP values get stored in stack slots that are 8 bytes in size and
627 // 8-byte aligned if there are no more registers to hold them.
628 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
630 // Long doubles get stack slots whose size and alignment depends on the
632 CCIfType<[f80], CCAssignToStack<0, 0>>
635 def CC_X86_Win64_VectorCall : CallingConv<[
636 CCCustom<"CC_X86_64_VectorCall">,
638 // Delegate to fastcall to handle integer types.
639 CCDelegateTo<CC_X86_Win64_C>
643 def CC_X86_64_GHC : CallingConv<[
644 // Promote i8/i16/i32 arguments to i64.
645 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
647 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
649 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
651 // Pass in STG registers: F1, F2, F3, F4, D1, D2
652 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
653 CCIfSubtarget<"hasSSE1()",
654 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
657 def CC_X86_64_HiPE : CallingConv<[
658 // Promote i8/i16/i32 arguments to i64.
659 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
661 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3
662 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
664 // Integer/FP values get stored in stack slots that are 8 bytes in size and
665 // 8-byte aligned if there are no more registers to hold them.
666 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>
669 def CC_X86_64_WebKit_JS : CallingConv<[
670 // Promote i8/i16 arguments to i32.
671 CCIfType<[i8, i16], CCPromoteToType<i32>>,
673 // Only the first integer argument is passed in register.
674 CCIfType<[i32], CCAssignToReg<[EAX]>>,
675 CCIfType<[i64], CCAssignToReg<[RAX]>>,
677 // The remaining integer arguments are passed on the stack. 32bit integer and
678 // floating-point arguments are aligned to 4 byte and stored in 4 byte slots.
679 // 64bit integer and floating-point arguments are aligned to 8 byte and stored
680 // in 8 byte stack slots.
681 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
682 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
685 // No explicit register is specified for the AnyReg calling convention. The
686 // register allocator may assign the arguments to any free register.
688 // This calling convention is currently only supported by the stackmap and
689 // patchpoint intrinsics. All other uses will result in an assert on Debug
690 // builds. On Release builds we fallback to the X86 C calling convention.
691 def CC_X86_64_AnyReg : CallingConv<[
692 CCCustom<"CC_X86_AnyReg_Error">
695 //===----------------------------------------------------------------------===//
696 // X86 C Calling Convention
697 //===----------------------------------------------------------------------===//
699 /// CC_X86_32_Vector_Common - In all X86-32 calling conventions, extra vector
700 /// values are spilled on the stack.
701 def CC_X86_32_Vector_Common : CallingConv<[
702 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
703 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
705 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned.
706 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
707 CCAssignToStack<32, 32>>,
709 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
710 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
711 CCAssignToStack<64, 64>>
714 // CC_X86_32_Vector_Standard - The first 3 vector arguments are passed in
716 def CC_X86_32_Vector_Standard : CallingConv<[
717 // SSE vector arguments are passed in XMM registers.
718 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
719 CCAssignToReg<[XMM0, XMM1, XMM2]>>>,
721 // AVX 256-bit vector arguments are passed in YMM registers.
722 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
723 CCIfSubtarget<"hasFp256()",
724 CCAssignToReg<[YMM0, YMM1, YMM2]>>>>,
726 // AVX 512-bit vector arguments are passed in ZMM registers.
727 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
728 CCAssignToReg<[ZMM0, ZMM1, ZMM2]>>>,
730 CCDelegateTo<CC_X86_32_Vector_Common>
733 // CC_X86_32_Vector_Darwin - The first 4 vector arguments are passed in
735 def CC_X86_32_Vector_Darwin : CallingConv<[
736 // SSE vector arguments are passed in XMM registers.
737 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
738 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
740 // AVX 256-bit vector arguments are passed in YMM registers.
741 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
742 CCIfSubtarget<"hasFp256()",
743 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>,
745 // AVX 512-bit vector arguments are passed in ZMM registers.
746 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
747 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>>,
749 CCDelegateTo<CC_X86_32_Vector_Common>
752 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
753 /// values are spilled on the stack.
754 def CC_X86_32_Common : CallingConv<[
755 // Handles byval parameters.
756 CCIfByVal<CCPassByVal<4, 4>>,
758 // The first 3 float or double arguments, if marked 'inreg' and if the call
759 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
760 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
761 CCIfSubtarget<"hasSSE2()",
762 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
764 // The first 3 __m64 vector arguments are passed in mmx registers if the
765 // call is not a vararg call.
766 CCIfNotVarArg<CCIfType<[x86mmx],
767 CCAssignToReg<[MM0, MM1, MM2]>>>,
769 // Integer/Float values get stored in stack slots that are 4 bytes in
770 // size and 4-byte aligned.
771 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
773 // Doubles get 8-byte slots that are 4-byte aligned.
774 CCIfType<[f64], CCAssignToStack<8, 4>>,
776 // Long doubles get slots whose size depends on the subtarget.
777 CCIfType<[f80], CCAssignToStack<0, 4>>,
779 // Boolean vectors of AVX-512 are passed in SIMD registers.
780 // The call from AVX to AVX-512 function should work,
781 // since the boolean types in AVX/AVX2 are promoted by default.
782 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
783 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
784 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
785 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
786 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
787 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
789 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
790 // passed in the parameter area.
791 CCIfType<[x86mmx], CCAssignToStack<8, 4>>,
793 // Darwin passes vectors in a form that differs from the i386 psABI
794 CCIfSubtarget<"isTargetDarwin()", CCDelegateTo<CC_X86_32_Vector_Darwin>>,
796 // Otherwise, drop to 'normal' X86-32 CC
797 CCDelegateTo<CC_X86_32_Vector_Standard>
800 def CC_X86_32_C : CallingConv<[
801 // Promote i1/i8/i16/v1i1 arguments to i32.
802 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
804 // The 'nest' parameter, if any, is passed in ECX.
805 CCIfNest<CCAssignToReg<[ECX]>>,
807 // The first 3 integer arguments, if marked 'inreg' and if the call is not
808 // a vararg call, are passed in integer registers.
809 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
811 // Otherwise, same as everything else.
812 CCDelegateTo<CC_X86_32_Common>
815 def CC_X86_32_MCU : CallingConv<[
816 // Handles byval parameters. Note that, like FastCC, we can't rely on
817 // the delegation to CC_X86_32_Common because that happens after code that
818 // puts arguments in registers.
819 CCIfByVal<CCPassByVal<4, 4>>,
821 // Promote i1/i8/i16/v1i1 arguments to i32.
822 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
824 // If the call is not a vararg call, some arguments may be passed
825 // in integer registers.
826 CCIfNotVarArg<CCIfType<[i32], CCCustom<"CC_X86_32_MCUInReg">>>,
828 // Otherwise, same as everything else.
829 CCDelegateTo<CC_X86_32_Common>
832 def CC_X86_32_FastCall : CallingConv<[
833 // Promote i1/i8/i16/v1i1 arguments to i32.
834 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
836 // The 'nest' parameter, if any, is passed in EAX.
837 CCIfNest<CCAssignToReg<[EAX]>>,
839 // The first 2 integer arguments are passed in ECX/EDX
840 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>,
842 // Otherwise, same as everything else.
843 CCDelegateTo<CC_X86_32_Common>
846 def CC_X86_Win32_VectorCall : CallingConv<[
847 // Pass floating point in XMMs
848 CCCustom<"CC_X86_32_VectorCall">,
850 // Delegate to fastcall to handle integer types.
851 CCDelegateTo<CC_X86_32_FastCall>
854 def CC_X86_32_ThisCall_Common : CallingConv<[
855 // The first integer argument is passed in ECX
856 CCIfType<[i32], CCAssignToReg<[ECX]>>,
858 // Otherwise, same as everything else.
859 CCDelegateTo<CC_X86_32_Common>
862 def CC_X86_32_ThisCall_Mingw : CallingConv<[
863 // Promote i1/i8/i16/v1i1 arguments to i32.
864 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
866 CCDelegateTo<CC_X86_32_ThisCall_Common>
869 def CC_X86_32_ThisCall_Win : CallingConv<[
870 // Promote i1/i8/i16/v1i1 arguments to i32.
871 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
873 // Pass sret arguments indirectly through stack.
874 CCIfSRet<CCAssignToStack<4, 4>>,
876 CCDelegateTo<CC_X86_32_ThisCall_Common>
879 def CC_X86_32_ThisCall : CallingConv<[
880 CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>,
881 CCDelegateTo<CC_X86_32_ThisCall_Win>
884 def CC_X86_32_FastCC : CallingConv<[
885 // Handles byval parameters. Note that we can't rely on the delegation
886 // to CC_X86_32_Common for this because that happens after code that
887 // puts arguments in registers.
888 CCIfByVal<CCPassByVal<4, 4>>,
890 // Promote i1/i8/i16/v1i1 arguments to i32.
891 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
893 // The 'nest' parameter, if any, is passed in EAX.
894 CCIfNest<CCAssignToReg<[EAX]>>,
896 // The first 2 integer arguments are passed in ECX/EDX
897 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
899 // The first 3 float or double arguments, if the call is not a vararg
900 // call and if SSE2 is available, are passed in SSE registers.
901 CCIfNotVarArg<CCIfType<[f32,f64],
902 CCIfSubtarget<"hasSSE2()",
903 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
905 // Doubles get 8-byte slots that are 8-byte aligned.
906 CCIfType<[f64], CCAssignToStack<8, 8>>,
908 // Otherwise, same as everything else.
909 CCDelegateTo<CC_X86_32_Common>
912 def CC_X86_32_GHC : CallingConv<[
913 // Promote i8/i16 arguments to i32.
914 CCIfType<[i8, i16], CCPromoteToType<i32>>,
916 // Pass in STG registers: Base, Sp, Hp, R1
917 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>>
920 def CC_X86_32_HiPE : CallingConv<[
921 // Promote i8/i16 arguments to i32.
922 CCIfType<[i8, i16], CCPromoteToType<i32>>,
924 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2
925 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>,
927 // Integer/Float values get stored in stack slots that are 4 bytes in
928 // size and 4-byte aligned.
929 CCIfType<[i32, f32], CCAssignToStack<4, 4>>
932 // X86-64 Intel OpenCL built-ins calling convention.
933 def CC_Intel_OCL_BI : CallingConv<[
935 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>,
936 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>,
938 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>,
939 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
941 CCIfType<[i32], CCAssignToStack<4, 4>>,
943 // The SSE vector arguments are passed in XMM registers.
944 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
945 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
947 // The 256-bit vector arguments are passed in YMM registers.
948 CCIfType<[v8f32, v4f64, v8i32, v4i64],
949 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>,
951 // The 512-bit vector arguments are passed in ZMM registers.
952 CCIfType<[v16f32, v8f64, v16i32, v8i64],
953 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>,
955 // Pass masks in mask registers
956 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>,
958 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
959 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>,
960 CCDelegateTo<CC_X86_32_C>
963 def CC_X86_32_Intr : CallingConv<[
964 CCAssignToStack<4, 4>
967 def CC_X86_64_Intr : CallingConv<[
968 CCAssignToStack<8, 8>
971 //===----------------------------------------------------------------------===//
972 // X86 Root Argument Calling Conventions
973 //===----------------------------------------------------------------------===//
975 // This is the root argument convention for the X86-32 backend.
976 def CC_X86_32 : CallingConv<[
977 // X86_INTR calling convention is valid in MCU target and should override the
978 // MCU calling convention. Thus, this should be checked before isTargetMCU().
979 CCIfCC<"CallingConv::X86_INTR", CCDelegateTo<CC_X86_32_Intr>>,
980 CCIfSubtarget<"isTargetMCU()", CCDelegateTo<CC_X86_32_MCU>>,
981 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>,
982 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win32_VectorCall>>,
983 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>,
984 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>,
985 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>,
986 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>,
987 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_32_RegCall>>,
989 // Otherwise, drop to normal X86-32 CC
990 CCDelegateTo<CC_X86_32_C>
993 // This is the root argument convention for the X86-64 backend.
994 def CC_X86_64 : CallingConv<[
995 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>,
996 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>,
997 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<CC_X86_64_WebKit_JS>>,
998 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_X86_64_AnyReg>>,
999 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<CC_X86_Win64_C>>,
1000 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>,
1001 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win64_VectorCall>>,
1002 CCIfCC<"CallingConv::HHVM", CCDelegateTo<CC_X86_64_HHVM>>,
1003 CCIfCC<"CallingConv::HHVM_C", CCDelegateTo<CC_X86_64_HHVM_C>>,
1004 CCIfCC<"CallingConv::X86_RegCall",
1005 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_RegCall>>>,
1006 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_SysV64_RegCall>>,
1007 CCIfCC<"CallingConv::X86_INTR", CCDelegateTo<CC_X86_64_Intr>>,
1009 // Mingw64 and native Win64 use Win64 CC
1010 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
1012 // Otherwise, drop to normal X86-64 CC
1013 CCDelegateTo<CC_X86_64_C>
1016 // This is the argument convention used for the entire X86 backend.
1017 def CC_X86 : CallingConv<[
1018 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>,
1019 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>,
1020 CCDelegateTo<CC_X86_32>
1023 //===----------------------------------------------------------------------===//
1024 // Callee-saved Registers.
1025 //===----------------------------------------------------------------------===//
1027 def CSR_NoRegs : CalleeSavedRegs<(add)>;
1029 def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
1030 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
1032 def CSR_64_SwiftError : CalleeSavedRegs<(sub CSR_64, R12)>;
1034 def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>;
1035 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
1037 def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>;
1039 def CSR_Win64 : CalleeSavedRegs<(add CSR_Win64_NoSSE,
1040 (sequence "XMM%u", 6, 15))>;
1042 // The function used by Darwin to obtain the address of a thread-local variable
1043 // uses rdi to pass a single parameter and rax for the return value. All other
1044 // GPRs are preserved.
1045 def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI,
1048 // CSRs that are handled by prologue, epilogue.
1049 def CSR_64_CXX_TLS_Darwin_PE : CalleeSavedRegs<(add RBP)>;
1051 // CSRs that are handled explicitly via copies.
1052 def CSR_64_CXX_TLS_Darwin_ViaCopy : CalleeSavedRegs<(sub CSR_64_TLS_Darwin, RBP)>;
1054 // All GPRs - except r11
1055 def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI,
1058 // All registers - except r11
1059 def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
1060 (sequence "XMM%u", 0, 15))>;
1061 def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
1062 (sequence "YMM%u", 0, 15))>;
1064 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
1065 R11, R12, R13, R14, R15, RBP,
1066 (sequence "XMM%u", 0, 15))>;
1068 def CSR_32_AllRegs : CalleeSavedRegs<(add EAX, EBX, ECX, EDX, EBP, ESI,
1070 def CSR_32_AllRegs_SSE : CalleeSavedRegs<(add CSR_32_AllRegs,
1071 (sequence "XMM%u", 0, 7))>;
1072 def CSR_32_AllRegs_AVX : CalleeSavedRegs<(add CSR_32_AllRegs,
1073 (sequence "YMM%u", 0, 7))>;
1074 def CSR_32_AllRegs_AVX512 : CalleeSavedRegs<(add CSR_32_AllRegs,
1075 (sequence "ZMM%u", 0, 7),
1076 (sequence "K%u", 0, 7))>;
1078 def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX)>;
1079 def CSR_64_AllRegs_NoSSE : CalleeSavedRegs<(add RAX, RBX, RCX, RDX, RSI, RDI, R8, R9,
1080 R10, R11, R12, R13, R14, R15, RBP)>;
1081 def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX,
1082 (sequence "YMM%u", 0, 15)),
1083 (sequence "XMM%u", 0, 15))>;
1084 def CSR_64_AllRegs_AVX512 : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX,
1085 (sequence "ZMM%u", 0, 31),
1086 (sequence "K%u", 0, 7)),
1087 (sequence "XMM%u", 0, 15))>;
1089 // Standard C + YMM6-15
1090 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
1092 (sequence "YMM%u", 6, 15))>;
1094 def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI,
1096 (sequence "ZMM%u", 6, 21),
1098 //Standard C + XMM 8-15
1099 def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64,
1100 (sequence "XMM%u", 8, 15))>;
1102 //Standard C + YMM 8-15
1103 def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64,
1104 (sequence "YMM%u", 8, 15))>;
1106 def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15,
1107 (sequence "ZMM%u", 16, 31),
1110 // Only R12 is preserved for PHP calls in HHVM.
1111 def CSR_64_HHVM : CalleeSavedRegs<(add R12)>;
1113 // Register calling convention preserves few GPR and XMM8-15
1114 def CSR_32_RegCall_NoSSE : CalleeSavedRegs<(add ESI, EDI, EBX, EBP, ESP)>;
1115 def CSR_32_RegCall : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE,
1116 (sequence "XMM%u", 4, 7))>;
1117 def CSR_Win64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, RSP,
1118 (sequence "R%u", 10, 15))>;
1119 def CSR_Win64_RegCall : CalleeSavedRegs<(add CSR_Win64_RegCall_NoSSE,
1120 (sequence "XMM%u", 8, 15))>;
1121 def CSR_SysV64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, RSP,
1122 (sequence "R%u", 12, 15))>;
1123 def CSR_SysV64_RegCall : CalleeSavedRegs<(add CSR_SysV64_RegCall_NoSSE,
1124 (sequence "XMM%u", 8, 15))>;