1 //===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("static_cast<const X86Subtarget&>"
18 "(State.getMachineFunction().getSubtarget()).", F),
21 // Register classes for RegCall
22 class RC_X86_RegCall {
23 list<Register> GPR_8 = [];
24 list<Register> GPR_16 = [];
25 list<Register> GPR_32 = [];
26 list<Register> GPR_64 = [];
27 list<Register> FP_CALL = [FP0];
28 list<Register> FP_RET = [FP0, FP1];
29 list<Register> XMM = [];
30 list<Register> YMM = [];
31 list<Register> ZMM = [];
34 // RegCall register classes for 32 bits
35 def RC_X86_32_RegCall : RC_X86_RegCall {
36 let GPR_8 = [AL, CL, DL, DIL, SIL];
37 let GPR_16 = [AX, CX, DX, DI, SI];
38 let GPR_32 = [EAX, ECX, EDX, EDI, ESI];
39 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle []
40 ///< \todo Fix AssignToReg to enable empty lists
41 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7];
42 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7];
43 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7];
46 class RC_X86_64_RegCall : RC_X86_RegCall {
47 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
48 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15];
49 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
50 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15];
51 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7,
52 ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15];
55 def RC_X86_64_RegCall_Win : RC_X86_64_RegCall {
56 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R10B, R11B, R12B, R14B, R15B];
57 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R10W, R11W, R12W, R14W, R15W];
58 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R10D, R11D, R12D, R14D, R15D];
59 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
62 def RC_X86_64_RegCall_SysV : RC_X86_64_RegCall {
63 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R12B, R13B, R14B, R15B];
64 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R12W, R13W, R14W, R15W];
65 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R12D, R13D, R14D, R15D];
66 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
69 // X86-64 Intel regcall calling convention.
70 multiclass X86_RegCall_base<RC_X86_RegCall RC> {
71 def CC_#NAME : CallingConv<[
72 // Handles byval parameters.
73 CCIfSubtarget<"is64Bit()", CCIfByVal<CCPassByVal<8, 8>>>,
74 CCIfByVal<CCPassByVal<4, 4>>,
76 // Promote i1/i8/i16 arguments to i32.
77 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
79 // Promote v8i1/v16i1/v32i1 arguments to i32.
80 CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType<i32>>,
82 // bool, char, int, enum, long, pointer --> GPR
83 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>,
85 // long long, __int64 --> GPR
86 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>,
88 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32)
89 CCIfType<[v64i1], CCPromoteToType<i64>>,
90 CCIfSubtarget<"is64Bit()", CCIfType<[i64],
91 CCAssignToReg<RC.GPR_64>>>,
92 CCIfSubtarget<"is32Bit()", CCIfType<[i64],
93 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>,
95 // float, double, float128 --> XMM
96 // In the case of SSE disabled --> save to stack
97 CCIfType<[f32, f64, f128],
98 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
100 // long double --> FP
101 CCIfType<[f80], CCAssignToReg<RC.FP_CALL>>,
103 // __m128, __m128i, __m128d --> XMM
104 // In the case of SSE disabled --> save to stack
105 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
106 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
108 // __m256, __m256i, __m256d --> YMM
109 // In the case of SSE disabled --> save to stack
110 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
111 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>,
113 // __m512, __m512i, __m512d --> ZMM
114 // In the case of SSE disabled --> save to stack
115 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
116 CCIfSubtarget<"hasAVX512()",CCAssignToReg<RC.ZMM>>>,
118 // If no register was found -> assign to stack
120 // In 64 bit, assign 64/32 bit values to 8 byte stack
121 CCIfSubtarget<"is64Bit()", CCIfType<[i32, i64, f32, f64],
122 CCAssignToStack<8, 8>>>,
124 // In 32 bit, assign 64/32 bit values to 8/4 byte stack
125 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
126 CCIfType<[i64, f64], CCAssignToStack<8, 4>>,
128 // MMX type gets 8 byte slot in stack , while alignment depends on target
129 CCIfSubtarget<"is64Bit()", CCIfType<[x86mmx], CCAssignToStack<8, 8>>>,
130 CCIfType<[x86mmx], CCAssignToStack<8, 4>>,
132 // float 128 get stack slots whose size and alignment depends
134 CCIfType<[f80, f128], CCAssignToStack<0, 0>>,
136 // Vectors get 16-byte stack slots that are 16-byte aligned.
137 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
138 CCAssignToStack<16, 16>>,
140 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
141 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
142 CCAssignToStack<32, 32>>,
144 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
145 CCIfType<[v16i32, v8i64, v16f32, v8f64], CCAssignToStack<64, 64>>
148 def RetCC_#NAME : CallingConv<[
149 // Promote i1, v8i1 arguments to i8.
150 CCIfType<[i1, v8i1], CCPromoteToType<i8>>,
152 // Promote v16i1 arguments to i16.
153 CCIfType<[v16i1], CCPromoteToType<i16>>,
155 // Promote v32i1 arguments to i32.
156 CCIfType<[v32i1], CCPromoteToType<i32>>,
158 // bool, char, int, enum, long, pointer --> GPR
159 CCIfType<[i8], CCAssignToReg<RC.GPR_8>>,
160 CCIfType<[i16], CCAssignToReg<RC.GPR_16>>,
161 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>,
163 // long long, __int64 --> GPR
164 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>,
166 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32)
167 CCIfType<[v64i1], CCPromoteToType<i64>>,
168 CCIfSubtarget<"is64Bit()", CCIfType<[i64],
169 CCAssignToReg<RC.GPR_64>>>,
170 CCIfSubtarget<"is32Bit()", CCIfType<[i64],
171 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>,
173 // long double --> FP
174 CCIfType<[f80], CCAssignToReg<RC.FP_RET>>,
176 // float, double, float128 --> XMM
177 CCIfType<[f32, f64, f128],
178 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
180 // __m128, __m128i, __m128d --> XMM
181 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
182 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
184 // __m256, __m256i, __m256d --> YMM
185 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
186 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>,
188 // __m512, __m512i, __m512d --> ZMM
189 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
190 CCIfSubtarget<"hasAVX512()", CCAssignToReg<RC.ZMM>>>
194 //===----------------------------------------------------------------------===//
195 // Return Value Calling Conventions
196 //===----------------------------------------------------------------------===//
198 // Return-value conventions common to all X86 CC's.
199 def RetCC_X86Common : CallingConv<[
200 // Scalar values are returned in AX first, then DX. For i8, the ABI
201 // requires the values to be in AL and AH, however this code uses AL and DL
202 // instead. This is because using AH for the second register conflicts with
203 // the way LLVM does multiple return values -- a return of {i16,i8} would end
204 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI
205 // for functions that return two i8 values are currently expected to pack the
206 // values into an i16 (which uses AX, and thus AL:AH).
208 // For code that doesn't care about the ABI, we allow returning more than two
209 // integer values in registers.
210 CCIfType<[i1], CCPromoteToType<i8>>,
211 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>,
212 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
213 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
214 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
216 // Boolean vectors of AVX-512 are returned in SIMD registers.
217 // The call from AVX to AVX-512 function should work,
218 // since the boolean types in AVX/AVX2 are promoted by default.
219 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
220 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
221 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
222 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
223 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
224 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
226 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3
227 // can only be used by ABI non-compliant code. If the target doesn't have XMM
228 // registers, it won't have vector types.
229 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
230 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
232 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3
233 // can only be used by ABI non-compliant code. This vector type is only
234 // supported while using the AVX target feature.
235 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
236 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
238 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3
239 // can only be used by ABI non-compliant code. This vector type is only
240 // supported while using the AVX-512 target feature.
241 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
242 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
244 // MMX vector types are always returned in MM0. If the target doesn't have
245 // MM0, it doesn't support these vector types.
246 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>,
248 // Long double types are always returned in FP0 (even with SSE).
249 CCIfType<[f80], CCAssignToReg<[FP0, FP1]>>
252 // X86-32 C return-value convention.
253 def RetCC_X86_32_C : CallingConv<[
254 // The X86-32 calling convention returns FP values in FP0, unless marked
255 // with "inreg" (used here to distinguish one kind of reg from another,
256 // weirdly; this is really the sse-regparm calling convention) in which
257 // case they use XMM0, otherwise it is the same as the common X86 calling
259 CCIfInReg<CCIfSubtarget<"hasSSE2()",
260 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
261 CCIfType<[f32,f64], CCAssignToReg<[FP0, FP1]>>,
262 CCDelegateTo<RetCC_X86Common>
265 // X86-32 FastCC return-value convention.
266 def RetCC_X86_32_Fast : CallingConv<[
267 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
269 // This can happen when a float, 2 x float, or 3 x float vector is split by
270 // target lowering, and is returned in 1-3 sse regs.
271 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
272 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
274 // For integers, ECX can be used as an extra return register
275 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,
276 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
277 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
279 // Otherwise, it is the same as the common X86 calling convention.
280 CCDelegateTo<RetCC_X86Common>
283 // Intel_OCL_BI return-value convention.
284 def RetCC_Intel_OCL_BI : CallingConv<[
285 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3.
286 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
287 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
289 // 256-bit FP vectors
290 // No more than 4 registers
291 CCIfType<[v8f32, v4f64, v8i32, v4i64],
292 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
294 // 512-bit FP vectors
295 CCIfType<[v16f32, v8f64, v16i32, v8i64],
296 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
298 // i32, i64 in the standard way
299 CCDelegateTo<RetCC_X86Common>
302 // X86-32 HiPE return-value convention.
303 def RetCC_X86_32_HiPE : CallingConv<[
304 // Promote all types to i32
305 CCIfType<[i8, i16], CCPromoteToType<i32>>,
307 // Return: HP, P, VAL1, VAL2
308 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>>
311 // X86-32 Vectorcall return-value convention.
312 def RetCC_X86_32_VectorCall : CallingConv<[
313 // Floating Point types are returned in XMM0,XMM1,XMMM2 and XMM3.
314 CCIfType<[f32, f64, f128],
315 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
317 // Return integers in the standard way.
318 CCDelegateTo<RetCC_X86Common>
321 // X86-64 C return-value convention.
322 def RetCC_X86_64_C : CallingConv<[
323 // The X86-64 calling convention always returns FP values in XMM0.
324 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
325 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
326 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1]>>,
328 // MMX vector types are always returned in XMM0.
329 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>,
331 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
333 CCDelegateTo<RetCC_X86Common>
336 // X86-Win64 C return-value convention.
337 def RetCC_X86_Win64_C : CallingConv<[
338 // The X86-Win64 calling convention always returns __m64 values in RAX.
339 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
341 // Otherwise, everything is the same as 'normal' X86-64 C CC.
342 CCDelegateTo<RetCC_X86_64_C>
345 // X86-64 vectorcall return-value convention.
346 def RetCC_X86_64_Vectorcall : CallingConv<[
347 // Vectorcall calling convention always returns FP values in XMMs.
348 CCIfType<[f32, f64, f128],
349 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
351 // Otherwise, everything is the same as Windows X86-64 C CC.
352 CCDelegateTo<RetCC_X86_Win64_C>
355 // X86-64 HiPE return-value convention.
356 def RetCC_X86_64_HiPE : CallingConv<[
357 // Promote all types to i64
358 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
360 // Return: HP, P, VAL1, VAL2
361 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
364 // X86-64 WebKit_JS return-value convention.
365 def RetCC_X86_64_WebKit_JS : CallingConv<[
366 // Promote all types to i64
367 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
370 CCIfType<[i64], CCAssignToReg<[RAX]>>
373 def RetCC_X86_64_Swift : CallingConv<[
375 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
377 // For integers, ECX, R8D can be used as extra return registers.
378 CCIfType<[i1], CCPromoteToType<i8>>,
379 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL, R8B]>>,
380 CCIfType<[i16], CCAssignToReg<[AX, DX, CX, R8W]>>,
381 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX, R8D]>>,
382 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>,
384 // XMM0, XMM1, XMM2 and XMM3 can be used to return FP values.
385 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
386 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
387 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
389 // MMX vector types are returned in XMM0, XMM1, XMM2 and XMM3.
390 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
391 CCDelegateTo<RetCC_X86Common>
394 // X86-64 AnyReg return-value convention. No explicit register is specified for
395 // the return-value. The register allocator is allowed and expected to choose
396 // any free register.
398 // This calling convention is currently only supported by the stackmap and
399 // patchpoint intrinsics. All other uses will result in an assert on Debug
400 // builds. On Release builds we fallback to the X86 C calling convention.
401 def RetCC_X86_64_AnyReg : CallingConv<[
402 CCCustom<"CC_X86_AnyReg_Error">
405 // X86-64 HHVM return-value convention.
406 def RetCC_X86_64_HHVM: CallingConv<[
407 // Promote all types to i64
408 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
410 // Return: could return in any GP register save RSP and R12.
411 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
412 RAX, R10, R11, R13, R14, R15]>>
416 defm X86_32_RegCall :
417 X86_RegCall_base<RC_X86_32_RegCall>;
418 defm X86_Win64_RegCall :
419 X86_RegCall_base<RC_X86_64_RegCall_Win>;
420 defm X86_SysV64_RegCall :
421 X86_RegCall_base<RC_X86_64_RegCall_SysV>;
423 // This is the root return-value convention for the X86-32 backend.
424 def RetCC_X86_32 : CallingConv<[
425 // If FastCC, use RetCC_X86_32_Fast.
426 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
427 // If HiPE, use RetCC_X86_32_HiPE.
428 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>,
429 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_32_VectorCall>>,
430 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_32_RegCall>>,
432 // Otherwise, use RetCC_X86_32_C.
433 CCDelegateTo<RetCC_X86_32_C>
436 // This is the root return-value convention for the X86-64 backend.
437 def RetCC_X86_64 : CallingConv<[
438 // HiPE uses RetCC_X86_64_HiPE
439 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>,
441 // Handle JavaScript calls.
442 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<RetCC_X86_64_WebKit_JS>>,
443 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_X86_64_AnyReg>>,
445 // Handle Swift calls.
446 CCIfCC<"CallingConv::Swift", CCDelegateTo<RetCC_X86_64_Swift>>,
448 // Handle explicit CC selection
449 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<RetCC_X86_Win64_C>>,
450 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>,
452 // Handle Vectorcall CC
453 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_64_Vectorcall>>,
455 // Handle HHVM calls.
456 CCIfCC<"CallingConv::HHVM", CCDelegateTo<RetCC_X86_64_HHVM>>,
458 CCIfCC<"CallingConv::X86_RegCall",
459 CCIfSubtarget<"isTargetWin64()",
460 CCDelegateTo<RetCC_X86_Win64_RegCall>>>,
461 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_SysV64_RegCall>>,
463 // Mingw64 and native Win64 use Win64 CC
464 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
466 // Otherwise, drop to normal X86-64 CC
467 CCDelegateTo<RetCC_X86_64_C>
470 // This is the return-value convention used for the entire X86 backend.
471 def RetCC_X86 : CallingConv<[
473 // Check if this is the Intel OpenCL built-ins calling convention
474 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>,
476 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
477 CCDelegateTo<RetCC_X86_32>
480 //===----------------------------------------------------------------------===//
481 // X86-64 Argument Calling Conventions
482 //===----------------------------------------------------------------------===//
484 def CC_X86_64_C : CallingConv<[
485 // Handles byval parameters.
486 CCIfByVal<CCPassByVal<8, 8>>,
488 // Promote i1/i8/i16 arguments to i32.
489 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
491 // The 'nest' parameter, if any, is passed in R10.
492 CCIfNest<CCIfSubtarget<"isTarget64BitILP32()", CCAssignToReg<[R10D]>>>,
493 CCIfNest<CCAssignToReg<[R10]>>,
495 // Pass SwiftSelf in a callee saved register.
496 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>,
498 // A SwiftError is passed in R12.
499 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
501 // For Swift Calling Convention, pass sret in %RAX.
502 CCIfCC<"CallingConv::Swift",
503 CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>,
505 // The first 6 integer arguments are passed in integer registers.
506 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
507 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
509 // The first 8 MMX vector arguments are passed in XMM registers on Darwin.
511 CCIfSubtarget<"isTargetDarwin()",
512 CCIfSubtarget<"hasSSE2()",
513 CCPromoteToType<v2i64>>>>,
515 // Boolean vectors of AVX-512 are passed in SIMD registers.
516 // The call from AVX to AVX-512 function should work,
517 // since the boolean types in AVX/AVX2 are promoted by default.
518 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
519 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
520 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
521 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
522 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
523 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
525 // The first 8 FP/Vector arguments are passed in XMM registers.
526 CCIfType<[f32, f64, f128, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
527 CCIfSubtarget<"hasSSE1()",
528 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
530 // The first 8 256-bit vector arguments are passed in YMM registers, unless
531 // this is a vararg function.
532 // FIXME: This isn't precisely correct; the x86-64 ABI document says that
533 // fixed arguments to vararg functions are supposed to be passed in
534 // registers. Actually modeling that would be a lot of work, though.
535 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
536 CCIfSubtarget<"hasFp256()",
537 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3,
538 YMM4, YMM5, YMM6, YMM7]>>>>,
540 // The first 8 512-bit vector arguments are passed in ZMM registers.
541 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
542 CCIfSubtarget<"hasAVX512()",
543 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>,
545 // Integer/FP values get stored in stack slots that are 8 bytes in size and
546 // 8-byte aligned if there are no more registers to hold them.
547 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
549 // Long doubles get stack slots whose size and alignment depends on the
551 CCIfType<[f80, f128], CCAssignToStack<0, 0>>,
553 // Vectors get 16-byte stack slots that are 16-byte aligned.
554 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
556 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
557 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
558 CCAssignToStack<32, 32>>,
560 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
561 CCIfType<[v16i32, v8i64, v16f32, v8f64],
562 CCAssignToStack<64, 64>>
565 // Calling convention for X86-64 HHVM.
566 def CC_X86_64_HHVM : CallingConv<[
567 // Use all/any GP registers for args, except RSP.
568 CCIfType<[i64], CCAssignToReg<[RBX, R12, RBP, R15,
569 RDI, RSI, RDX, RCX, R8, R9,
570 RAX, R10, R11, R13, R14]>>
573 // Calling convention for helper functions in HHVM.
574 def CC_X86_64_HHVM_C : CallingConv<[
575 // Pass the first argument in RBP.
576 CCIfType<[i64], CCAssignToReg<[RBP]>>,
578 // Otherwise it's the same as the regular C calling convention.
579 CCDelegateTo<CC_X86_64_C>
582 // Calling convention used on Win64
583 def CC_X86_Win64_C : CallingConv<[
584 // FIXME: Handle byval stuff.
585 // FIXME: Handle varargs.
587 // Promote i1/i8/i16 arguments to i32.
588 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
590 // The 'nest' parameter, if any, is passed in R10.
591 CCIfNest<CCAssignToReg<[R10]>>,
593 // 128 bit vectors are passed by pointer
594 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
597 // 256 bit vectors are passed by pointer
598 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
600 // 512 bit vectors are passed by pointer
601 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
603 // The first 4 MMX vector arguments are passed in GPRs.
604 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
606 // The first 4 integer arguments are passed in integer registers.
607 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
608 [XMM0, XMM1, XMM2, XMM3]>>,
610 // Do not pass the sret argument in RCX, the Win64 thiscall calling
611 // convention requires "this" to be passed in RCX.
612 CCIfCC<"CallingConv::X86_ThisCall",
613 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
614 [XMM1, XMM2, XMM3]>>>>,
616 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
617 [XMM0, XMM1, XMM2, XMM3]>>,
619 // The first 4 FP/Vector arguments are passed in XMM registers.
620 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
621 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
622 [RCX , RDX , R8 , R9 ]>>,
624 // Integer/FP values get stored in stack slots that are 8 bytes in size and
625 // 8-byte aligned if there are no more registers to hold them.
626 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
628 // Long doubles get stack slots whose size and alignment depends on the
630 CCIfType<[f80], CCAssignToStack<0, 0>>
633 def CC_X86_Win64_VectorCall : CallingConv<[
634 CCCustom<"CC_X86_64_VectorCall">,
636 // Delegate to fastcall to handle integer types.
637 CCDelegateTo<CC_X86_Win64_C>
641 def CC_X86_64_GHC : CallingConv<[
642 // Promote i8/i16/i32 arguments to i64.
643 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
645 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
647 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
649 // Pass in STG registers: F1, F2, F3, F4, D1, D2
650 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
651 CCIfSubtarget<"hasSSE1()",
652 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
655 def CC_X86_64_HiPE : CallingConv<[
656 // Promote i8/i16/i32 arguments to i64.
657 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
659 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3
660 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
662 // Integer/FP values get stored in stack slots that are 8 bytes in size and
663 // 8-byte aligned if there are no more registers to hold them.
664 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>
667 def CC_X86_64_WebKit_JS : CallingConv<[
668 // Promote i8/i16 arguments to i32.
669 CCIfType<[i8, i16], CCPromoteToType<i32>>,
671 // Only the first integer argument is passed in register.
672 CCIfType<[i32], CCAssignToReg<[EAX]>>,
673 CCIfType<[i64], CCAssignToReg<[RAX]>>,
675 // The remaining integer arguments are passed on the stack. 32bit integer and
676 // floating-point arguments are aligned to 4 byte and stored in 4 byte slots.
677 // 64bit integer and floating-point arguments are aligned to 8 byte and stored
678 // in 8 byte stack slots.
679 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
680 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
683 // No explicit register is specified for the AnyReg calling convention. The
684 // register allocator may assign the arguments to any free register.
686 // This calling convention is currently only supported by the stackmap and
687 // patchpoint intrinsics. All other uses will result in an assert on Debug
688 // builds. On Release builds we fallback to the X86 C calling convention.
689 def CC_X86_64_AnyReg : CallingConv<[
690 CCCustom<"CC_X86_AnyReg_Error">
693 //===----------------------------------------------------------------------===//
694 // X86 C Calling Convention
695 //===----------------------------------------------------------------------===//
697 /// CC_X86_32_Vector_Common - In all X86-32 calling conventions, extra vector
698 /// values are spilled on the stack.
699 def CC_X86_32_Vector_Common : CallingConv<[
700 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
701 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
703 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned.
704 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
705 CCAssignToStack<32, 32>>,
707 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
708 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
709 CCAssignToStack<64, 64>>
712 // CC_X86_32_Vector_Standard - The first 3 vector arguments are passed in
714 def CC_X86_32_Vector_Standard : CallingConv<[
715 // SSE vector arguments are passed in XMM registers.
716 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
717 CCAssignToReg<[XMM0, XMM1, XMM2]>>>,
719 // AVX 256-bit vector arguments are passed in YMM registers.
720 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
721 CCIfSubtarget<"hasFp256()",
722 CCAssignToReg<[YMM0, YMM1, YMM2]>>>>,
724 // AVX 512-bit vector arguments are passed in ZMM registers.
725 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
726 CCAssignToReg<[ZMM0, ZMM1, ZMM2]>>>,
728 CCDelegateTo<CC_X86_32_Vector_Common>
731 // CC_X86_32_Vector_Darwin - The first 4 vector arguments are passed in
733 def CC_X86_32_Vector_Darwin : CallingConv<[
734 // SSE vector arguments are passed in XMM registers.
735 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
736 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
738 // AVX 256-bit vector arguments are passed in YMM registers.
739 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
740 CCIfSubtarget<"hasFp256()",
741 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>,
743 // AVX 512-bit vector arguments are passed in ZMM registers.
744 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
745 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>>,
747 CCDelegateTo<CC_X86_32_Vector_Common>
750 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
751 /// values are spilled on the stack.
752 def CC_X86_32_Common : CallingConv<[
753 // Handles byval parameters.
754 CCIfByVal<CCPassByVal<4, 4>>,
756 // The first 3 float or double arguments, if marked 'inreg' and if the call
757 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
758 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
759 CCIfSubtarget<"hasSSE2()",
760 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
762 // The first 3 __m64 vector arguments are passed in mmx registers if the
763 // call is not a vararg call.
764 CCIfNotVarArg<CCIfType<[x86mmx],
765 CCAssignToReg<[MM0, MM1, MM2]>>>,
767 // Integer/Float values get stored in stack slots that are 4 bytes in
768 // size and 4-byte aligned.
769 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
771 // Doubles get 8-byte slots that are 4-byte aligned.
772 CCIfType<[f64], CCAssignToStack<8, 4>>,
774 // Long doubles get slots whose size depends on the subtarget.
775 CCIfType<[f80], CCAssignToStack<0, 4>>,
777 // Boolean vectors of AVX-512 are passed in SIMD registers.
778 // The call from AVX to AVX-512 function should work,
779 // since the boolean types in AVX/AVX2 are promoted by default.
780 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
781 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
782 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
783 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
784 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
785 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
787 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
788 // passed in the parameter area.
789 CCIfType<[x86mmx], CCAssignToStack<8, 4>>,
791 // Darwin passes vectors in a form that differs from the i386 psABI
792 CCIfSubtarget<"isTargetDarwin()", CCDelegateTo<CC_X86_32_Vector_Darwin>>,
794 // Otherwise, drop to 'normal' X86-32 CC
795 CCDelegateTo<CC_X86_32_Vector_Standard>
798 def CC_X86_32_C : CallingConv<[
799 // Promote i1/i8/i16 arguments to i32.
800 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
802 // The 'nest' parameter, if any, is passed in ECX.
803 CCIfNest<CCAssignToReg<[ECX]>>,
805 // The first 3 integer arguments, if marked 'inreg' and if the call is not
806 // a vararg call, are passed in integer registers.
807 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
809 // Otherwise, same as everything else.
810 CCDelegateTo<CC_X86_32_Common>
813 def CC_X86_32_MCU : CallingConv<[
814 // Handles byval parameters. Note that, like FastCC, we can't rely on
815 // the delegation to CC_X86_32_Common because that happens after code that
816 // puts arguments in registers.
817 CCIfByVal<CCPassByVal<4, 4>>,
819 // Promote i1/i8/i16 arguments to i32.
820 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
822 // If the call is not a vararg call, some arguments may be passed
823 // in integer registers.
824 CCIfNotVarArg<CCIfType<[i32], CCCustom<"CC_X86_32_MCUInReg">>>,
826 // Otherwise, same as everything else.
827 CCDelegateTo<CC_X86_32_Common>
830 def CC_X86_32_FastCall : CallingConv<[
831 // Promote i1/i8/i16 arguments to i32.
832 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
834 // The 'nest' parameter, if any, is passed in EAX.
835 CCIfNest<CCAssignToReg<[EAX]>>,
837 // The first 2 integer arguments are passed in ECX/EDX
838 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>,
840 // Otherwise, same as everything else.
841 CCDelegateTo<CC_X86_32_Common>
844 def CC_X86_Win32_VectorCall : CallingConv<[
845 // Pass floating point in XMMs
846 CCCustom<"CC_X86_32_VectorCall">,
848 // Delegate to fastcall to handle integer types.
849 CCDelegateTo<CC_X86_32_FastCall>
852 def CC_X86_32_ThisCall_Common : CallingConv<[
853 // The first integer argument is passed in ECX
854 CCIfType<[i32], CCAssignToReg<[ECX]>>,
856 // Otherwise, same as everything else.
857 CCDelegateTo<CC_X86_32_Common>
860 def CC_X86_32_ThisCall_Mingw : CallingConv<[
861 // Promote i1/i8/i16 arguments to i32.
862 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
864 CCDelegateTo<CC_X86_32_ThisCall_Common>
867 def CC_X86_32_ThisCall_Win : CallingConv<[
868 // Promote i1/i8/i16 arguments to i32.
869 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
871 // Pass sret arguments indirectly through stack.
872 CCIfSRet<CCAssignToStack<4, 4>>,
874 CCDelegateTo<CC_X86_32_ThisCall_Common>
877 def CC_X86_32_ThisCall : CallingConv<[
878 CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>,
879 CCDelegateTo<CC_X86_32_ThisCall_Win>
882 def CC_X86_32_FastCC : CallingConv<[
883 // Handles byval parameters. Note that we can't rely on the delegation
884 // to CC_X86_32_Common for this because that happens after code that
885 // puts arguments in registers.
886 CCIfByVal<CCPassByVal<4, 4>>,
888 // Promote i1/i8/i16 arguments to i32.
889 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
891 // The 'nest' parameter, if any, is passed in EAX.
892 CCIfNest<CCAssignToReg<[EAX]>>,
894 // The first 2 integer arguments are passed in ECX/EDX
895 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
897 // The first 3 float or double arguments, if the call is not a vararg
898 // call and if SSE2 is available, are passed in SSE registers.
899 CCIfNotVarArg<CCIfType<[f32,f64],
900 CCIfSubtarget<"hasSSE2()",
901 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
903 // Doubles get 8-byte slots that are 8-byte aligned.
904 CCIfType<[f64], CCAssignToStack<8, 8>>,
906 // Otherwise, same as everything else.
907 CCDelegateTo<CC_X86_32_Common>
910 def CC_X86_32_GHC : CallingConv<[
911 // Promote i8/i16 arguments to i32.
912 CCIfType<[i8, i16], CCPromoteToType<i32>>,
914 // Pass in STG registers: Base, Sp, Hp, R1
915 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>>
918 def CC_X86_32_HiPE : CallingConv<[
919 // Promote i8/i16 arguments to i32.
920 CCIfType<[i8, i16], CCPromoteToType<i32>>,
922 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2
923 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>,
925 // Integer/Float values get stored in stack slots that are 4 bytes in
926 // size and 4-byte aligned.
927 CCIfType<[i32, f32], CCAssignToStack<4, 4>>
930 // X86-64 Intel OpenCL built-ins calling convention.
931 def CC_Intel_OCL_BI : CallingConv<[
933 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>,
934 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>,
936 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>,
937 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
939 CCIfType<[i32], CCAssignToStack<4, 4>>,
941 // The SSE vector arguments are passed in XMM registers.
942 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
943 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
945 // The 256-bit vector arguments are passed in YMM registers.
946 CCIfType<[v8f32, v4f64, v8i32, v4i64],
947 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>,
949 // The 512-bit vector arguments are passed in ZMM registers.
950 CCIfType<[v16f32, v8f64, v16i32, v8i64],
951 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>,
953 // Pass masks in mask registers
954 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>,
956 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
957 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>,
958 CCDelegateTo<CC_X86_32_C>
961 def CC_X86_32_Intr : CallingConv<[
962 CCAssignToStack<4, 4>
965 def CC_X86_64_Intr : CallingConv<[
966 CCAssignToStack<8, 8>
969 //===----------------------------------------------------------------------===//
970 // X86 Root Argument Calling Conventions
971 //===----------------------------------------------------------------------===//
973 // This is the root argument convention for the X86-32 backend.
974 def CC_X86_32 : CallingConv<[
975 // X86_INTR calling convention is valid in MCU target and should override the
976 // MCU calling convention. Thus, this should be checked before isTargetMCU().
977 CCIfCC<"CallingConv::X86_INTR", CCDelegateTo<CC_X86_32_Intr>>,
978 CCIfSubtarget<"isTargetMCU()", CCDelegateTo<CC_X86_32_MCU>>,
979 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>,
980 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win32_VectorCall>>,
981 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>,
982 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>,
983 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>,
984 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>,
985 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_32_RegCall>>,
987 // Otherwise, drop to normal X86-32 CC
988 CCDelegateTo<CC_X86_32_C>
991 // This is the root argument convention for the X86-64 backend.
992 def CC_X86_64 : CallingConv<[
993 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>,
994 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>,
995 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<CC_X86_64_WebKit_JS>>,
996 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_X86_64_AnyReg>>,
997 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<CC_X86_Win64_C>>,
998 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>,
999 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win64_VectorCall>>,
1000 CCIfCC<"CallingConv::HHVM", CCDelegateTo<CC_X86_64_HHVM>>,
1001 CCIfCC<"CallingConv::HHVM_C", CCDelegateTo<CC_X86_64_HHVM_C>>,
1002 CCIfCC<"CallingConv::X86_RegCall",
1003 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_RegCall>>>,
1004 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_SysV64_RegCall>>,
1005 CCIfCC<"CallingConv::X86_INTR", CCDelegateTo<CC_X86_64_Intr>>,
1007 // Mingw64 and native Win64 use Win64 CC
1008 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
1010 // Otherwise, drop to normal X86-64 CC
1011 CCDelegateTo<CC_X86_64_C>
1014 // This is the argument convention used for the entire X86 backend.
1015 def CC_X86 : CallingConv<[
1016 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>,
1017 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>,
1018 CCDelegateTo<CC_X86_32>
1021 //===----------------------------------------------------------------------===//
1022 // Callee-saved Registers.
1023 //===----------------------------------------------------------------------===//
1025 def CSR_NoRegs : CalleeSavedRegs<(add)>;
1027 def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
1028 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
1030 def CSR_64_SwiftError : CalleeSavedRegs<(sub CSR_64, R12)>;
1032 def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>;
1033 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
1035 def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>;
1037 def CSR_Win64 : CalleeSavedRegs<(add CSR_Win64_NoSSE,
1038 (sequence "XMM%u", 6, 15))>;
1040 // The function used by Darwin to obtain the address of a thread-local variable
1041 // uses rdi to pass a single parameter and rax for the return value. All other
1042 // GPRs are preserved.
1043 def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI,
1046 // CSRs that are handled by prologue, epilogue.
1047 def CSR_64_CXX_TLS_Darwin_PE : CalleeSavedRegs<(add RBP)>;
1049 // CSRs that are handled explicitly via copies.
1050 def CSR_64_CXX_TLS_Darwin_ViaCopy : CalleeSavedRegs<(sub CSR_64_TLS_Darwin, RBP)>;
1052 // All GPRs - except r11
1053 def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI,
1056 // All registers - except r11
1057 def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
1058 (sequence "XMM%u", 0, 15))>;
1059 def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
1060 (sequence "YMM%u", 0, 15))>;
1062 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
1063 R11, R12, R13, R14, R15, RBP,
1064 (sequence "XMM%u", 0, 15))>;
1066 def CSR_32_AllRegs : CalleeSavedRegs<(add EAX, EBX, ECX, EDX, EBP, ESI,
1068 def CSR_32_AllRegs_SSE : CalleeSavedRegs<(add CSR_32_AllRegs,
1069 (sequence "XMM%u", 0, 7))>;
1070 def CSR_32_AllRegs_AVX : CalleeSavedRegs<(add CSR_32_AllRegs,
1071 (sequence "YMM%u", 0, 7))>;
1072 def CSR_32_AllRegs_AVX512 : CalleeSavedRegs<(add CSR_32_AllRegs,
1073 (sequence "ZMM%u", 0, 7),
1074 (sequence "K%u", 0, 7))>;
1076 def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX)>;
1077 def CSR_64_AllRegs_NoSSE : CalleeSavedRegs<(add RAX, RBX, RCX, RDX, RSI, RDI, R8, R9,
1078 R10, R11, R12, R13, R14, R15, RBP)>;
1079 def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX,
1080 (sequence "YMM%u", 0, 15)),
1081 (sequence "XMM%u", 0, 15))>;
1082 def CSR_64_AllRegs_AVX512 : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX,
1083 (sequence "ZMM%u", 0, 31),
1084 (sequence "K%u", 0, 7)),
1085 (sequence "XMM%u", 0, 15))>;
1087 // Standard C + YMM6-15
1088 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
1090 (sequence "YMM%u", 6, 15))>;
1092 def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI,
1094 (sequence "ZMM%u", 6, 21),
1096 //Standard C + XMM 8-15
1097 def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64,
1098 (sequence "XMM%u", 8, 15))>;
1100 //Standard C + YMM 8-15
1101 def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64,
1102 (sequence "YMM%u", 8, 15))>;
1104 def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15,
1105 (sequence "ZMM%u", 16, 31),
1108 // Only R12 is preserved for PHP calls in HHVM.
1109 def CSR_64_HHVM : CalleeSavedRegs<(add R12)>;
1111 // Register calling convention preserves few GPR and XMM8-15
1112 def CSR_32_RegCall_NoSSE : CalleeSavedRegs<(add ESI, EDI, EBX, EBP, ESP)>;
1113 def CSR_32_RegCall : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE,
1114 (sequence "XMM%u", 4, 7))>;
1115 def CSR_Win64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, RSP,
1116 (sequence "R%u", 10, 15))>;
1117 def CSR_Win64_RegCall : CalleeSavedRegs<(add CSR_Win64_RegCall_NoSSE,
1118 (sequence "XMM%u", 8, 15))>;
1119 def CSR_SysV64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, RSP,
1120 (sequence "R%u", 12, 15))>;
1121 def CSR_SysV64_RegCall : CalleeSavedRegs<(add CSR_SysV64_RegCall_NoSSE,
1122 (sequence "XMM%u", 8, 15))>;