1 //===----------------------- X86EvexToVex.cpp ----------------------------===//
2 // Compress EVEX instructions to VEX encoding when possible to reduce code size
4 // The LLVM Compiler Infrastructure
6 // This file is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===---------------------------------------------------------------------===//
11 /// This file defines the pass that goes over all AVX-512 instructions which
12 /// are encoded using the EVEX prefix and if possible replaces them by their
13 /// corresponding VEX encoding which is usually shorter by 2 bytes.
14 /// EVEX instructions may be encoded via the VEX prefix when the AVX-512
15 /// instruction has a corresponding AVX/AVX2 opcode and when it does not
16 /// use the xmm or the mask registers or xmm/ymm registers wuith indexes
18 /// The pass applies code reduction on the generated code for AVX-512 instrs.
20 //===---------------------------------------------------------------------===//
22 #include "InstPrinter/X86InstComments.h"
23 #include "MCTargetDesc/X86BaseInfo.h"
25 #include "X86InstrInfo.h"
26 #include "X86Subtarget.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineInstr.h"
32 #include "llvm/CodeGen/MachineOperand.h"
33 #include "llvm/MC/MCInstrDesc.h"
34 #include "llvm/Pass.h"
40 // Including the generated EVEX2VEX tables.
41 struct X86EvexToVexCompressTableEntry {
45 #include "X86GenEVEX2VEXTables.inc"
47 #define EVEX2VEX_DESC "Compressing EVEX instrs to VEX encoding when possible"
48 #define EVEX2VEX_NAME "x86-evex-to-vex-compress"
50 #define DEBUG_TYPE EVEX2VEX_NAME
54 class EvexToVexInstPass : public MachineFunctionPass {
56 /// X86EvexToVexCompressTable - Evex to Vex encoding opcode map.
57 typedef DenseMap<unsigned, uint16_t> EvexToVexTableType;
58 EvexToVexTableType EvexToVex128Table;
59 EvexToVexTableType EvexToVex256Table;
61 /// For EVEX instructions that can be encoded using VEX encoding, replace
62 /// them by the VEX encoding in order to reduce size.
63 bool CompressEvexToVexImpl(MachineInstr &MI) const;
65 /// For initializing the hash map tables of all AVX-512 EVEX
66 /// corresponding to AVX/AVX2 opcodes.
67 void AddTableEntry(EvexToVexTableType &EvexToVexTable, uint16_t EvexOp,
73 EvexToVexInstPass() : MachineFunctionPass(ID) {
74 initializeEvexToVexInstPassPass(*PassRegistry::getPassRegistry());
76 // Initialize the EVEX to VEX 128 table map.
77 for (X86EvexToVexCompressTableEntry Entry : X86EvexToVex128CompressTable) {
78 AddTableEntry(EvexToVex128Table, Entry.EvexOpcode, Entry.VexOpcode);
81 // Initialize the EVEX to VEX 256 table map.
82 for (X86EvexToVexCompressTableEntry Entry : X86EvexToVex256CompressTable) {
83 AddTableEntry(EvexToVex256Table, Entry.EvexOpcode, Entry.VexOpcode);
87 StringRef getPassName() const override { return EVEX2VEX_DESC; }
89 /// Loop over all of the basic blocks, replacing EVEX instructions
90 /// by equivalent VEX instructions when possible for reducing code size.
91 bool runOnMachineFunction(MachineFunction &MF) override;
93 // This pass runs after regalloc and doesn't support VReg operands.
94 MachineFunctionProperties getRequiredProperties() const override {
95 return MachineFunctionProperties().set(
96 MachineFunctionProperties::Property::NoVRegs);
100 /// Machine instruction info used throughout the class.
101 const X86InstrInfo *TII;
104 char EvexToVexInstPass::ID = 0;
106 } // end anonymous namespace
108 bool EvexToVexInstPass::runOnMachineFunction(MachineFunction &MF) {
109 TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
111 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
115 bool Changed = false;
117 /// Go over all basic blocks in function and replace
118 /// EVEX encoded instrs by VEX encoding when possible.
119 for (MachineBasicBlock &MBB : MF) {
121 // Traverse the basic block.
122 for (MachineInstr &MI : MBB)
123 Changed |= CompressEvexToVexImpl(MI);
129 void EvexToVexInstPass::AddTableEntry(EvexToVexTableType &EvexToVexTable,
130 uint16_t EvexOp, uint16_t VexOp) {
131 EvexToVexTable[EvexOp] = VexOp;
134 // For EVEX instructions that can be encoded using VEX encoding
135 // replace them by the VEX encoding in order to reduce size.
136 bool EvexToVexInstPass::CompressEvexToVexImpl(MachineInstr &MI) const {
138 // # of bytes: 0,2,3 1 1 0,1 0,1,2,4 0,1
139 // [Prefixes] [VEX] OPCODE ModR/M [SIB] [DISP] [IMM]
142 // # of bytes: 4 1 1 1 4 / 1 1
143 // [Prefixes] EVEX Opcode ModR/M [SIB] [Disp32] / [Disp8*N] [Immediate]
145 const MCInstrDesc &Desc = MI.getDesc();
147 // Check for EVEX instructions only.
148 if ((Desc.TSFlags & X86II::EncodingMask) != X86II::EVEX)
151 // Check for EVEX instructions with mask or broadcast as in these cases
152 // the EVEX prefix is needed in order to carry this information
153 // thus preventing the transformation to VEX encoding.
154 if (Desc.TSFlags & (X86II::EVEX_K | X86II::EVEX_B))
157 // Check for non EVEX_V512 instrs only.
158 // EVEX_V512 instr: bit EVEX_L2 = 1; bit VEX_L = 0.
159 if ((Desc.TSFlags & X86II::EVEX_L2) && !(Desc.TSFlags & X86II::VEX_L))
162 // EVEX_V128 instr: bit EVEX_L2 = 0, bit VEX_L = 0.
164 (!(Desc.TSFlags & X86II::EVEX_L2) && !(Desc.TSFlags & X86II::VEX_L));
166 // EVEX_V256 instr: bit EVEX_L2 = 0, bit VEX_L = 1.
168 (!(Desc.TSFlags & X86II::EVEX_L2) && (Desc.TSFlags & X86II::VEX_L));
172 // Check for EVEX_V256 instructions.
174 // Search for opcode in the EvexToVex256 table.
175 auto It = EvexToVex256Table.find(MI.getOpcode());
176 if (It != EvexToVex256Table.end())
180 // Check for EVEX_V128 or Scalar instructions.
181 else if (IsEVEX_V128) {
182 // Search for opcode in the EvexToVex128 table.
183 auto It = EvexToVex128Table.find(MI.getOpcode());
184 if (It != EvexToVex128Table.end())
191 auto isHiRegIdx = [](unsigned Reg) {
192 // Check for XMM register with indexes between 16 - 31.
193 if (Reg >= X86::XMM16 && Reg <= X86::XMM31)
196 // Check for YMM register with indexes between 16 - 31.
197 if (Reg >= X86::YMM16 && Reg <= X86::YMM31)
203 // Check that operands are not ZMM regs or
204 // XMM/YMM regs with hi indexes between 16 - 31.
205 for (const MachineOperand &MO : MI.explicit_operands()) {
209 unsigned Reg = MO.getReg();
211 assert (!(Reg >= X86::ZMM0 && Reg <= X86::ZMM31));
217 const MCInstrDesc &MCID = TII->get(NewOpc);
219 MI.setAsmPrinterFlag(AC_EVEX_2_VEX);
223 INITIALIZE_PASS(EvexToVexInstPass, EVEX2VEX_NAME, EVEX2VEX_DESC, false, false)
225 FunctionPass *llvm::createX86EvexToVexInsts() {
226 return new EvexToVexInstPass();