1 //===----------------------- X86EvexToVex.cpp ----------------------------===//
2 // Compress EVEX instructions to VEX encoding when possible to reduce code size
4 // The LLVM Compiler Infrastructure
6 // This file is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===---------------------------------------------------------------------===//
11 /// This file defines the pass that goes over all AVX-512 instructions which
12 /// are encoded using the EVEX prefix and if possible replaces them by their
13 /// corresponding VEX encoding which is usually shorter by 2 bytes.
14 /// EVEX instructions may be encoded via the VEX prefix when the AVX-512
15 /// instruction has a corresponding AVX/AVX2 opcode and when it does not
16 /// use the xmm or the mask registers or xmm/ymm registers wuith indexes
18 /// The pass applies code reduction on the generated code for AVX-512 instrs.
20 //===---------------------------------------------------------------------===//
22 #include "InstPrinter/X86InstComments.h"
24 #include "X86InstrBuilder.h"
25 #include "X86InstrInfo.h"
26 #include "X86InstrTablesInfo.h"
27 #include "X86MachineFunctionInfo.h"
28 #include "X86Subtarget.h"
29 #include "X86TargetMachine.h"
33 #define EVEX2VEX_DESC "Compressing EVEX instrs to VEX encoding when possible"
34 #define EVEX2VEX_NAME "x86-evex-to-vex-compress"
36 #define DEBUG_TYPE EVEX2VEX_NAME
40 class EvexToVexInstPass : public MachineFunctionPass {
42 /// X86EvexToVexCompressTable - Evex to Vex encoding opcode map.
43 typedef DenseMap<unsigned, uint16_t> EvexToVexTableType;
44 EvexToVexTableType EvexToVex128Table;
45 EvexToVexTableType EvexToVex256Table;
47 /// For EVEX instructions that can be encoded using VEX encoding, replace
48 /// them by the VEX encoding in order to reduce size.
49 bool CompressEvexToVexImpl(MachineInstr &MI) const;
51 /// For initializing the hash map tables of all AVX-512 EVEX
52 /// corresponding to AVX/AVX2 opcodes.
53 void AddTableEntry(EvexToVexTableType &EvexToVexTable, uint16_t EvexOp,
59 StringRef getPassName() const override { return EVEX2VEX_DESC; }
61 EvexToVexInstPass() : MachineFunctionPass(ID) {
62 initializeEvexToVexInstPassPass(*PassRegistry::getPassRegistry());
64 // Initialize the EVEX to VEX 128 table map.
65 for (X86EvexToVexCompressTableEntry Entry : X86EvexToVex128CompressTable) {
66 AddTableEntry(EvexToVex128Table, Entry.EvexOpcode, Entry.VexOpcode);
69 // Initialize the EVEX to VEX 256 table map.
70 for (X86EvexToVexCompressTableEntry Entry : X86EvexToVex256CompressTable) {
71 AddTableEntry(EvexToVex256Table, Entry.EvexOpcode, Entry.VexOpcode);
75 /// Loop over all of the basic blocks, replacing EVEX instructions
76 /// by equivalent VEX instructions when possible for reducing code size.
77 bool runOnMachineFunction(MachineFunction &MF) override;
79 // This pass runs after regalloc and doesn't support VReg operands.
80 MachineFunctionProperties getRequiredProperties() const override {
81 return MachineFunctionProperties().set(
82 MachineFunctionProperties::Property::NoVRegs);
86 /// Machine instruction info used throughout the class.
87 const X86InstrInfo *TII;
90 char EvexToVexInstPass::ID = 0;
93 INITIALIZE_PASS(EvexToVexInstPass, EVEX2VEX_NAME, EVEX2VEX_DESC, false, false)
95 FunctionPass *llvm::createX86EvexToVexInsts() {
96 return new EvexToVexInstPass();
99 bool EvexToVexInstPass::runOnMachineFunction(MachineFunction &MF) {
100 TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
102 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
106 bool Changed = false;
108 /// Go over all basic blocks in function and replace
109 /// EVEX encoded instrs by VEX encoding when possible.
110 for (MachineBasicBlock &MBB : MF) {
112 // Traverse the basic block.
113 for (MachineInstr &MI : MBB)
114 Changed |= CompressEvexToVexImpl(MI);
120 void EvexToVexInstPass::AddTableEntry(EvexToVexTableType &EvexToVexTable,
121 uint16_t EvexOp, uint16_t VexOp) {
122 EvexToVexTable[EvexOp] = VexOp;
125 // For EVEX instructions that can be encoded using VEX encoding
126 // replace them by the VEX encoding in order to reduce size.
127 bool EvexToVexInstPass::CompressEvexToVexImpl(MachineInstr &MI) const {
130 // # of bytes: 0,2,3 1 1 0,1 0,1,2,4 0,1
131 // [Prefixes] [VEX] OPCODE ModR/M [SIB] [DISP] [IMM]
134 // # of bytes: 4 1 1 1 4 / 1 1
135 // [Prefixes] EVEX Opcode ModR/M [SIB] [Disp32] / [Disp8*N] [Immediate]
137 const MCInstrDesc &Desc = MI.getDesc();
139 // Check for EVEX instructions only.
140 if ((Desc.TSFlags & X86II::EncodingMask) != X86II::EVEX)
143 // Check for EVEX instructions with mask or broadcast as in these cases
144 // the EVEX prefix is needed in order to carry this information
145 // thus preventing the transformation to VEX encoding.
146 if (Desc.TSFlags & (X86II::EVEX_K | X86II::EVEX_B))
149 // Check for non EVEX_V512 instrs only.
150 // EVEX_V512 instr: bit EVEX_L2 = 1; bit VEX_L = 0.
151 if ((Desc.TSFlags & X86II::EVEX_L2) && !(Desc.TSFlags & X86II::VEX_L))
154 // EVEX_V128 instr: bit EVEX_L2 = 0, bit VEX_L = 0.
156 (!(Desc.TSFlags & X86II::EVEX_L2) && !(Desc.TSFlags & X86II::VEX_L));
158 // EVEX_V256 instr: bit EVEX_L2 = 0, bit VEX_L = 1.
160 (!(Desc.TSFlags & X86II::EVEX_L2) && (Desc.TSFlags & X86II::VEX_L));
164 // Check for EVEX_V256 instructions.
166 // Search for opcode in the EvexToVex256 table.
167 auto It = EvexToVex256Table.find(MI.getOpcode());
168 if (It != EvexToVex256Table.end())
172 // Check for EVEX_V128 or Scalar instructions.
173 else if (IsEVEX_V128) {
174 // Search for opcode in the EvexToVex128 table.
175 auto It = EvexToVex128Table.find(MI.getOpcode());
176 if (It != EvexToVex128Table.end())
183 auto isHiRegIdx = [](unsigned Reg) {
184 // Check for XMM register with indexes between 16 - 31.
185 if (Reg >= X86::XMM16 && Reg <= X86::XMM31)
188 // Check for YMM register with indexes between 16 - 31.
189 if (Reg >= X86::YMM16 && Reg <= X86::YMM31)
195 // Check that operands are not ZMM regs or
196 // XMM/YMM regs with hi indexes between 16 - 31.
197 for (const MachineOperand &MO : MI.explicit_operands()) {
201 unsigned Reg = MO.getReg();
203 assert (!(Reg >= X86::ZMM0 && Reg <= X86::ZMM31));
209 const MCInstrDesc &MCID = TII->get(NewOpc);
211 MI.setAsmPrinterFlag(AC_EVEX_2_VEX);