1 //===------- X86ExpandPseudo.cpp - Expand pseudo instructions -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, other late
12 // optimizations, or simply the encoding of the instructions.
14 //===----------------------------------------------------------------------===//
17 #include "X86FrameLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86InstrInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86Subtarget.h"
22 #include "llvm/Analysis/EHPersonalities.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/Passes.h" // For IDs of passes that are preserved.
26 #include "llvm/IR/GlobalValue.h"
29 #define DEBUG_TYPE "x86-pseudo"
32 class X86ExpandPseudo : public MachineFunctionPass {
35 X86ExpandPseudo() : MachineFunctionPass(ID) {}
37 void getAnalysisUsage(AnalysisUsage &AU) const override {
39 AU.addPreservedID(MachineLoopInfoID);
40 AU.addPreservedID(MachineDominatorsID);
41 MachineFunctionPass::getAnalysisUsage(AU);
44 const X86Subtarget *STI;
45 const X86InstrInfo *TII;
46 const X86RegisterInfo *TRI;
47 const X86MachineFunctionInfo *X86FI;
48 const X86FrameLowering *X86FL;
50 bool runOnMachineFunction(MachineFunction &Fn) override;
52 MachineFunctionProperties getRequiredProperties() const override {
53 return MachineFunctionProperties().set(
54 MachineFunctionProperties::Property::NoVRegs);
57 StringRef getPassName() const override {
58 return "X86 pseudo instruction expansion pass";
62 bool ExpandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
63 bool ExpandMBB(MachineBasicBlock &MBB);
65 char X86ExpandPseudo::ID = 0;
66 } // End anonymous namespace.
68 /// If \p MBBI is a pseudo instruction, this method expands
69 /// it to the corresponding (sequence of) actual instruction(s).
70 /// \returns true if \p MBBI has been expanded.
71 bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
72 MachineBasicBlock::iterator MBBI) {
73 MachineInstr &MI = *MBBI;
74 unsigned Opcode = MI.getOpcode();
75 DebugLoc DL = MBBI->getDebugLoc();
80 case X86::TCRETURNdicc:
83 case X86::TCRETURNdi64:
84 case X86::TCRETURNdi64cc:
85 case X86::TCRETURNri64:
86 case X86::TCRETURNmi64: {
87 bool isMem = Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64;
88 MachineOperand &JumpTarget = MBBI->getOperand(0);
89 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
90 assert(StackAdjust.isImm() && "Expecting immediate value.");
92 // Adjust stack pointer.
93 int StackAdj = StackAdjust.getImm();
94 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
96 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
98 // Incoporate the retaddr area.
99 Offset = StackAdj - MaxTCDelta;
100 assert(Offset >= 0 && "Offset should never be negative");
102 if (Opcode == X86::TCRETURNdicc || Opcode == X86::TCRETURNdi64cc) {
103 assert(Offset == 0 && "Conditional tail call cannot adjust the stack.");
107 // Check for possible merge with preceding ADD instruction.
108 Offset += X86FL->mergeSPUpdates(MBB, MBBI, true);
109 X86FL->emitSPUpdate(MBB, MBBI, Offset, /*InEpilogue=*/true);
112 // Jump to label or value in register.
113 bool IsWin64 = STI->isTargetWin64();
114 if (Opcode == X86::TCRETURNdi || Opcode == X86::TCRETURNdicc ||
115 Opcode == X86::TCRETURNdi64 || Opcode == X86::TCRETURNdi64cc) {
118 case X86::TCRETURNdi:
121 case X86::TCRETURNdicc:
122 Op = X86::TAILJMPd_CC;
124 case X86::TCRETURNdi64cc:
125 assert(!IsWin64 && "Conditional tail calls confuse the Win64 unwinder.");
126 // TODO: We could do it for Win64 "leaf" functions though; PR30337.
127 Op = X86::TAILJMPd64_CC;
130 // Note: Win64 uses REX prefixes indirect jumps out of functions, but
132 Op = X86::TAILJMPd64;
135 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
136 if (JumpTarget.isGlobal()) {
137 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
138 JumpTarget.getTargetFlags());
140 assert(JumpTarget.isSymbol());
141 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
142 JumpTarget.getTargetFlags());
144 if (Op == X86::TAILJMPd_CC || Op == X86::TAILJMPd64_CC) {
145 MIB.addImm(MBBI->getOperand(2).getImm());
148 } else if (Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64) {
149 unsigned Op = (Opcode == X86::TCRETURNmi)
151 : (IsWin64 ? X86::TAILJMPm64_REX : X86::TAILJMPm64);
152 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
153 for (unsigned i = 0; i != 5; ++i)
154 MIB.addOperand(MBBI->getOperand(i));
155 } else if (Opcode == X86::TCRETURNri64) {
156 BuildMI(MBB, MBBI, DL,
157 TII->get(IsWin64 ? X86::TAILJMPr64_REX : X86::TAILJMPr64))
158 .addReg(JumpTarget.getReg(), RegState::Kill);
160 BuildMI(MBB, MBBI, DL, TII->get(X86::TAILJMPr))
161 .addReg(JumpTarget.getReg(), RegState::Kill);
164 MachineInstr &NewMI = *std::prev(MBBI);
165 NewMI.copyImplicitOps(*MBBI->getParent()->getParent(), *MBBI);
167 // Delete the pseudo instruction TCRETURN.
173 case X86::EH_RETURN64: {
174 MachineOperand &DestAddr = MBBI->getOperand(0);
175 assert(DestAddr.isReg() && "Offset should be in register!");
176 const bool Uses64BitFramePtr =
177 STI->isTarget64BitLP64() || STI->isTargetNaCl64();
178 unsigned StackPtr = TRI->getStackRegister();
179 BuildMI(MBB, MBBI, DL,
180 TII->get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr), StackPtr)
181 .addReg(DestAddr.getReg());
182 // The EH_RETURN pseudo is really removed during the MC Lowering.
186 // Adjust stack to erase error code
187 int64_t StackAdj = MBBI->getOperand(0).getImm();
188 X86FL->emitSPUpdate(MBB, MBBI, StackAdj, true);
189 // Replace pseudo with machine iret
190 BuildMI(MBB, MBBI, DL,
191 TII->get(STI->is64Bit() ? X86::IRET64 : X86::IRET32));
196 // Adjust stack to erase error code
197 int64_t StackAdj = MBBI->getOperand(0).getImm();
198 MachineInstrBuilder MIB;
200 MIB = BuildMI(MBB, MBBI, DL,
201 TII->get(STI->is64Bit() ? X86::RETQ : X86::RETL));
202 } else if (isUInt<16>(StackAdj)) {
203 MIB = BuildMI(MBB, MBBI, DL,
204 TII->get(STI->is64Bit() ? X86::RETIQ : X86::RETIL))
207 assert(!STI->is64Bit() &&
208 "shouldn't need to do this for x86_64 targets!");
209 // A ret can only handle immediates as big as 2**16-1. If we need to pop
210 // off bytes before the return address, we must do it manually.
211 BuildMI(MBB, MBBI, DL, TII->get(X86::POP32r)).addReg(X86::ECX, RegState::Define);
212 X86FL->emitSPUpdate(MBB, MBBI, StackAdj, /*InEpilogue=*/true);
213 BuildMI(MBB, MBBI, DL, TII->get(X86::PUSH32r)).addReg(X86::ECX);
214 MIB = BuildMI(MBB, MBBI, DL, TII->get(X86::RETL));
216 for (unsigned I = 1, E = MBBI->getNumOperands(); I != E; ++I)
217 MIB.addOperand(MBBI->getOperand(I));
221 case X86::EH_RESTORE: {
222 // Restore ESP and EBP, and optionally ESI if required.
223 bool IsSEH = isAsynchronousEHPersonality(classifyEHPersonality(
224 MBB.getParent()->getFunction()->getPersonalityFn()));
225 X86FL->restoreWin32EHStackPointers(MBB, MBBI, DL, /*RestoreSP=*/IsSEH);
226 MBBI->eraseFromParent();
229 case X86::LCMPXCHG8B_SAVE_EBX:
230 case X86::LCMPXCHG16B_SAVE_RBX: {
231 // Perform the following transformation.
232 // SaveRbx = pseudocmpxchg Addr, <4 opds for the address>, InArg, SaveRbx
235 // actualcmpxchg Addr
237 const MachineOperand &InArg = MBBI->getOperand(6);
238 unsigned SaveRbx = MBBI->getOperand(7).getReg();
240 unsigned ActualInArg =
241 Opcode == X86::LCMPXCHG8B_SAVE_EBX ? X86::EBX : X86::RBX;
242 // Copy the input argument of the pseudo into the argument of the
243 // actual instruction.
244 TII->copyPhysReg(MBB, MBBI, DL, ActualInArg, InArg.getReg(),
246 // Create the actual instruction.
248 Opcode == X86::LCMPXCHG8B_SAVE_EBX ? X86::LCMPXCHG8B : X86::LCMPXCHG16B;
249 MachineInstr *NewInstr = BuildMI(MBB, MBBI, DL, TII->get(ActualOpc));
250 // Copy the operands related to the address.
251 for (unsigned Idx = 1; Idx < 6; ++Idx)
252 NewInstr->addOperand(MBBI->getOperand(Idx));
253 // Finally, restore the value of RBX.
254 TII->copyPhysReg(MBB, MBBI, DL, ActualInArg, SaveRbx,
257 // Delete the pseudo.
258 MBBI->eraseFromParent();
262 llvm_unreachable("Previous switch has a fallthrough?");
265 /// Expand all pseudo instructions contained in \p MBB.
266 /// \returns true if any expansion occurred for \p MBB.
267 bool X86ExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
268 bool Modified = false;
270 // MBBI may be invalidated by the expansion.
271 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
273 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
274 Modified |= ExpandMI(MBB, MBBI);
281 bool X86ExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
282 STI = &static_cast<const X86Subtarget &>(MF.getSubtarget());
283 TII = STI->getInstrInfo();
284 TRI = STI->getRegisterInfo();
285 X86FI = MF.getInfo<X86MachineFunctionInfo>();
286 X86FL = STI->getFrameLowering();
288 bool Modified = false;
289 for (MachineBasicBlock &MBB : MF)
290 Modified |= ExpandMBB(MBB);
294 /// Returns an instance of the pseudo instruction expansion pass.
295 FunctionPass *llvm::createX86ExpandPseudoPass() {
296 return new X86ExpandPseudo();