1 //===-- X86FixupBWInsts.cpp - Fixup Byte or Word instructions -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file defines the pass that looks through the machine instructions
11 /// late in the compilation, and finds byte or word instructions that
12 /// can be profitably replaced with 32 bit instructions that give equivalent
13 /// results for the bits of the results that are used. There are two possible
14 /// reasons to do this.
16 /// One reason is to avoid false-dependences on the upper portions
17 /// of the registers. Only instructions that have a destination register
18 /// which is not in any of the source registers can be affected by this.
19 /// Any instruction where one of the source registers is also the destination
20 /// register is unaffected, because it has a true dependence on the source
21 /// register already. So, this consideration primarily affects load
22 /// instructions and register-to-register moves. It would
23 /// seem like cmov(s) would also be affected, but because of the way cmov is
24 /// really implemented by most machines as reading both the destination and
25 /// and source regsters, and then "merging" the two based on a condition,
26 /// it really already should be considered as having a true dependence on the
27 /// destination register as well.
29 /// The other reason to do this is for potential code size savings. Word
30 /// operations need an extra override byte compared to their 32 bit
31 /// versions. So this can convert many word operations to their larger
32 /// size, saving a byte in encoding. This could introduce partial register
33 /// dependences where none existed however. As an example take:
36 /// now if this were to get transformed into
39 /// because the addl encodes shorter than the addw, this would introduce
40 /// a use of a register that was only partially written earlier. On older
41 /// Intel processors this can be quite a performance penalty, so this should
42 /// probably only be done when it can be proven that a new partial dependence
43 /// wouldn't be created, or when your know a newer processor is being
44 /// targeted, or when optimizing for minimum code size.
46 //===----------------------------------------------------------------------===//
49 #include "X86InstrInfo.h"
50 #include "X86Subtarget.h"
51 #include "llvm/ADT/Statistic.h"
52 #include "llvm/CodeGen/LivePhysRegs.h"
53 #include "llvm/CodeGen/MachineFunctionPass.h"
54 #include "llvm/CodeGen/MachineInstrBuilder.h"
55 #include "llvm/CodeGen/MachineLoopInfo.h"
56 #include "llvm/CodeGen/MachineRegisterInfo.h"
57 #include "llvm/CodeGen/Passes.h"
58 #include "llvm/Support/Debug.h"
59 #include "llvm/Support/raw_ostream.h"
60 #include "llvm/Target/TargetInstrInfo.h"
63 #define FIXUPBW_DESC "X86 Byte/Word Instruction Fixup"
64 #define FIXUPBW_NAME "x86-fixup-bw-insts"
66 #define DEBUG_TYPE FIXUPBW_NAME
68 // Option to allow this optimization pass to have fine-grained control.
70 FixupBWInsts("fixup-byte-word-insts",
71 cl::desc("Change byte and word instructions to larger sizes"),
72 cl::init(true), cl::Hidden);
75 class FixupBWInstPass : public MachineFunctionPass {
76 /// Loop over all of the instructions in the basic block replacing applicable
77 /// byte or word instructions with better alternatives.
78 void processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
80 /// This sets the \p SuperDestReg to the 32 bit super reg of the original
81 /// destination register of the MachineInstr passed in. It returns true if
82 /// that super register is dead just prior to \p OrigMI, and false if not.
83 bool getSuperRegDestIfDead(MachineInstr *OrigMI,
84 unsigned &SuperDestReg) const;
86 /// Change the MachineInstr \p MI into the equivalent extending load to 32 bit
87 /// register if it is safe to do so. Return the replacement instruction if
88 /// OK, otherwise return nullptr.
89 MachineInstr *tryReplaceLoad(unsigned New32BitOpcode, MachineInstr *MI) const;
91 /// Change the MachineInstr \p MI into the equivalent 32-bit copy if it is
92 /// safe to do so. Return the replacement instruction if OK, otherwise return
94 MachineInstr *tryReplaceCopy(MachineInstr *MI) const;
96 // Change the MachineInstr \p MI into an eqivalent 32 bit instruction if
97 // possible. Return the replacement instruction if OK, return nullptr
99 MachineInstr *tryReplaceInstr(MachineInstr *MI, MachineBasicBlock &MBB) const;
104 StringRef getPassName() const override { return FIXUPBW_DESC; }
106 FixupBWInstPass() : MachineFunctionPass(ID) {
107 initializeFixupBWInstPassPass(*PassRegistry::getPassRegistry());
110 void getAnalysisUsage(AnalysisUsage &AU) const override {
111 AU.addRequired<MachineLoopInfo>(); // Machine loop info is used to
112 // guide some heuristics.
113 MachineFunctionPass::getAnalysisUsage(AU);
116 /// Loop over all of the basic blocks, replacing byte and word instructions by
117 /// equivalent 32 bit instructions where performance or code size can be
119 bool runOnMachineFunction(MachineFunction &MF) override;
121 MachineFunctionProperties getRequiredProperties() const override {
122 return MachineFunctionProperties().set(
123 MachineFunctionProperties::Property::NoVRegs);
129 /// Machine instruction info used throughout the class.
130 const X86InstrInfo *TII;
132 /// Local member for function's OptForSize attribute.
135 /// Machine loop info used for guiding some heruistics.
136 MachineLoopInfo *MLI;
138 /// Register Liveness information after the current instruction.
139 LivePhysRegs LiveRegs;
141 char FixupBWInstPass::ID = 0;
144 INITIALIZE_PASS(FixupBWInstPass, FIXUPBW_NAME, FIXUPBW_DESC, false, false)
146 FunctionPass *llvm::createX86FixupBWInsts() { return new FixupBWInstPass(); }
148 bool FixupBWInstPass::runOnMachineFunction(MachineFunction &MF) {
149 if (!FixupBWInsts || skipFunction(*MF.getFunction()))
153 TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
154 OptForSize = MF.getFunction()->optForSize();
155 MLI = &getAnalysis<MachineLoopInfo>();
156 LiveRegs.init(TII->getRegisterInfo());
158 DEBUG(dbgs() << "Start X86FixupBWInsts\n";);
160 // Process all basic blocks.
162 processBasicBlock(MF, MBB);
164 DEBUG(dbgs() << "End X86FixupBWInsts\n";);
169 // TODO: This method of analysis can miss some legal cases, because the
170 // super-register could be live into the address expression for a memory
171 // reference for the instruction, and still be killed/last used by the
172 // instruction. However, the existing query interfaces don't seem to
173 // easily allow that to be checked.
175 // What we'd really like to know is whether after OrigMI, the
176 // only portion of SuperDestReg that is alive is the portion that
177 // was the destination register of OrigMI.
178 bool FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI,
179 unsigned &SuperDestReg) const {
180 auto *TRI = &TII->getRegisterInfo();
182 unsigned OrigDestReg = OrigMI->getOperand(0).getReg();
183 SuperDestReg = getX86SubSuperRegister(OrigDestReg, 32);
185 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg);
187 // Make sure that the sub-register that this instruction has as its
188 // destination is the lowest order sub-register of the super-register.
189 // If it isn't, then the register isn't really dead even if the
190 // super-register is considered dead.
191 if (SubRegIdx == X86::sub_8bit_hi)
194 if (LiveRegs.contains(SuperDestReg))
197 if (SubRegIdx == X86::sub_8bit) {
198 // In the case of byte registers, we also have to check that the upper
199 // byte register is also dead. That is considered to be independent of
200 // whether the super-register is dead.
201 unsigned UpperByteReg =
202 getX86SubSuperRegister(SuperDestReg, 8, /*High=*/true);
204 if (LiveRegs.contains(UpperByteReg))
211 MachineInstr *FixupBWInstPass::tryReplaceLoad(unsigned New32BitOpcode,
212 MachineInstr *MI) const {
215 // We are going to try to rewrite this load to a larger zero-extending
216 // load. This is safe if all portions of the 32 bit super-register
217 // of the original destination register, except for the original destination
218 // register are dead. getSuperRegDestIfDead checks that.
219 if (!getSuperRegDestIfDead(MI, NewDestReg))
222 // Safe to change the instruction.
223 MachineInstrBuilder MIB =
224 BuildMI(*MF, MI->getDebugLoc(), TII->get(New32BitOpcode), NewDestReg);
226 unsigned NumArgs = MI->getNumOperands();
227 for (unsigned i = 1; i < NumArgs; ++i)
228 MIB.add(MI->getOperand(i));
230 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
235 MachineInstr *FixupBWInstPass::tryReplaceCopy(MachineInstr *MI) const {
236 assert(MI->getNumExplicitOperands() == 2);
237 auto &OldDest = MI->getOperand(0);
238 auto &OldSrc = MI->getOperand(1);
241 if (!getSuperRegDestIfDead(MI, NewDestReg))
244 unsigned NewSrcReg = getX86SubSuperRegister(OldSrc.getReg(), 32);
246 // This is only correct if we access the same subregister index: otherwise,
247 // we could try to replace "movb %ah, %al" with "movl %eax, %eax".
248 auto *TRI = &TII->getRegisterInfo();
249 if (TRI->getSubRegIndex(NewSrcReg, OldSrc.getReg()) !=
250 TRI->getSubRegIndex(NewDestReg, OldDest.getReg()))
253 // Safe to change the instruction.
254 // Don't set src flags, as we don't know if we're also killing the superreg.
255 // However, the superregister might not be defined; make it explicit that
256 // we don't care about the higher bits by reading it as Undef, and adding
257 // an imp-use on the original subregister.
258 MachineInstrBuilder MIB =
259 BuildMI(*MF, MI->getDebugLoc(), TII->get(X86::MOV32rr), NewDestReg)
260 .addReg(NewSrcReg, RegState::Undef)
261 .addReg(OldSrc.getReg(), RegState::Implicit);
263 // Drop imp-defs/uses that would be redundant with the new def/use.
264 for (auto &Op : MI->implicit_operands())
265 if (Op.getReg() != (Op.isDef() ? NewDestReg : NewSrcReg))
271 MachineInstr *FixupBWInstPass::tryReplaceInstr(MachineInstr *MI,
272 MachineBasicBlock &MBB) const {
273 // See if this is an instruction of the type we are currently looking for.
274 switch (MI->getOpcode()) {
277 // Only replace 8 bit loads with the zero extending versions if
278 // in an inner most loop and not optimizing for size. This takes
279 // an extra byte to encode, and provides limited performance upside.
280 if (MachineLoop *ML = MLI->getLoopFor(&MBB))
281 if (ML->begin() == ML->end() && !OptForSize)
282 return tryReplaceLoad(X86::MOVZX32rm8, MI);
286 // Always try to replace 16 bit load with 32 bit zero extending.
287 // Code size is the same, and there is sometimes a perf advantage
288 // from eliminating a false dependence on the upper portion of
290 return tryReplaceLoad(X86::MOVZX32rm16, MI);
294 // Always try to replace 8/16 bit copies with a 32 bit copy.
295 // Code size is either less (16) or equal (8), and there is sometimes a
296 // perf advantage from eliminating a false dependence on the upper portion
298 return tryReplaceCopy(MI);
301 // nothing to do here.
308 void FixupBWInstPass::processBasicBlock(MachineFunction &MF,
309 MachineBasicBlock &MBB) {
311 // This algorithm doesn't delete the instructions it is replacing
312 // right away. By leaving the existing instructions in place, the
313 // register liveness information doesn't change, and this makes the
314 // analysis that goes on be better than if the replaced instructions
315 // were immediately removed.
317 // This algorithm always creates a replacement instruction
318 // and notes that and the original in a data structure, until the
319 // whole BB has been analyzed. This keeps the replacement instructions
320 // from making it seem as if the larger register might be live.
321 SmallVector<std::pair<MachineInstr *, MachineInstr *>, 8> MIReplacements;
323 // Start computing liveness for this block. We iterate from the end to be able
324 // to update this for each instruction.
326 // We run after PEI, so we need to AddPristinesAndCSRs.
327 LiveRegs.addLiveOuts(MBB);
329 for (auto I = MBB.rbegin(); I != MBB.rend(); ++I) {
330 MachineInstr *MI = &*I;
332 if (MachineInstr *NewMI = tryReplaceInstr(MI, MBB))
333 MIReplacements.push_back(std::make_pair(MI, NewMI));
335 // We're done with this instruction, update liveness for the next one.
336 LiveRegs.stepBackward(*MI);
339 while (!MIReplacements.empty()) {
340 MachineInstr *MI = MIReplacements.back().first;
341 MachineInstr *NewMI = MIReplacements.back().second;
342 MIReplacements.pop_back();
343 MBB.insert(MI, NewMI);