1 //===-- X86FixupBWInsts.cpp - Fixup Byte or Word instructions -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file defines the pass that looks through the machine instructions
11 /// late in the compilation, and finds byte or word instructions that
12 /// can be profitably replaced with 32 bit instructions that give equivalent
13 /// results for the bits of the results that are used. There are two possible
14 /// reasons to do this.
16 /// One reason is to avoid false-dependences on the upper portions
17 /// of the registers. Only instructions that have a destination register
18 /// which is not in any of the source registers can be affected by this.
19 /// Any instruction where one of the source registers is also the destination
20 /// register is unaffected, because it has a true dependence on the source
21 /// register already. So, this consideration primarily affects load
22 /// instructions and register-to-register moves. It would
23 /// seem like cmov(s) would also be affected, but because of the way cmov is
24 /// really implemented by most machines as reading both the destination and
25 /// and source regsters, and then "merging" the two based on a condition,
26 /// it really already should be considered as having a true dependence on the
27 /// destination register as well.
29 /// The other reason to do this is for potential code size savings. Word
30 /// operations need an extra override byte compared to their 32 bit
31 /// versions. So this can convert many word operations to their larger
32 /// size, saving a byte in encoding. This could introduce partial register
33 /// dependences where none existed however. As an example take:
36 /// now if this were to get transformed into
39 /// because the addl encodes shorter than the addw, this would introduce
40 /// a use of a register that was only partially written earlier. On older
41 /// Intel processors this can be quite a performance penalty, so this should
42 /// probably only be done when it can be proven that a new partial dependence
43 /// wouldn't be created, or when your know a newer processor is being
44 /// targeted, or when optimizing for minimum code size.
46 //===----------------------------------------------------------------------===//
49 #include "X86InstrInfo.h"
50 #include "X86Subtarget.h"
51 #include "llvm/ADT/Statistic.h"
52 #include "llvm/CodeGen/LivePhysRegs.h"
53 #include "llvm/CodeGen/MachineFunctionPass.h"
54 #include "llvm/CodeGen/MachineInstrBuilder.h"
55 #include "llvm/CodeGen/MachineLoopInfo.h"
56 #include "llvm/CodeGen/MachineRegisterInfo.h"
57 #include "llvm/CodeGen/Passes.h"
58 #include "llvm/Support/Debug.h"
59 #include "llvm/Support/raw_ostream.h"
60 #include "llvm/Target/TargetInstrInfo.h"
63 #define FIXUPBW_DESC "X86 Byte/Word Instruction Fixup"
64 #define FIXUPBW_NAME "x86-fixup-bw-insts"
66 #define DEBUG_TYPE FIXUPBW_NAME
68 // Option to allow this optimization pass to have fine-grained control.
69 // This is turned off by default so as not to affect a large number of
70 // existing lit tests.
72 FixupBWInsts("fixup-byte-word-insts",
73 cl::desc("Change byte and word instructions to larger sizes"),
74 cl::init(true), cl::Hidden);
77 class FixupBWInstPass : public MachineFunctionPass {
78 /// Loop over all of the instructions in the basic block replacing applicable
79 /// byte or word instructions with better alternatives.
80 void processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
82 /// This sets the \p SuperDestReg to the 32 bit super reg of the original
83 /// destination register of the MachineInstr passed in. It returns true if
84 /// that super register is dead just prior to \p OrigMI, and false if not.
85 bool getSuperRegDestIfDead(MachineInstr *OrigMI,
86 unsigned &SuperDestReg) const;
88 /// Change the MachineInstr \p MI into the equivalent extending load to 32 bit
89 /// register if it is safe to do so. Return the replacement instruction if
90 /// OK, otherwise return nullptr.
91 MachineInstr *tryReplaceLoad(unsigned New32BitOpcode, MachineInstr *MI) const;
93 /// Change the MachineInstr \p MI into the equivalent 32-bit copy if it is
94 /// safe to do so. Return the replacement instruction if OK, otherwise return
96 MachineInstr *tryReplaceCopy(MachineInstr *MI) const;
98 // Change the MachineInstr \p MI into an eqivalent 32 bit instruction if
99 // possible. Return the replacement instruction if OK, return nullptr
100 // otherwise. Set WasCandidate to true or false depending on whether the
101 // MI was a candidate for this sort of transformation.
102 MachineInstr *tryReplaceInstr(MachineInstr *MI, MachineBasicBlock &MBB,
103 bool &WasCandidate) const;
107 const char *getPassName() const override {
111 FixupBWInstPass() : MachineFunctionPass(ID) {
112 initializeFixupBWInstPassPass(*PassRegistry::getPassRegistry());
115 void getAnalysisUsage(AnalysisUsage &AU) const override {
116 AU.addRequired<MachineLoopInfo>(); // Machine loop info is used to
117 // guide some heuristics.
118 MachineFunctionPass::getAnalysisUsage(AU);
121 /// Loop over all of the basic blocks, replacing byte and word instructions by
122 /// equivalent 32 bit instructions where performance or code size can be
124 bool runOnMachineFunction(MachineFunction &MF) override;
126 MachineFunctionProperties getRequiredProperties() const override {
127 return MachineFunctionProperties().set(
128 MachineFunctionProperties::Property::AllVRegsAllocated);
134 /// Machine instruction info used throughout the class.
135 const X86InstrInfo *TII;
137 /// Local member for function's OptForSize attribute.
140 /// Machine loop info used for guiding some heruistics.
141 MachineLoopInfo *MLI;
143 /// Register Liveness information after the current instruction.
144 LivePhysRegs LiveRegs;
146 char FixupBWInstPass::ID = 0;
149 INITIALIZE_PASS(FixupBWInstPass, FIXUPBW_NAME, FIXUPBW_DESC, false, false)
151 FunctionPass *llvm::createX86FixupBWInsts() { return new FixupBWInstPass(); }
153 bool FixupBWInstPass::runOnMachineFunction(MachineFunction &MF) {
154 if (!FixupBWInsts || skipFunction(*MF.getFunction()))
158 TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
159 OptForSize = MF.getFunction()->optForSize();
160 MLI = &getAnalysis<MachineLoopInfo>();
161 LiveRegs.init(&TII->getRegisterInfo());
163 DEBUG(dbgs() << "Start X86FixupBWInsts\n";);
165 // Process all basic blocks.
167 processBasicBlock(MF, MBB);
169 DEBUG(dbgs() << "End X86FixupBWInsts\n";);
174 // TODO: This method of analysis can miss some legal cases, because the
175 // super-register could be live into the address expression for a memory
176 // reference for the instruction, and still be killed/last used by the
177 // instruction. However, the existing query interfaces don't seem to
178 // easily allow that to be checked.
180 // What we'd really like to know is whether after OrigMI, the
181 // only portion of SuperDestReg that is alive is the portion that
182 // was the destination register of OrigMI.
183 bool FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI,
184 unsigned &SuperDestReg) const {
185 auto *TRI = &TII->getRegisterInfo();
187 unsigned OrigDestReg = OrigMI->getOperand(0).getReg();
188 SuperDestReg = getX86SubSuperRegister(OrigDestReg, 32);
190 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg);
192 // Make sure that the sub-register that this instruction has as its
193 // destination is the lowest order sub-register of the super-register.
194 // If it isn't, then the register isn't really dead even if the
195 // super-register is considered dead.
196 if (SubRegIdx == X86::sub_8bit_hi)
199 if (LiveRegs.contains(SuperDestReg))
202 if (SubRegIdx == X86::sub_8bit) {
203 // In the case of byte registers, we also have to check that the upper
204 // byte register is also dead. That is considered to be independent of
205 // whether the super-register is dead.
206 unsigned UpperByteReg =
207 getX86SubSuperRegister(SuperDestReg, 8, /*High=*/true);
209 if (LiveRegs.contains(UpperByteReg))
216 MachineInstr *FixupBWInstPass::tryReplaceLoad(unsigned New32BitOpcode,
217 MachineInstr *MI) const {
220 // We are going to try to rewrite this load to a larger zero-extending
221 // load. This is safe if all portions of the 32 bit super-register
222 // of the original destination register, except for the original destination
223 // register are dead. getSuperRegDestIfDead checks that.
224 if (!getSuperRegDestIfDead(MI, NewDestReg))
227 // Safe to change the instruction.
228 MachineInstrBuilder MIB =
229 BuildMI(*MF, MI->getDebugLoc(), TII->get(New32BitOpcode), NewDestReg);
231 unsigned NumArgs = MI->getNumOperands();
232 for (unsigned i = 1; i < NumArgs; ++i)
233 MIB.addOperand(MI->getOperand(i));
235 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
240 MachineInstr *FixupBWInstPass::tryReplaceCopy(MachineInstr *MI) const {
241 assert(MI->getNumExplicitOperands() == 2);
242 auto &OldDest = MI->getOperand(0);
243 auto &OldSrc = MI->getOperand(1);
246 if (!getSuperRegDestIfDead(MI, NewDestReg))
249 unsigned NewSrcReg = getX86SubSuperRegister(OldSrc.getReg(), 32);
251 // This is only correct if we access the same subregister index: otherwise,
252 // we could try to replace "movb %ah, %al" with "movl %eax, %eax".
253 auto *TRI = &TII->getRegisterInfo();
254 if (TRI->getSubRegIndex(NewSrcReg, OldSrc.getReg()) !=
255 TRI->getSubRegIndex(NewDestReg, OldDest.getReg()))
258 // Safe to change the instruction.
259 // Don't set src flags, as we don't know if we're also killing the superreg.
260 // However, the superregister might not be defined; make it explicit that
261 // we don't care about the higher bits by reading it as Undef, and adding
262 // an imp-use on the original subregister.
263 MachineInstrBuilder MIB =
264 BuildMI(*MF, MI->getDebugLoc(), TII->get(X86::MOV32rr), NewDestReg)
265 .addReg(NewSrcReg, RegState::Undef)
266 .addReg(OldSrc.getReg(), RegState::Implicit);
268 // Drop imp-defs/uses that would be redundant with the new def/use.
269 for (auto &Op : MI->implicit_operands())
270 if (Op.getReg() != (Op.isDef() ? NewDestReg : NewSrcReg))
276 MachineInstr *FixupBWInstPass::tryReplaceInstr(
277 MachineInstr *MI, MachineBasicBlock &MBB,
278 bool &WasCandidate) const {
279 MachineInstr *NewMI = nullptr;
280 WasCandidate = false;
282 // See if this is an instruction of the type we are currently looking for.
283 switch (MI->getOpcode()) {
286 // Only replace 8 bit loads with the zero extending versions if
287 // in an inner most loop and not optimizing for size. This takes
288 // an extra byte to encode, and provides limited performance upside.
289 if (MachineLoop *ML = MLI->getLoopFor(&MBB)) {
290 if (ML->begin() == ML->end() && !OptForSize) {
291 NewMI = tryReplaceLoad(X86::MOVZX32rm8, MI);
298 // Always try to replace 16 bit load with 32 bit zero extending.
299 // Code size is the same, and there is sometimes a perf advantage
300 // from eliminating a false dependence on the upper portion of
302 NewMI = tryReplaceLoad(X86::MOVZX32rm16, MI);
308 // Always try to replace 8/16 bit copies with a 32 bit copy.
309 // Code size is either less (16) or equal (8), and there is sometimes a
310 // perf advantage from eliminating a false dependence on the upper portion
312 NewMI = tryReplaceCopy(MI);
317 // nothing to do here.
324 void FixupBWInstPass::processBasicBlock(MachineFunction &MF,
325 MachineBasicBlock &MBB) {
327 // This algorithm doesn't delete the instructions it is replacing
328 // right away. By leaving the existing instructions in place, the
329 // register liveness information doesn't change, and this makes the
330 // analysis that goes on be better than if the replaced instructions
331 // were immediately removed.
333 // This algorithm always creates a replacement instruction
334 // and notes that and the original in a data structure, until the
335 // whole BB has been analyzed. This keeps the replacement instructions
336 // from making it seem as if the larger register might be live.
337 SmallVector<std::pair<MachineInstr *, MachineInstr *>, 8> MIReplacements;
339 // Start computing liveness for this block. We iterate from the end to be able
340 // to update this for each instruction.
342 // We run after PEI, so we need to AddPristinesAndCSRs.
343 LiveRegs.addLiveOuts(MBB);
345 bool WasCandidate = false;
347 for (auto I = MBB.rbegin(); I != MBB.rend(); ++I) {
348 MachineInstr *MI = &*I;
350 MachineInstr *NewMI = tryReplaceInstr(MI, MBB, WasCandidate);
352 // Add this to replacements if it was a candidate, even if NewMI is
353 // nullptr. We will revisit that in a bit.
355 MIReplacements.push_back(std::make_pair(MI, NewMI));
358 // We're done with this instruction, update liveness for the next one.
359 LiveRegs.stepBackward(*MI);
362 while (!MIReplacements.empty()) {
363 MachineInstr *MI = MIReplacements.back().first;
364 MachineInstr *NewMI = MIReplacements.back().second;
365 MIReplacements.pop_back();
367 MBB.insert(MI, NewMI);