1 //===-- X86FixupLEAs.cpp - use or replace LEA instructions -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the pass that finds instructions that can be
11 // re-written as LEA instructions in order to reduce pipeline delays.
12 // When optimizing for size it replaces suitable LEAs with INC or DEC.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrInfo.h"
18 #include "X86Subtarget.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Target/TargetInstrInfo.h"
31 void initializeFixupLEAPassPass(PassRegistry &);
34 #define FIXUPLEA_DESC "X86 LEA Fixup"
35 #define FIXUPLEA_NAME "x86-fixup-LEAs"
37 #define DEBUG_TYPE FIXUPLEA_NAME
39 STATISTIC(NumLEAs, "Number of LEA instructions created");
42 class FixupLEAPass : public MachineFunctionPass {
43 enum RegUsageState { RU_NotUsed, RU_Write, RU_Read };
45 /// \brief Loop over all of the instructions in the basic block
46 /// replacing applicable instructions with LEA instructions,
47 /// where appropriate.
48 bool processBasicBlock(MachineFunction &MF, MachineFunction::iterator MFI);
51 /// \brief Given a machine register, look for the instruction
52 /// which writes it in the current basic block. If found,
53 /// try to replace it with an equivalent LEA instruction.
54 /// If replacement succeeds, then also process the newly created
56 void seekLEAFixup(MachineOperand &p, MachineBasicBlock::iterator &I,
57 MachineFunction::iterator MFI);
59 /// \brief Given a memory access or LEA instruction
60 /// whose address mode uses a base and/or index register, look for
61 /// an opportunity to replace the instruction which sets the base or index
62 /// register with an equivalent LEA instruction.
63 void processInstruction(MachineBasicBlock::iterator &I,
64 MachineFunction::iterator MFI);
66 /// \brief Given a LEA instruction which is unprofitable
67 /// on Silvermont try to replace it with an equivalent ADD instruction
68 void processInstructionForSLM(MachineBasicBlock::iterator &I,
69 MachineFunction::iterator MFI);
72 /// \brief Given a LEA instruction which is unprofitable
73 /// on SNB+ try to replace it with other instructions.
74 /// According to Intel's Optimization Reference Manual:
75 /// " For LEA instructions with three source operands and some specific
76 /// situations, instruction latency has increased to 3 cycles, and must
77 /// dispatch via port 1:
78 /// - LEA that has all three source operands: base, index, and offset
79 /// - LEA that uses base and index registers where the base is EBP, RBP,
81 /// - LEA that uses RIP relative addressing mode
82 /// - LEA that uses 16-bit addressing mode "
83 /// This function currently handles the first 2 cases only.
84 MachineInstr *processInstrForSlow3OpLEA(MachineInstr &MI,
85 MachineFunction::iterator MFI);
87 /// \brief Look for LEAs that add 1 to reg or subtract 1 from reg
88 /// and convert them to INC or DEC respectively.
89 bool fixupIncDec(MachineBasicBlock::iterator &I,
90 MachineFunction::iterator MFI) const;
92 /// \brief Determine if an instruction references a machine register
93 /// and, if so, whether it reads or writes the register.
94 RegUsageState usesRegister(MachineOperand &p, MachineBasicBlock::iterator I);
96 /// \brief Step backwards through a basic block, looking
97 /// for an instruction which writes a register within
98 /// a maximum of INSTR_DISTANCE_THRESHOLD instruction latency cycles.
99 MachineBasicBlock::iterator searchBackwards(MachineOperand &p,
100 MachineBasicBlock::iterator &I,
101 MachineFunction::iterator MFI);
103 /// \brief if an instruction can be converted to an
104 /// equivalent LEA, insert the new instruction into the basic block
105 /// and return a pointer to it. Otherwise, return zero.
106 MachineInstr *postRAConvertToLEA(MachineFunction::iterator &MFI,
107 MachineBasicBlock::iterator &MBBI) const;
112 StringRef getPassName() const override { return FIXUPLEA_DESC; }
114 FixupLEAPass() : MachineFunctionPass(ID) {
115 initializeFixupLEAPassPass(*PassRegistry::getPassRegistry());
118 /// \brief Loop over all of the basic blocks,
119 /// replacing instructions by equivalent LEA instructions
120 /// if needed and when possible.
121 bool runOnMachineFunction(MachineFunction &MF) override;
123 // This pass runs after regalloc and doesn't support VReg operands.
124 MachineFunctionProperties getRequiredProperties() const override {
125 return MachineFunctionProperties().set(
126 MachineFunctionProperties::Property::NoVRegs);
131 const X86InstrInfo *TII; // Machine instruction info.
137 char FixupLEAPass::ID = 0;
139 INITIALIZE_PASS(FixupLEAPass, FIXUPLEA_NAME, FIXUPLEA_DESC, false, false)
142 FixupLEAPass::postRAConvertToLEA(MachineFunction::iterator &MFI,
143 MachineBasicBlock::iterator &MBBI) const {
144 MachineInstr &MI = *MBBI;
145 switch (MI.getOpcode()) {
148 const MachineOperand &Src = MI.getOperand(1);
149 const MachineOperand &Dest = MI.getOperand(0);
150 MachineInstr *NewMI =
151 BuildMI(*MF, MI.getDebugLoc(),
152 TII->get(MI.getOpcode() == X86::MOV32rr ? X86::LEA32r
160 MFI->insert(MBBI, NewMI); // Insert the new inst
165 case X86::ADD64ri32_DB:
166 case X86::ADD64ri8_DB:
169 case X86::ADD32ri_DB:
170 case X86::ADD32ri8_DB:
173 case X86::ADD16ri_DB:
174 case X86::ADD16ri8_DB:
175 if (!MI.getOperand(2).isImm()) {
176 // convertToThreeAddress will call getImm()
177 // which requires isImm() to be true
182 case X86::ADD16rr_DB:
183 if (MI.getOperand(1).getReg() != MI.getOperand(2).getReg()) {
184 // if src1 != src2, then convertToThreeAddress will
185 // need to create a Virtual register, which we cannot do
186 // after register allocation.
190 return TII->convertToThreeAddress(MFI, MI, nullptr);
193 FunctionPass *llvm::createX86FixupLEAs() { return new FixupLEAPass(); }
195 bool FixupLEAPass::runOnMachineFunction(MachineFunction &Func) {
196 if (skipFunction(*Func.getFunction()))
200 const X86Subtarget &ST = Func.getSubtarget<X86Subtarget>();
201 OptIncDec = !ST.slowIncDec() || Func.getFunction()->optForMinSize();
202 OptLEA = ST.LEAusesAG() || ST.slowLEA() || ST.slow3OpsLEA();
204 if (!OptLEA && !OptIncDec)
207 TII = ST.getInstrInfo();
209 DEBUG(dbgs() << "Start X86FixupLEAs\n";);
210 // Process all basic blocks.
211 for (MachineFunction::iterator I = Func.begin(), E = Func.end(); I != E; ++I)
212 processBasicBlock(Func, I);
213 DEBUG(dbgs() << "End X86FixupLEAs\n";);
218 FixupLEAPass::RegUsageState
219 FixupLEAPass::usesRegister(MachineOperand &p, MachineBasicBlock::iterator I) {
220 RegUsageState RegUsage = RU_NotUsed;
221 MachineInstr &MI = *I;
223 for (unsigned int i = 0; i < MI.getNumOperands(); ++i) {
224 MachineOperand &opnd = MI.getOperand(i);
225 if (opnd.isReg() && opnd.getReg() == p.getReg()) {
234 /// getPreviousInstr - Given a reference to an instruction in a basic
235 /// block, return a reference to the previous instruction in the block,
236 /// wrapping around to the last instruction of the block if the block
237 /// branches to itself.
238 static inline bool getPreviousInstr(MachineBasicBlock::iterator &I,
239 MachineFunction::iterator MFI) {
240 if (I == MFI->begin()) {
241 if (MFI->isPredecessor(&*MFI)) {
251 MachineBasicBlock::iterator
252 FixupLEAPass::searchBackwards(MachineOperand &p, MachineBasicBlock::iterator &I,
253 MachineFunction::iterator MFI) {
254 int InstrDistance = 1;
255 MachineBasicBlock::iterator CurInst;
256 static const int INSTR_DISTANCE_THRESHOLD = 5;
260 Found = getPreviousInstr(CurInst, MFI);
261 while (Found && I != CurInst) {
262 if (CurInst->isCall() || CurInst->isInlineAsm())
264 if (InstrDistance > INSTR_DISTANCE_THRESHOLD)
265 break; // too far back to make a difference
266 if (usesRegister(p, CurInst) == RU_Write) {
269 InstrDistance += TII->getInstrLatency(
270 MF->getSubtarget().getInstrItineraryData(), *CurInst);
271 Found = getPreviousInstr(CurInst, MFI);
273 return MachineBasicBlock::iterator();
276 static inline bool isLEA(const int Opcode) {
277 return Opcode == X86::LEA16r || Opcode == X86::LEA32r ||
278 Opcode == X86::LEA64r || Opcode == X86::LEA64_32r;
281 static inline bool isInefficientLEAReg(unsigned int Reg) {
282 return Reg == X86::EBP || Reg == X86::RBP || Reg == X86::R13;
285 static inline bool isRegOperand(const MachineOperand &Op) {
286 return Op.isReg() && Op.getReg() != X86::NoRegister;
288 /// hasIneffecientLEARegs - LEA that uses base and index registers
289 /// where the base is EBP, RBP, or R13
290 static inline bool hasInefficientLEABaseReg(const MachineOperand &Base,
291 const MachineOperand &Index) {
292 return Base.isReg() && isInefficientLEAReg(Base.getReg()) &&
296 static inline bool hasLEAOffset(const MachineOperand &Offset) {
297 return (Offset.isImm() && Offset.getImm() != 0) || Offset.isGlobal();
300 // LEA instruction that has all three operands: offset, base and index
301 static inline bool isThreeOperandsLEA(const MachineOperand &Base,
302 const MachineOperand &Index,
303 const MachineOperand &Offset) {
304 return isRegOperand(Base) && isRegOperand(Index) && hasLEAOffset(Offset);
307 static inline int getADDrrFromLEA(int LEAOpcode) {
310 llvm_unreachable("Unexpected LEA instruction");
321 static inline int getADDriFromLEA(int LEAOpcode, const MachineOperand &Offset) {
322 bool IsInt8 = Offset.isImm() && isInt<8>(Offset.getImm());
325 llvm_unreachable("Unexpected LEA instruction");
327 return IsInt8 ? X86::ADD16ri8 : X86::ADD16ri;
330 return IsInt8 ? X86::ADD32ri8 : X86::ADD32ri;
332 return IsInt8 ? X86::ADD64ri8 : X86::ADD64ri32;
336 /// isLEASimpleIncOrDec - Does this LEA have one these forms:
337 /// lea %reg, 1(%reg)
338 /// lea %reg, -1(%reg)
339 static inline bool isLEASimpleIncOrDec(MachineInstr &LEA) {
340 unsigned SrcReg = LEA.getOperand(1 + X86::AddrBaseReg).getReg();
341 unsigned DstReg = LEA.getOperand(0).getReg();
342 unsigned AddrDispOp = 1 + X86::AddrDisp;
343 return SrcReg == DstReg &&
344 LEA.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
345 LEA.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
346 LEA.getOperand(AddrDispOp).isImm() &&
347 (LEA.getOperand(AddrDispOp).getImm() == 1 ||
348 LEA.getOperand(AddrDispOp).getImm() == -1);
351 bool FixupLEAPass::fixupIncDec(MachineBasicBlock::iterator &I,
352 MachineFunction::iterator MFI) const {
353 MachineInstr &MI = *I;
354 int Opcode = MI.getOpcode();
358 if (isLEASimpleIncOrDec(MI) && TII->isSafeToClobberEFLAGS(*MFI, I)) {
360 bool isINC = MI.getOperand(4).getImm() == 1;
363 NewOpcode = isINC ? X86::INC16r : X86::DEC16r;
367 NewOpcode = isINC ? X86::INC32r : X86::DEC32r;
370 NewOpcode = isINC ? X86::INC64r : X86::DEC64r;
374 MachineInstr *NewMI =
375 BuildMI(*MFI, I, MI.getDebugLoc(), TII->get(NewOpcode))
376 .add(MI.getOperand(0))
377 .add(MI.getOperand(1));
379 I = static_cast<MachineBasicBlock::iterator>(NewMI);
385 void FixupLEAPass::processInstruction(MachineBasicBlock::iterator &I,
386 MachineFunction::iterator MFI) {
387 // Process a load, store, or LEA instruction.
388 MachineInstr &MI = *I;
389 const MCInstrDesc &Desc = MI.getDesc();
390 int AddrOffset = X86II::getMemoryOperandNo(Desc.TSFlags);
391 if (AddrOffset >= 0) {
392 AddrOffset += X86II::getOperandBias(Desc);
393 MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg);
394 if (p.isReg() && p.getReg() != X86::ESP) {
395 seekLEAFixup(p, I, MFI);
397 MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg);
398 if (q.isReg() && q.getReg() != X86::ESP) {
399 seekLEAFixup(q, I, MFI);
404 void FixupLEAPass::seekLEAFixup(MachineOperand &p,
405 MachineBasicBlock::iterator &I,
406 MachineFunction::iterator MFI) {
407 MachineBasicBlock::iterator MBI = searchBackwards(p, I, MFI);
408 if (MBI != MachineBasicBlock::iterator()) {
409 MachineInstr *NewMI = postRAConvertToLEA(MFI, MBI);
412 DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MBI->dump(););
413 // now to replace with an equivalent LEA...
414 DEBUG(dbgs() << "FixLEA: Replaced by: "; NewMI->dump(););
416 MachineBasicBlock::iterator J =
417 static_cast<MachineBasicBlock::iterator>(NewMI);
418 processInstruction(J, MFI);
423 void FixupLEAPass::processInstructionForSLM(MachineBasicBlock::iterator &I,
424 MachineFunction::iterator MFI) {
425 MachineInstr &MI = *I;
426 const int Opcode = MI.getOpcode();
429 if (MI.getOperand(5).getReg() != 0 || !MI.getOperand(4).isImm() ||
430 !TII->isSafeToClobberEFLAGS(*MFI, I))
432 const unsigned DstR = MI.getOperand(0).getReg();
433 const unsigned SrcR1 = MI.getOperand(1).getReg();
434 const unsigned SrcR2 = MI.getOperand(3).getReg();
435 if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
437 if (MI.getOperand(2).getImm() > 1)
439 DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump(););
440 DEBUG(dbgs() << "FixLEA: Replaced by: ";);
441 MachineInstr *NewMI = nullptr;
442 // Make ADD instruction for two registers writing to LEA's destination
443 if (SrcR1 != 0 && SrcR2 != 0) {
444 const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode));
445 const MachineOperand &Src = MI.getOperand(SrcR1 == DstR ? 3 : 1);
447 BuildMI(*MFI, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src);
448 DEBUG(NewMI->dump(););
450 // Make ADD instruction for immediate
451 if (MI.getOperand(4).getImm() != 0) {
452 const MCInstrDesc &ADDri =
453 TII->get(getADDriFromLEA(Opcode, MI.getOperand(4)));
454 const MachineOperand &SrcR = MI.getOperand(SrcR1 == DstR ? 1 : 3);
455 NewMI = BuildMI(*MFI, I, MI.getDebugLoc(), ADDri, DstR)
457 .addImm(MI.getOperand(4).getImm());
458 DEBUG(NewMI->dump(););
467 FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI,
468 MachineFunction::iterator MFI) {
470 const int LEAOpcode = MI.getOpcode();
471 if (!isLEA(LEAOpcode))
474 const MachineOperand &Dst = MI.getOperand(0);
475 const MachineOperand &Base = MI.getOperand(1);
476 const MachineOperand &Scale = MI.getOperand(2);
477 const MachineOperand &Index = MI.getOperand(3);
478 const MachineOperand &Offset = MI.getOperand(4);
479 const MachineOperand &Segment = MI.getOperand(5);
481 if (!(isThreeOperandsLEA(Base, Index, Offset) ||
482 hasInefficientLEABaseReg(Base, Index)) ||
483 !TII->isSafeToClobberEFLAGS(*MFI, MI) ||
484 Segment.getReg() != X86::NoRegister)
487 unsigned int DstR = Dst.getReg();
488 unsigned int BaseR = Base.getReg();
489 unsigned int IndexR = Index.getReg();
491 (LEAOpcode == X86::LEA64_32r) ? getX86SubSuperRegister(DstR, 64) : DstR;
492 bool IsScale1 = Scale.getImm() == 1;
493 bool IsInefficientBase = isInefficientLEAReg(BaseR);
494 bool IsInefficientIndex = isInefficientLEAReg(IndexR);
496 // Skip these cases since it takes more than 2 instructions
497 // to replace the LEA instruction.
498 if (IsInefficientBase && SSDstR == BaseR && !IsScale1)
500 if (LEAOpcode == X86::LEA64_32r && IsInefficientBase &&
501 (IsInefficientIndex || !IsScale1))
504 const DebugLoc DL = MI.getDebugLoc();
505 const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(LEAOpcode));
506 const MCInstrDesc &ADDri = TII->get(getADDriFromLEA(LEAOpcode, Offset));
508 DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MI.dump(););
509 DEBUG(dbgs() << "FixLEA: Replaced by: ";);
511 // First try to replace LEA with one or two (for the 3-op LEA case)
513 // 1.lea (%base,%index,1), %base => add %index,%base
514 // 2.lea (%base,%index,1), %index => add %base,%index
515 if (IsScale1 && (DstR == BaseR || DstR == IndexR)) {
516 const MachineOperand &Src = DstR == BaseR ? Index : Base;
517 MachineInstr *NewMI =
518 BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Src);
519 DEBUG(NewMI->dump(););
520 // Create ADD instruction for the Offset in case of 3-Ops LEA.
521 if (hasLEAOffset(Offset)) {
522 NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
523 DEBUG(NewMI->dump(););
527 // If the base is inefficient try switching the index and base operands,
528 // otherwise just break the 3-Ops LEA inst into 2-Ops LEA + ADD instruction:
529 // lea offset(%base,%index,scale),%dst =>
530 // lea (%base,%index,scale); add offset,%dst
531 if (!IsInefficientBase || (!IsInefficientIndex && IsScale1)) {
532 MachineInstr *NewMI = BuildMI(*MFI, MI, DL, TII->get(LEAOpcode))
534 .add(IsInefficientBase ? Index : Base)
536 .add(IsInefficientBase ? Base : Index)
539 DEBUG(NewMI->dump(););
540 // Create ADD instruction for the Offset in case of 3-Ops LEA.
541 if (hasLEAOffset(Offset)) {
542 NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
543 DEBUG(NewMI->dump(););
547 // Handle the rest of the cases with inefficient base register:
548 assert(SSDstR != BaseR && "SSDstR == BaseR should be handled already!");
549 assert(IsInefficientBase && "efficient base should be handled already!");
551 // lea (%base,%index,1), %dst => mov %base,%dst; add %index,%dst
552 if (IsScale1 && !hasLEAOffset(Offset)) {
553 TII->copyPhysReg(*MFI, MI, DL, DstR, BaseR, Base.isKill());
554 DEBUG(MI.getPrevNode()->dump(););
556 MachineInstr *NewMI =
557 BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Index);
558 DEBUG(NewMI->dump(););
561 // lea offset(%base,%index,scale), %dst =>
562 // lea offset( ,%index,scale), %dst; add %base,%dst
563 MachineInstr *NewMI = BuildMI(*MFI, MI, DL, TII->get(LEAOpcode))
570 DEBUG(NewMI->dump(););
572 NewMI = BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Base);
573 DEBUG(NewMI->dump(););
577 bool FixupLEAPass::processBasicBlock(MachineFunction &MF,
578 MachineFunction::iterator MFI) {
580 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
582 if (fixupIncDec(I, MFI))
586 if (MF.getSubtarget<X86Subtarget>().isSLM())
587 processInstructionForSLM(I, MFI);
590 if (MF.getSubtarget<X86Subtarget>().slow3OpsLEA()) {
591 if (auto *NewMI = processInstrForSlow3OpLEA(*I, MFI)) {
596 processInstruction(I, MFI);