1 //===-- X86FixupLEAs.cpp - use or replace LEA instructions -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the pass that finds instructions that can be
11 // re-written as LEA instructions in order to reduce pipeline delays.
12 // When optimizing for size it replaces suitable LEAs with INC or DEC.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrInfo.h"
18 #include "X86Subtarget.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/CodeGen/TargetInstrInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/raw_ostream.h"
29 void initializeFixupLEAPassPass(PassRegistry &);
32 #define FIXUPLEA_DESC "X86 LEA Fixup"
33 #define FIXUPLEA_NAME "x86-fixup-LEAs"
35 #define DEBUG_TYPE FIXUPLEA_NAME
37 STATISTIC(NumLEAs, "Number of LEA instructions created");
40 class FixupLEAPass : public MachineFunctionPass {
41 enum RegUsageState { RU_NotUsed, RU_Write, RU_Read };
43 /// \brief Loop over all of the instructions in the basic block
44 /// replacing applicable instructions with LEA instructions,
45 /// where appropriate.
46 bool processBasicBlock(MachineFunction &MF, MachineFunction::iterator MFI);
49 /// \brief Given a machine register, look for the instruction
50 /// which writes it in the current basic block. If found,
51 /// try to replace it with an equivalent LEA instruction.
52 /// If replacement succeeds, then also process the newly created
54 void seekLEAFixup(MachineOperand &p, MachineBasicBlock::iterator &I,
55 MachineFunction::iterator MFI);
57 /// \brief Given a memory access or LEA instruction
58 /// whose address mode uses a base and/or index register, look for
59 /// an opportunity to replace the instruction which sets the base or index
60 /// register with an equivalent LEA instruction.
61 void processInstruction(MachineBasicBlock::iterator &I,
62 MachineFunction::iterator MFI);
64 /// \brief Given a LEA instruction which is unprofitable
65 /// on Silvermont try to replace it with an equivalent ADD instruction
66 void processInstructionForSLM(MachineBasicBlock::iterator &I,
67 MachineFunction::iterator MFI);
70 /// \brief Given a LEA instruction which is unprofitable
71 /// on SNB+ try to replace it with other instructions.
72 /// According to Intel's Optimization Reference Manual:
73 /// " For LEA instructions with three source operands and some specific
74 /// situations, instruction latency has increased to 3 cycles, and must
75 /// dispatch via port 1:
76 /// - LEA that has all three source operands: base, index, and offset
77 /// - LEA that uses base and index registers where the base is EBP, RBP,
79 /// - LEA that uses RIP relative addressing mode
80 /// - LEA that uses 16-bit addressing mode "
81 /// This function currently handles the first 2 cases only.
82 MachineInstr *processInstrForSlow3OpLEA(MachineInstr &MI,
83 MachineFunction::iterator MFI);
85 /// \brief Look for LEAs that add 1 to reg or subtract 1 from reg
86 /// and convert them to INC or DEC respectively.
87 bool fixupIncDec(MachineBasicBlock::iterator &I,
88 MachineFunction::iterator MFI) const;
90 /// \brief Determine if an instruction references a machine register
91 /// and, if so, whether it reads or writes the register.
92 RegUsageState usesRegister(MachineOperand &p, MachineBasicBlock::iterator I);
94 /// \brief Step backwards through a basic block, looking
95 /// for an instruction which writes a register within
96 /// a maximum of INSTR_DISTANCE_THRESHOLD instruction latency cycles.
97 MachineBasicBlock::iterator searchBackwards(MachineOperand &p,
98 MachineBasicBlock::iterator &I,
99 MachineFunction::iterator MFI);
101 /// \brief if an instruction can be converted to an
102 /// equivalent LEA, insert the new instruction into the basic block
103 /// and return a pointer to it. Otherwise, return zero.
104 MachineInstr *postRAConvertToLEA(MachineFunction::iterator &MFI,
105 MachineBasicBlock::iterator &MBBI) const;
110 StringRef getPassName() const override { return FIXUPLEA_DESC; }
112 FixupLEAPass() : MachineFunctionPass(ID) {
113 initializeFixupLEAPassPass(*PassRegistry::getPassRegistry());
116 /// \brief Loop over all of the basic blocks,
117 /// replacing instructions by equivalent LEA instructions
118 /// if needed and when possible.
119 bool runOnMachineFunction(MachineFunction &MF) override;
121 // This pass runs after regalloc and doesn't support VReg operands.
122 MachineFunctionProperties getRequiredProperties() const override {
123 return MachineFunctionProperties().set(
124 MachineFunctionProperties::Property::NoVRegs);
129 const X86InstrInfo *TII; // Machine instruction info.
135 char FixupLEAPass::ID = 0;
137 INITIALIZE_PASS(FixupLEAPass, FIXUPLEA_NAME, FIXUPLEA_DESC, false, false)
140 FixupLEAPass::postRAConvertToLEA(MachineFunction::iterator &MFI,
141 MachineBasicBlock::iterator &MBBI) const {
142 MachineInstr &MI = *MBBI;
143 switch (MI.getOpcode()) {
146 const MachineOperand &Src = MI.getOperand(1);
147 const MachineOperand &Dest = MI.getOperand(0);
148 MachineInstr *NewMI =
149 BuildMI(*MF, MI.getDebugLoc(),
150 TII->get(MI.getOpcode() == X86::MOV32rr ? X86::LEA32r
158 MFI->insert(MBBI, NewMI); // Insert the new inst
163 case X86::ADD64ri32_DB:
164 case X86::ADD64ri8_DB:
167 case X86::ADD32ri_DB:
168 case X86::ADD32ri8_DB:
171 case X86::ADD16ri_DB:
172 case X86::ADD16ri8_DB:
173 if (!MI.getOperand(2).isImm()) {
174 // convertToThreeAddress will call getImm()
175 // which requires isImm() to be true
180 case X86::ADD16rr_DB:
181 if (MI.getOperand(1).getReg() != MI.getOperand(2).getReg()) {
182 // if src1 != src2, then convertToThreeAddress will
183 // need to create a Virtual register, which we cannot do
184 // after register allocation.
188 return TII->convertToThreeAddress(MFI, MI, nullptr);
191 FunctionPass *llvm::createX86FixupLEAs() { return new FixupLEAPass(); }
193 bool FixupLEAPass::runOnMachineFunction(MachineFunction &Func) {
194 if (skipFunction(Func.getFunction()))
198 const X86Subtarget &ST = Func.getSubtarget<X86Subtarget>();
199 OptIncDec = !ST.slowIncDec() || Func.getFunction().optForMinSize();
200 OptLEA = ST.LEAusesAG() || ST.slowLEA() || ST.slow3OpsLEA();
202 if (!OptLEA && !OptIncDec)
205 TII = ST.getInstrInfo();
207 DEBUG(dbgs() << "Start X86FixupLEAs\n";);
208 // Process all basic blocks.
209 for (MachineFunction::iterator I = Func.begin(), E = Func.end(); I != E; ++I)
210 processBasicBlock(Func, I);
211 DEBUG(dbgs() << "End X86FixupLEAs\n";);
216 FixupLEAPass::RegUsageState
217 FixupLEAPass::usesRegister(MachineOperand &p, MachineBasicBlock::iterator I) {
218 RegUsageState RegUsage = RU_NotUsed;
219 MachineInstr &MI = *I;
221 for (unsigned int i = 0; i < MI.getNumOperands(); ++i) {
222 MachineOperand &opnd = MI.getOperand(i);
223 if (opnd.isReg() && opnd.getReg() == p.getReg()) {
232 /// getPreviousInstr - Given a reference to an instruction in a basic
233 /// block, return a reference to the previous instruction in the block,
234 /// wrapping around to the last instruction of the block if the block
235 /// branches to itself.
236 static inline bool getPreviousInstr(MachineBasicBlock::iterator &I,
237 MachineFunction::iterator MFI) {
238 if (I == MFI->begin()) {
239 if (MFI->isPredecessor(&*MFI)) {
249 MachineBasicBlock::iterator
250 FixupLEAPass::searchBackwards(MachineOperand &p, MachineBasicBlock::iterator &I,
251 MachineFunction::iterator MFI) {
252 int InstrDistance = 1;
253 MachineBasicBlock::iterator CurInst;
254 static const int INSTR_DISTANCE_THRESHOLD = 5;
258 Found = getPreviousInstr(CurInst, MFI);
259 while (Found && I != CurInst) {
260 if (CurInst->isCall() || CurInst->isInlineAsm())
262 if (InstrDistance > INSTR_DISTANCE_THRESHOLD)
263 break; // too far back to make a difference
264 if (usesRegister(p, CurInst) == RU_Write) {
267 InstrDistance += TII->getInstrLatency(
268 MF->getSubtarget().getInstrItineraryData(), *CurInst);
269 Found = getPreviousInstr(CurInst, MFI);
271 return MachineBasicBlock::iterator();
274 static inline bool isLEA(const int Opcode) {
275 return Opcode == X86::LEA16r || Opcode == X86::LEA32r ||
276 Opcode == X86::LEA64r || Opcode == X86::LEA64_32r;
279 static inline bool isInefficientLEAReg(unsigned int Reg) {
280 return Reg == X86::EBP || Reg == X86::RBP || Reg == X86::R13;
283 static inline bool isRegOperand(const MachineOperand &Op) {
284 return Op.isReg() && Op.getReg() != X86::NoRegister;
286 /// hasIneffecientLEARegs - LEA that uses base and index registers
287 /// where the base is EBP, RBP, or R13
288 static inline bool hasInefficientLEABaseReg(const MachineOperand &Base,
289 const MachineOperand &Index) {
290 return Base.isReg() && isInefficientLEAReg(Base.getReg()) &&
294 static inline bool hasLEAOffset(const MachineOperand &Offset) {
295 return (Offset.isImm() && Offset.getImm() != 0) || Offset.isGlobal();
298 // LEA instruction that has all three operands: offset, base and index
299 static inline bool isThreeOperandsLEA(const MachineOperand &Base,
300 const MachineOperand &Index,
301 const MachineOperand &Offset) {
302 return isRegOperand(Base) && isRegOperand(Index) && hasLEAOffset(Offset);
305 static inline int getADDrrFromLEA(int LEAOpcode) {
308 llvm_unreachable("Unexpected LEA instruction");
319 static inline int getADDriFromLEA(int LEAOpcode, const MachineOperand &Offset) {
320 bool IsInt8 = Offset.isImm() && isInt<8>(Offset.getImm());
323 llvm_unreachable("Unexpected LEA instruction");
325 return IsInt8 ? X86::ADD16ri8 : X86::ADD16ri;
328 return IsInt8 ? X86::ADD32ri8 : X86::ADD32ri;
330 return IsInt8 ? X86::ADD64ri8 : X86::ADD64ri32;
334 /// isLEASimpleIncOrDec - Does this LEA have one these forms:
335 /// lea %reg, 1(%reg)
336 /// lea %reg, -1(%reg)
337 static inline bool isLEASimpleIncOrDec(MachineInstr &LEA) {
338 unsigned SrcReg = LEA.getOperand(1 + X86::AddrBaseReg).getReg();
339 unsigned DstReg = LEA.getOperand(0).getReg();
340 unsigned AddrDispOp = 1 + X86::AddrDisp;
341 return SrcReg == DstReg &&
342 LEA.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
343 LEA.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
344 LEA.getOperand(AddrDispOp).isImm() &&
345 (LEA.getOperand(AddrDispOp).getImm() == 1 ||
346 LEA.getOperand(AddrDispOp).getImm() == -1);
349 bool FixupLEAPass::fixupIncDec(MachineBasicBlock::iterator &I,
350 MachineFunction::iterator MFI) const {
351 MachineInstr &MI = *I;
352 int Opcode = MI.getOpcode();
356 if (isLEASimpleIncOrDec(MI) && TII->isSafeToClobberEFLAGS(*MFI, I)) {
358 bool isINC = MI.getOperand(4).getImm() == 1;
361 NewOpcode = isINC ? X86::INC16r : X86::DEC16r;
365 NewOpcode = isINC ? X86::INC32r : X86::DEC32r;
368 NewOpcode = isINC ? X86::INC64r : X86::DEC64r;
372 MachineInstr *NewMI =
373 BuildMI(*MFI, I, MI.getDebugLoc(), TII->get(NewOpcode))
374 .add(MI.getOperand(0))
375 .add(MI.getOperand(1));
377 I = static_cast<MachineBasicBlock::iterator>(NewMI);
383 void FixupLEAPass::processInstruction(MachineBasicBlock::iterator &I,
384 MachineFunction::iterator MFI) {
385 // Process a load, store, or LEA instruction.
386 MachineInstr &MI = *I;
387 const MCInstrDesc &Desc = MI.getDesc();
388 int AddrOffset = X86II::getMemoryOperandNo(Desc.TSFlags);
389 if (AddrOffset >= 0) {
390 AddrOffset += X86II::getOperandBias(Desc);
391 MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg);
392 if (p.isReg() && p.getReg() != X86::ESP) {
393 seekLEAFixup(p, I, MFI);
395 MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg);
396 if (q.isReg() && q.getReg() != X86::ESP) {
397 seekLEAFixup(q, I, MFI);
402 void FixupLEAPass::seekLEAFixup(MachineOperand &p,
403 MachineBasicBlock::iterator &I,
404 MachineFunction::iterator MFI) {
405 MachineBasicBlock::iterator MBI = searchBackwards(p, I, MFI);
406 if (MBI != MachineBasicBlock::iterator()) {
407 MachineInstr *NewMI = postRAConvertToLEA(MFI, MBI);
410 DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MBI->dump(););
411 // now to replace with an equivalent LEA...
412 DEBUG(dbgs() << "FixLEA: Replaced by: "; NewMI->dump(););
414 MachineBasicBlock::iterator J =
415 static_cast<MachineBasicBlock::iterator>(NewMI);
416 processInstruction(J, MFI);
421 void FixupLEAPass::processInstructionForSLM(MachineBasicBlock::iterator &I,
422 MachineFunction::iterator MFI) {
423 MachineInstr &MI = *I;
424 const int Opcode = MI.getOpcode();
427 if (MI.getOperand(5).getReg() != 0 || !MI.getOperand(4).isImm() ||
428 !TII->isSafeToClobberEFLAGS(*MFI, I))
430 const unsigned DstR = MI.getOperand(0).getReg();
431 const unsigned SrcR1 = MI.getOperand(1).getReg();
432 const unsigned SrcR2 = MI.getOperand(3).getReg();
433 if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
435 if (MI.getOperand(2).getImm() > 1)
437 DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump(););
438 DEBUG(dbgs() << "FixLEA: Replaced by: ";);
439 MachineInstr *NewMI = nullptr;
440 // Make ADD instruction for two registers writing to LEA's destination
441 if (SrcR1 != 0 && SrcR2 != 0) {
442 const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode));
443 const MachineOperand &Src = MI.getOperand(SrcR1 == DstR ? 3 : 1);
445 BuildMI(*MFI, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src);
446 DEBUG(NewMI->dump(););
448 // Make ADD instruction for immediate
449 if (MI.getOperand(4).getImm() != 0) {
450 const MCInstrDesc &ADDri =
451 TII->get(getADDriFromLEA(Opcode, MI.getOperand(4)));
452 const MachineOperand &SrcR = MI.getOperand(SrcR1 == DstR ? 1 : 3);
453 NewMI = BuildMI(*MFI, I, MI.getDebugLoc(), ADDri, DstR)
455 .addImm(MI.getOperand(4).getImm());
456 DEBUG(NewMI->dump(););
465 FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI,
466 MachineFunction::iterator MFI) {
468 const int LEAOpcode = MI.getOpcode();
469 if (!isLEA(LEAOpcode))
472 const MachineOperand &Dst = MI.getOperand(0);
473 const MachineOperand &Base = MI.getOperand(1);
474 const MachineOperand &Scale = MI.getOperand(2);
475 const MachineOperand &Index = MI.getOperand(3);
476 const MachineOperand &Offset = MI.getOperand(4);
477 const MachineOperand &Segment = MI.getOperand(5);
479 if (!(isThreeOperandsLEA(Base, Index, Offset) ||
480 hasInefficientLEABaseReg(Base, Index)) ||
481 !TII->isSafeToClobberEFLAGS(*MFI, MI) ||
482 Segment.getReg() != X86::NoRegister)
485 unsigned int DstR = Dst.getReg();
486 unsigned int BaseR = Base.getReg();
487 unsigned int IndexR = Index.getReg();
489 (LEAOpcode == X86::LEA64_32r) ? getX86SubSuperRegister(DstR, 64) : DstR;
490 bool IsScale1 = Scale.getImm() == 1;
491 bool IsInefficientBase = isInefficientLEAReg(BaseR);
492 bool IsInefficientIndex = isInefficientLEAReg(IndexR);
494 // Skip these cases since it takes more than 2 instructions
495 // to replace the LEA instruction.
496 if (IsInefficientBase && SSDstR == BaseR && !IsScale1)
498 if (LEAOpcode == X86::LEA64_32r && IsInefficientBase &&
499 (IsInefficientIndex || !IsScale1))
502 const DebugLoc DL = MI.getDebugLoc();
503 const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(LEAOpcode));
504 const MCInstrDesc &ADDri = TII->get(getADDriFromLEA(LEAOpcode, Offset));
506 DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MI.dump(););
507 DEBUG(dbgs() << "FixLEA: Replaced by: ";);
509 // First try to replace LEA with one or two (for the 3-op LEA case)
511 // 1.lea (%base,%index,1), %base => add %index,%base
512 // 2.lea (%base,%index,1), %index => add %base,%index
513 if (IsScale1 && (DstR == BaseR || DstR == IndexR)) {
514 const MachineOperand &Src = DstR == BaseR ? Index : Base;
515 MachineInstr *NewMI =
516 BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Src);
517 DEBUG(NewMI->dump(););
518 // Create ADD instruction for the Offset in case of 3-Ops LEA.
519 if (hasLEAOffset(Offset)) {
520 NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
521 DEBUG(NewMI->dump(););
525 // If the base is inefficient try switching the index and base operands,
526 // otherwise just break the 3-Ops LEA inst into 2-Ops LEA + ADD instruction:
527 // lea offset(%base,%index,scale),%dst =>
528 // lea (%base,%index,scale); add offset,%dst
529 if (!IsInefficientBase || (!IsInefficientIndex && IsScale1)) {
530 MachineInstr *NewMI = BuildMI(*MFI, MI, DL, TII->get(LEAOpcode))
532 .add(IsInefficientBase ? Index : Base)
534 .add(IsInefficientBase ? Base : Index)
537 DEBUG(NewMI->dump(););
538 // Create ADD instruction for the Offset in case of 3-Ops LEA.
539 if (hasLEAOffset(Offset)) {
540 NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
541 DEBUG(NewMI->dump(););
545 // Handle the rest of the cases with inefficient base register:
546 assert(SSDstR != BaseR && "SSDstR == BaseR should be handled already!");
547 assert(IsInefficientBase && "efficient base should be handled already!");
549 // lea (%base,%index,1), %dst => mov %base,%dst; add %index,%dst
550 if (IsScale1 && !hasLEAOffset(Offset)) {
551 TII->copyPhysReg(*MFI, MI, DL, DstR, BaseR, Base.isKill());
552 DEBUG(MI.getPrevNode()->dump(););
554 MachineInstr *NewMI =
555 BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Index);
556 DEBUG(NewMI->dump(););
559 // lea offset(%base,%index,scale), %dst =>
560 // lea offset( ,%index,scale), %dst; add %base,%dst
561 MachineInstr *NewMI = BuildMI(*MFI, MI, DL, TII->get(LEAOpcode))
568 DEBUG(NewMI->dump(););
570 NewMI = BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Base);
571 DEBUG(NewMI->dump(););
575 bool FixupLEAPass::processBasicBlock(MachineFunction &MF,
576 MachineFunction::iterator MFI) {
578 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
580 if (fixupIncDec(I, MFI))
584 if (MF.getSubtarget<X86Subtarget>().isSLM())
585 processInstructionForSLM(I, MFI);
588 if (MF.getSubtarget<X86Subtarget>().slow3OpsLEA()) {
589 if (auto *NewMI = processInstrForSlow3OpLEA(*I, MFI)) {
594 processInstruction(I, MFI);