1 //===---- X86FixupSetCC.cpp - optimize usage of LEA instructions ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pass that fixes zero-extension of setcc patterns.
11 // X86 setcc instructions are modeled to have no input arguments, and a single
12 // GR8 output argument. This is consistent with other similar instructions
13 // (e.g. movb), but means it is impossible to directly generate a setcc into
14 // the lower GR8 of a specified GR32.
15 // This means that ISel must select (zext (setcc)) into something like
16 // seta %al; movzbl %al, %eax.
17 // Unfortunately, this can cause a stall due to the partial register write
18 // performed by the setcc. Instead, we can use:
19 // xor %eax, %eax; seta %al
20 // This both avoids the stall, and encodes shorter.
21 //===----------------------------------------------------------------------===//
24 #include "X86InstrInfo.h"
25 #include "X86Subtarget.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #define DEBUG_TYPE "x86-fixup-setcc"
35 STATISTIC(NumSubstZexts, "Number of setcc + zext pairs substituted");
38 class X86FixupSetCCPass : public MachineFunctionPass {
40 X86FixupSetCCPass() : MachineFunctionPass(ID) {}
42 const char *getPassName() const override { return "X86 Fixup SetCC"; }
44 bool runOnMachineFunction(MachineFunction &MF) override;
47 // Find the preceding instruction that imp-defs eflags.
48 MachineInstr *findFlagsImpDef(MachineBasicBlock *MBB,
49 MachineBasicBlock::reverse_iterator MI);
51 // Return true if MI imp-uses eflags.
52 bool impUsesFlags(MachineInstr *MI);
54 // Return true if this is the opcode of a SetCC instruction with a register
56 bool isSetCCr(unsigned Opode);
58 MachineRegisterInfo *MRI;
59 const X86InstrInfo *TII;
61 enum { SearchBound = 16 };
66 char X86FixupSetCCPass::ID = 0;
69 FunctionPass *llvm::createX86FixupSetCC() { return new X86FixupSetCCPass(); }
71 bool X86FixupSetCCPass::isSetCCr(unsigned Opcode) {
95 // We expect the instruction *immediately* before the setcc to imp-def
96 // EFLAGS (because of scheduling glue). To make this less brittle w.r.t
97 // scheduling, look backwards until we hit the beginning of the
98 // basic-block, or a small bound (to avoid quadratic behavior).
100 X86FixupSetCCPass::findFlagsImpDef(MachineBasicBlock *MBB,
101 MachineBasicBlock::reverse_iterator MI) {
102 auto MBBStart = MBB->instr_rend();
103 for (int i = 0; (i < SearchBound) && (MI != MBBStart); ++i, ++MI)
104 for (auto &Op : MI->implicit_operands())
105 if ((Op.getReg() == X86::EFLAGS) && (Op.isDef()))
111 bool X86FixupSetCCPass::impUsesFlags(MachineInstr *MI) {
112 for (auto &Op : MI->implicit_operands())
113 if ((Op.getReg() == X86::EFLAGS) && (Op.isUse()))
119 bool X86FixupSetCCPass::runOnMachineFunction(MachineFunction &MF) {
120 bool Changed = false;
121 MRI = &MF.getRegInfo();
122 TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
124 SmallVector<MachineInstr*, 4> ToErase;
126 for (auto &MBB : MF) {
127 for (auto &MI : MBB) {
128 // Find a setcc that is used by a zext.
129 // This doesn't have to be the only use, the transformation is safe
131 if (!isSetCCr(MI.getOpcode()))
134 MachineInstr *ZExt = nullptr;
135 for (auto &Use : MRI->use_instructions(MI.getOperand(0).getReg()))
136 if (Use.getOpcode() == X86::MOVZX32rr8)
142 // Find the preceding instruction that imp-defs eflags.
143 MachineInstr *FlagsDefMI = findFlagsImpDef(
144 MI.getParent(), MachineBasicBlock::reverse_iterator(&MI));
148 // We'd like to put something that clobbers eflags directly before
149 // FlagsDefMI. This can't hurt anything after FlagsDefMI, because
150 // it, itself, by definition, clobbers eflags. But it may happen that
151 // FlagsDefMI also *uses* eflags, in which case the transformation is
153 if (impUsesFlags(FlagsDefMI))
159 // On 32-bit, we need to be careful to force an ABCD register.
160 const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit()
162 : &X86::GR32_ABCDRegClass;
163 unsigned ZeroReg = MRI->createVirtualRegister(RC);
164 unsigned InsertReg = MRI->createVirtualRegister(RC);
166 // Initialize a register with 0. This must go before the eflags def
167 BuildMI(MBB, FlagsDefMI, MI.getDebugLoc(), TII->get(X86::MOV32r0),
170 // X86 setcc only takes an output GR8, so fake a GR32 input by inserting
171 // the setcc result into the low byte of the zeroed register.
172 BuildMI(*ZExt->getParent(), ZExt, ZExt->getDebugLoc(),
173 TII->get(X86::INSERT_SUBREG), InsertReg)
175 .addReg(MI.getOperand(0).getReg())
176 .addImm(X86::sub_8bit);
177 MRI->replaceRegWith(ZExt->getOperand(0).getReg(), InsertReg);
178 ToErase.push_back(ZExt);
182 for (auto &I : ToErase)
183 I->eraseFromParent();