1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the pass which converts floating point instructions from
11 // pseudo registers into register stack instructions. This pass uses live
12 // variable information to indicate where the FPn registers are used and their
15 // The x87 hardware tracks liveness of the stack registers, so it is necessary
16 // to implement exact liveness tracking between basic blocks. The CFG edges are
17 // partitioned into bundles where the same FP registers must be live in
18 // identical stack positions. Instructions are inserted at the end of each basic
19 // block to rearrange the live registers to match the outgoing bundle.
21 // This approach avoids splitting critical edges at the potential cost of more
22 // live register shuffling instructions when critical edges are present.
24 //===----------------------------------------------------------------------===//
27 #include "X86InstrInfo.h"
28 #include "llvm/ADT/DepthFirstIterator.h"
29 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/ADT/SmallPtrSet.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/CodeGen/EdgeBundles.h"
35 #include "llvm/CodeGen/LivePhysRegs.h"
36 #include "llvm/CodeGen/MachineFunctionPass.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/Passes.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/raw_ostream.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetSubtargetInfo.h"
51 #define DEBUG_TYPE "x86-codegen"
53 STATISTIC(NumFXCH, "Number of fxch instructions inserted");
54 STATISTIC(NumFP , "Number of floating point instructions");
57 const unsigned ScratchFPReg = 7;
59 struct FPS : public MachineFunctionPass {
61 FPS() : MachineFunctionPass(ID) {
62 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
63 // This is really only to keep valgrind quiet.
64 // The logic in isLive() is too much for it.
65 memset(Stack, 0, sizeof(Stack));
66 memset(RegMap, 0, sizeof(RegMap));
69 void getAnalysisUsage(AnalysisUsage &AU) const override {
71 AU.addRequired<EdgeBundles>();
72 AU.addPreservedID(MachineLoopInfoID);
73 AU.addPreservedID(MachineDominatorsID);
74 MachineFunctionPass::getAnalysisUsage(AU);
77 bool runOnMachineFunction(MachineFunction &MF) override;
79 MachineFunctionProperties getRequiredProperties() const override {
80 return MachineFunctionProperties().set(
81 MachineFunctionProperties::Property::NoVRegs);
84 StringRef getPassName() const override { return "X86 FP Stackifier"; }
87 const TargetInstrInfo *TII; // Machine instruction info.
89 // Two CFG edges are related if they leave the same block, or enter the same
90 // block. The transitive closure of an edge under this relation is a
91 // LiveBundle. It represents a set of CFG edges where the live FP stack
92 // registers must be allocated identically in the x87 stack.
94 // A LiveBundle is usually all the edges leaving a block, or all the edges
95 // entering a block, but it can contain more edges if critical edges are
98 // The set of live FP registers in a LiveBundle is calculated by bundleCFG,
99 // but the exact mapping of FP registers to stack slots is fixed later.
101 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c.
104 // Number of pre-assigned live registers in FixStack. This is 0 when the
105 // stack order has not yet been fixed.
108 // Assigned stack order for live-in registers.
109 // FixStack[i] == getStackEntry(i) for all i < FixCount.
110 unsigned char FixStack[8];
112 LiveBundle() : Mask(0), FixCount(0) {}
114 // Have the live registers been assigned a stack order yet?
115 bool isFixed() const { return !Mask || FixCount; }
118 // Numbered LiveBundle structs. LiveBundles[0] is used for all CFG edges
119 // with no live FP registers.
120 SmallVector<LiveBundle, 8> LiveBundles;
122 // The edge bundle analysis provides indices into the LiveBundles vector.
123 EdgeBundles *Bundles;
125 // Return a bitmask of FP registers in block's live-in list.
126 static unsigned calcLiveInMask(MachineBasicBlock *MBB) {
128 for (const auto &LI : MBB->liveins()) {
129 if (LI.PhysReg < X86::FP0 || LI.PhysReg > X86::FP6)
131 Mask |= 1 << (LI.PhysReg - X86::FP0);
136 // Partition all the CFG edges into LiveBundles.
137 void bundleCFG(MachineFunction &MF);
139 MachineBasicBlock *MBB; // Current basic block
141 // The hardware keeps track of how many FP registers are live, so we have
142 // to model that exactly. Usually, each live register corresponds to an
143 // FP<n> register, but when dealing with calls, returns, and inline
144 // assembly, it is sometimes necessary to have live scratch registers.
145 unsigned Stack[8]; // FP<n> Registers in each stack slot...
146 unsigned StackTop; // The current top of the FP stack.
149 NumFPRegs = 8 // Including scratch pseudo-registers.
152 // For each live FP<n> register, point to its Stack[] entry.
153 // The first entries correspond to FP0-FP6, the rest are scratch registers
154 // used when we need slightly different live registers than what the
155 // register allocator thinks.
156 unsigned RegMap[NumFPRegs];
158 // Set up our stack model to match the incoming registers to MBB.
159 void setupBlockStack();
161 // Shuffle live registers to match the expectations of successor blocks.
162 void finishBlockStack();
164 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
165 void dumpStack() const {
166 dbgs() << "Stack contents:";
167 for (unsigned i = 0; i != StackTop; ++i) {
168 dbgs() << " FP" << Stack[i];
169 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
174 /// getSlot - Return the stack slot number a particular register number is
176 unsigned getSlot(unsigned RegNo) const {
177 assert(RegNo < NumFPRegs && "Regno out of range!");
178 return RegMap[RegNo];
181 /// isLive - Is RegNo currently live in the stack?
182 bool isLive(unsigned RegNo) const {
183 unsigned Slot = getSlot(RegNo);
184 return Slot < StackTop && Stack[Slot] == RegNo;
187 /// getStackEntry - Return the X86::FP<n> register in register ST(i).
188 unsigned getStackEntry(unsigned STi) const {
190 report_fatal_error("Access past stack top!");
191 return Stack[StackTop-1-STi];
194 /// getSTReg - Return the X86::ST(i) register which contains the specified
195 /// FP<RegNo> register.
196 unsigned getSTReg(unsigned RegNo) const {
197 return StackTop - 1 - getSlot(RegNo) + X86::ST0;
200 // pushReg - Push the specified FP<n> register onto the stack.
201 void pushReg(unsigned Reg) {
202 assert(Reg < NumFPRegs && "Register number out of range!");
204 report_fatal_error("Stack overflow!");
205 Stack[StackTop] = Reg;
206 RegMap[Reg] = StackTop++;
209 // popReg - Pop a register from the stack.
212 report_fatal_error("Cannot pop empty stack!");
213 RegMap[Stack[--StackTop]] = ~0; // Update state
216 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
217 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
218 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
219 if (isAtTop(RegNo)) return;
221 unsigned STReg = getSTReg(RegNo);
222 unsigned RegOnTop = getStackEntry(0);
224 // Swap the slots the regs are in.
225 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
227 // Swap stack slot contents.
228 if (RegMap[RegOnTop] >= StackTop)
229 report_fatal_error("Access past stack top!");
230 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
232 // Emit an fxch to update the runtime processors version of the state.
233 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
237 void duplicateToTop(unsigned RegNo, unsigned AsReg,
238 MachineBasicBlock::iterator I) {
239 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
240 unsigned STReg = getSTReg(RegNo);
241 pushReg(AsReg); // New register on top of stack
243 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
246 /// popStackAfter - Pop the current value off of the top of the FP stack
247 /// after the specified instruction.
248 void popStackAfter(MachineBasicBlock::iterator &I);
250 /// freeStackSlotAfter - Free the specified register from the register
251 /// stack, so that it is no longer in a register. If the register is
252 /// currently at the top of the stack, we just pop the current instruction,
253 /// otherwise we store the current top-of-stack into the specified slot,
254 /// then pop the top of stack.
255 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
257 /// freeStackSlotBefore - Just the pop, no folding. Return the inserted
259 MachineBasicBlock::iterator
260 freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo);
262 /// Adjust the live registers to be the set in Mask.
263 void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I);
265 /// Shuffle the top FixCount stack entries such that FP reg FixStack[0] is
266 /// st(0), FP reg FixStack[1] is st(1) etc.
267 void shuffleStackTop(const unsigned char *FixStack, unsigned FixCount,
268 MachineBasicBlock::iterator I);
270 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
272 void handleCall(MachineBasicBlock::iterator &I);
273 void handleReturn(MachineBasicBlock::iterator &I);
274 void handleZeroArgFP(MachineBasicBlock::iterator &I);
275 void handleOneArgFP(MachineBasicBlock::iterator &I);
276 void handleOneArgFPRW(MachineBasicBlock::iterator &I);
277 void handleTwoArgFP(MachineBasicBlock::iterator &I);
278 void handleCompareFP(MachineBasicBlock::iterator &I);
279 void handleCondMovFP(MachineBasicBlock::iterator &I);
280 void handleSpecialFP(MachineBasicBlock::iterator &I);
282 // Check if a COPY instruction is using FP registers.
283 static bool isFPCopy(MachineInstr &MI) {
284 unsigned DstReg = MI.getOperand(0).getReg();
285 unsigned SrcReg = MI.getOperand(1).getReg();
287 return X86::RFP80RegClass.contains(DstReg) ||
288 X86::RFP80RegClass.contains(SrcReg);
291 void setKillFlags(MachineBasicBlock &MBB) const;
296 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
298 /// getFPReg - Return the X86::FPx register number for the specified operand.
299 /// For example, this returns 3 for X86::FP3.
300 static unsigned getFPReg(const MachineOperand &MO) {
301 assert(MO.isReg() && "Expected an FP register!");
302 unsigned Reg = MO.getReg();
303 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
304 return Reg - X86::FP0;
307 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
308 /// register references into FP stack references.
310 bool FPS::runOnMachineFunction(MachineFunction &MF) {
311 // We only need to run this pass if there are any FP registers used in this
312 // function. If it is all integer, there is nothing for us to do!
313 bool FPIsUsed = false;
315 static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!");
316 const MachineRegisterInfo &MRI = MF.getRegInfo();
317 for (unsigned i = 0; i <= 6; ++i)
318 if (!MRI.reg_nodbg_empty(X86::FP0 + i)) {
324 if (!FPIsUsed) return false;
326 Bundles = &getAnalysis<EdgeBundles>();
327 TII = MF.getSubtarget().getInstrInfo();
329 // Prepare cross-MBB liveness.
334 // Process the function in depth first order so that we process at least one
335 // of the predecessors for every reachable block in the function.
336 df_iterator_default_set<MachineBasicBlock*> Processed;
337 MachineBasicBlock *Entry = &MF.front();
340 LiveBundles[Bundles->getBundle(Entry->getNumber(), false)];
342 // In regcall convention, some FP registers may not be passed through
343 // the stack, so they will need to be assigned to the stack first
344 if ((Entry->getParent()->getFunction()->getCallingConv() ==
345 CallingConv::X86_RegCall) && (Bundle.Mask && !Bundle.FixCount)) {
346 // In the register calling convention, up to one FP argument could be
347 // saved in the first FP register.
348 // If bundle.mask is non-zero and Bundle.FixCount is zero, it means
349 // that the FP registers contain arguments.
350 // The actual value is passed in FP0.
351 // Here we fix the stack and mark FP0 as pre-assigned register.
352 assert((Bundle.Mask & 0xFE) == 0 &&
353 "Only FP0 could be passed as an argument");
355 Bundle.FixStack[0] = 0;
358 bool Changed = false;
359 for (MachineBasicBlock *BB : depth_first_ext(Entry, Processed))
360 Changed |= processBasicBlock(MF, *BB);
362 // Process any unreachable blocks in arbitrary order now.
363 if (MF.size() != Processed.size())
364 for (MachineBasicBlock &BB : MF)
365 if (Processed.insert(&BB).second)
366 Changed |= processBasicBlock(MF, BB);
373 /// bundleCFG - Scan all the basic blocks to determine consistent live-in and
374 /// live-out sets for the FP registers. Consistent means that the set of
375 /// registers live-out from a block is identical to the live-in set of all
376 /// successors. This is not enforced by the normal live-in lists since
377 /// registers may be implicitly defined, or not used by all successors.
378 void FPS::bundleCFG(MachineFunction &MF) {
379 assert(LiveBundles.empty() && "Stale data in LiveBundles");
380 LiveBundles.resize(Bundles->getNumBundles());
382 // Gather the actual live-in masks for all MBBs.
383 for (MachineBasicBlock &MBB : MF) {
384 const unsigned Mask = calcLiveInMask(&MBB);
387 // Update MBB ingoing bundle mask.
388 LiveBundles[Bundles->getBundle(MBB.getNumber(), false)].Mask |= Mask;
392 /// processBasicBlock - Loop over all of the instructions in the basic block,
393 /// transforming FP instructions into their stack form.
395 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
396 bool Changed = false;
402 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
403 MachineInstr &MI = *I;
404 uint64_t Flags = MI.getDesc().TSFlags;
406 unsigned FPInstClass = Flags & X86II::FPTypeMask;
407 if (MI.isInlineAsm())
408 FPInstClass = X86II::SpecialFP;
410 if (MI.isCopy() && isFPCopy(MI))
411 FPInstClass = X86II::SpecialFP;
413 if (MI.isImplicitDef() &&
414 X86::RFP80RegClass.contains(MI.getOperand(0).getReg()))
415 FPInstClass = X86II::SpecialFP;
418 FPInstClass = X86II::SpecialFP;
420 if (FPInstClass == X86II::NotFP)
421 continue; // Efficiently ignore non-fp insts!
423 MachineInstr *PrevMI = nullptr;
425 PrevMI = &*std::prev(I);
427 ++NumFP; // Keep track of # of pseudo instrs
428 DEBUG(dbgs() << "\nFPInst:\t" << MI);
430 // Get dead variables list now because the MI pointer may be deleted as part
432 SmallVector<unsigned, 8> DeadRegs;
433 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
434 const MachineOperand &MO = MI.getOperand(i);
435 if (MO.isReg() && MO.isDead())
436 DeadRegs.push_back(MO.getReg());
439 switch (FPInstClass) {
440 case X86II::ZeroArgFP: handleZeroArgFP(I); break;
441 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
442 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
443 case X86II::TwoArgFP: handleTwoArgFP(I); break;
444 case X86II::CompareFP: handleCompareFP(I); break;
445 case X86II::CondMovFP: handleCondMovFP(I); break;
446 case X86II::SpecialFP: handleSpecialFP(I); break;
447 default: llvm_unreachable("Unknown FP Type!");
450 // Check to see if any of the values defined by this instruction are dead
451 // after definition. If so, pop them.
452 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
453 unsigned Reg = DeadRegs[i];
454 // Check if Reg is live on the stack. An inline-asm register operand that
455 // is in the clobber list and marked dead might not be live on the stack.
456 if (Reg >= X86::FP0 && Reg <= X86::FP6 && isLive(Reg-X86::FP0)) {
457 DEBUG(dbgs() << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
458 freeStackSlotAfter(I, Reg-X86::FP0);
462 // Print out all of the instructions expanded to if -debug
464 MachineBasicBlock::iterator PrevI = PrevMI;
466 dbgs() << "Just deleted pseudo instruction\n";
468 MachineBasicBlock::iterator Start = I;
469 // Rewind to first instruction newly inserted.
470 while (Start != BB.begin() && std::prev(Start) != PrevI)
472 dbgs() << "Inserted instructions:\n\t";
473 Start->print(dbgs());
474 while (++Start != std::next(I)) {
489 /// setupBlockStack - Use the live bundles to set up our model of the stack
490 /// to match predecessors' live out stack.
491 void FPS::setupBlockStack() {
492 DEBUG(dbgs() << "\nSetting up live-ins for BB#" << MBB->getNumber()
493 << " derived from " << MBB->getName() << ".\n");
495 // Get the live-in bundle for MBB.
496 const LiveBundle &Bundle =
497 LiveBundles[Bundles->getBundle(MBB->getNumber(), false)];
500 DEBUG(dbgs() << "Block has no FP live-ins.\n");
504 // Depth-first iteration should ensure that we always have an assigned stack.
505 assert(Bundle.isFixed() && "Reached block before any predecessors");
507 // Push the fixed live-in registers.
508 for (unsigned i = Bundle.FixCount; i > 0; --i) {
509 MBB->addLiveIn(X86::ST0+i-1);
510 DEBUG(dbgs() << "Live-in st(" << (i-1) << "): %FP"
511 << unsigned(Bundle.FixStack[i-1]) << '\n');
512 pushReg(Bundle.FixStack[i-1]);
515 // Kill off unwanted live-ins. This can happen with a critical edge.
516 // FIXME: We could keep these live registers around as zombies. They may need
517 // to be revived at the end of a short block. It might save a few instrs.
518 adjustLiveRegs(calcLiveInMask(MBB), MBB->begin());
522 /// finishBlockStack - Revive live-outs that are implicitly defined out of
523 /// MBB. Shuffle live registers to match the expected fixed stack of any
524 /// predecessors, and ensure that all predecessors are expecting the same
526 void FPS::finishBlockStack() {
527 // The RET handling below takes care of return blocks for us.
528 if (MBB->succ_empty())
531 DEBUG(dbgs() << "Setting up live-outs for BB#" << MBB->getNumber()
532 << " derived from " << MBB->getName() << ".\n");
534 // Get MBB's live-out bundle.
535 unsigned BundleIdx = Bundles->getBundle(MBB->getNumber(), true);
536 LiveBundle &Bundle = LiveBundles[BundleIdx];
538 // We may need to kill and define some registers to match successors.
539 // FIXME: This can probably be combined with the shuffle below.
540 MachineBasicBlock::iterator Term = MBB->getFirstTerminator();
541 adjustLiveRegs(Bundle.Mask, Term);
544 DEBUG(dbgs() << "No live-outs.\n");
548 // Has the stack order been fixed yet?
549 DEBUG(dbgs() << "LB#" << BundleIdx << ": ");
550 if (Bundle.isFixed()) {
551 DEBUG(dbgs() << "Shuffling stack to match.\n");
552 shuffleStackTop(Bundle.FixStack, Bundle.FixCount, Term);
554 // Not fixed yet, we get to choose.
555 DEBUG(dbgs() << "Fixing stack order now.\n");
556 Bundle.FixCount = StackTop;
557 for (unsigned i = 0; i < StackTop; ++i)
558 Bundle.FixStack[i] = getStackEntry(i);
563 //===----------------------------------------------------------------------===//
564 // Efficient Lookup Table Support
565 //===----------------------------------------------------------------------===//
571 bool operator<(const TableEntry &TE) const { return from < TE.from; }
572 friend bool operator<(const TableEntry &TE, unsigned V) {
575 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned V,
576 const TableEntry &TE) {
582 static int Lookup(ArrayRef<TableEntry> Table, unsigned Opcode) {
583 const TableEntry *I = std::lower_bound(Table.begin(), Table.end(), Opcode);
584 if (I != Table.end() && I->from == Opcode)
590 #define ASSERT_SORTED(TABLE)
592 #define ASSERT_SORTED(TABLE) \
593 { static bool TABLE##Checked = false; \
594 if (!TABLE##Checked) { \
595 assert(std::is_sorted(std::begin(TABLE), std::end(TABLE)) && \
596 "All lookup tables must be sorted for efficient access!"); \
597 TABLE##Checked = true; \
602 //===----------------------------------------------------------------------===//
603 // Register File -> Register Stack Mapping Methods
604 //===----------------------------------------------------------------------===//
606 // OpcodeTable - Sorted map of register instructions to their stack version.
607 // The first element is an register file pseudo instruction, the second is the
608 // concrete X86 instruction which uses the register stack.
610 static const TableEntry OpcodeTable[] = {
611 { X86::ABS_Fp32 , X86::ABS_F },
612 { X86::ABS_Fp64 , X86::ABS_F },
613 { X86::ABS_Fp80 , X86::ABS_F },
614 { X86::ADD_Fp32m , X86::ADD_F32m },
615 { X86::ADD_Fp64m , X86::ADD_F64m },
616 { X86::ADD_Fp64m32 , X86::ADD_F32m },
617 { X86::ADD_Fp80m32 , X86::ADD_F32m },
618 { X86::ADD_Fp80m64 , X86::ADD_F64m },
619 { X86::ADD_FpI16m32 , X86::ADD_FI16m },
620 { X86::ADD_FpI16m64 , X86::ADD_FI16m },
621 { X86::ADD_FpI16m80 , X86::ADD_FI16m },
622 { X86::ADD_FpI32m32 , X86::ADD_FI32m },
623 { X86::ADD_FpI32m64 , X86::ADD_FI32m },
624 { X86::ADD_FpI32m80 , X86::ADD_FI32m },
625 { X86::CHS_Fp32 , X86::CHS_F },
626 { X86::CHS_Fp64 , X86::CHS_F },
627 { X86::CHS_Fp80 , X86::CHS_F },
628 { X86::CMOVBE_Fp32 , X86::CMOVBE_F },
629 { X86::CMOVBE_Fp64 , X86::CMOVBE_F },
630 { X86::CMOVBE_Fp80 , X86::CMOVBE_F },
631 { X86::CMOVB_Fp32 , X86::CMOVB_F },
632 { X86::CMOVB_Fp64 , X86::CMOVB_F },
633 { X86::CMOVB_Fp80 , X86::CMOVB_F },
634 { X86::CMOVE_Fp32 , X86::CMOVE_F },
635 { X86::CMOVE_Fp64 , X86::CMOVE_F },
636 { X86::CMOVE_Fp80 , X86::CMOVE_F },
637 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
638 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
639 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
640 { X86::CMOVNB_Fp32 , X86::CMOVNB_F },
641 { X86::CMOVNB_Fp64 , X86::CMOVNB_F },
642 { X86::CMOVNB_Fp80 , X86::CMOVNB_F },
643 { X86::CMOVNE_Fp32 , X86::CMOVNE_F },
644 { X86::CMOVNE_Fp64 , X86::CMOVNE_F },
645 { X86::CMOVNE_Fp80 , X86::CMOVNE_F },
646 { X86::CMOVNP_Fp32 , X86::CMOVNP_F },
647 { X86::CMOVNP_Fp64 , X86::CMOVNP_F },
648 { X86::CMOVNP_Fp80 , X86::CMOVNP_F },
649 { X86::CMOVP_Fp32 , X86::CMOVP_F },
650 { X86::CMOVP_Fp64 , X86::CMOVP_F },
651 { X86::CMOVP_Fp80 , X86::CMOVP_F },
652 { X86::COS_Fp32 , X86::COS_F },
653 { X86::COS_Fp64 , X86::COS_F },
654 { X86::COS_Fp80 , X86::COS_F },
655 { X86::DIVR_Fp32m , X86::DIVR_F32m },
656 { X86::DIVR_Fp64m , X86::DIVR_F64m },
657 { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
658 { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
659 { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
660 { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
661 { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
662 { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
663 { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
664 { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
665 { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
666 { X86::DIV_Fp32m , X86::DIV_F32m },
667 { X86::DIV_Fp64m , X86::DIV_F64m },
668 { X86::DIV_Fp64m32 , X86::DIV_F32m },
669 { X86::DIV_Fp80m32 , X86::DIV_F32m },
670 { X86::DIV_Fp80m64 , X86::DIV_F64m },
671 { X86::DIV_FpI16m32 , X86::DIV_FI16m },
672 { X86::DIV_FpI16m64 , X86::DIV_FI16m },
673 { X86::DIV_FpI16m80 , X86::DIV_FI16m },
674 { X86::DIV_FpI32m32 , X86::DIV_FI32m },
675 { X86::DIV_FpI32m64 , X86::DIV_FI32m },
676 { X86::DIV_FpI32m80 , X86::DIV_FI32m },
677 { X86::ILD_Fp16m32 , X86::ILD_F16m },
678 { X86::ILD_Fp16m64 , X86::ILD_F16m },
679 { X86::ILD_Fp16m80 , X86::ILD_F16m },
680 { X86::ILD_Fp32m32 , X86::ILD_F32m },
681 { X86::ILD_Fp32m64 , X86::ILD_F32m },
682 { X86::ILD_Fp32m80 , X86::ILD_F32m },
683 { X86::ILD_Fp64m32 , X86::ILD_F64m },
684 { X86::ILD_Fp64m64 , X86::ILD_F64m },
685 { X86::ILD_Fp64m80 , X86::ILD_F64m },
686 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
687 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
688 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
689 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
690 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
691 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
692 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
693 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
694 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
695 { X86::IST_Fp16m32 , X86::IST_F16m },
696 { X86::IST_Fp16m64 , X86::IST_F16m },
697 { X86::IST_Fp16m80 , X86::IST_F16m },
698 { X86::IST_Fp32m32 , X86::IST_F32m },
699 { X86::IST_Fp32m64 , X86::IST_F32m },
700 { X86::IST_Fp32m80 , X86::IST_F32m },
701 { X86::IST_Fp64m32 , X86::IST_FP64m },
702 { X86::IST_Fp64m64 , X86::IST_FP64m },
703 { X86::IST_Fp64m80 , X86::IST_FP64m },
704 { X86::LD_Fp032 , X86::LD_F0 },
705 { X86::LD_Fp064 , X86::LD_F0 },
706 { X86::LD_Fp080 , X86::LD_F0 },
707 { X86::LD_Fp132 , X86::LD_F1 },
708 { X86::LD_Fp164 , X86::LD_F1 },
709 { X86::LD_Fp180 , X86::LD_F1 },
710 { X86::LD_Fp32m , X86::LD_F32m },
711 { X86::LD_Fp32m64 , X86::LD_F32m },
712 { X86::LD_Fp32m80 , X86::LD_F32m },
713 { X86::LD_Fp64m , X86::LD_F64m },
714 { X86::LD_Fp64m80 , X86::LD_F64m },
715 { X86::LD_Fp80m , X86::LD_F80m },
716 { X86::MUL_Fp32m , X86::MUL_F32m },
717 { X86::MUL_Fp64m , X86::MUL_F64m },
718 { X86::MUL_Fp64m32 , X86::MUL_F32m },
719 { X86::MUL_Fp80m32 , X86::MUL_F32m },
720 { X86::MUL_Fp80m64 , X86::MUL_F64m },
721 { X86::MUL_FpI16m32 , X86::MUL_FI16m },
722 { X86::MUL_FpI16m64 , X86::MUL_FI16m },
723 { X86::MUL_FpI16m80 , X86::MUL_FI16m },
724 { X86::MUL_FpI32m32 , X86::MUL_FI32m },
725 { X86::MUL_FpI32m64 , X86::MUL_FI32m },
726 { X86::MUL_FpI32m80 , X86::MUL_FI32m },
727 { X86::SIN_Fp32 , X86::SIN_F },
728 { X86::SIN_Fp64 , X86::SIN_F },
729 { X86::SIN_Fp80 , X86::SIN_F },
730 { X86::SQRT_Fp32 , X86::SQRT_F },
731 { X86::SQRT_Fp64 , X86::SQRT_F },
732 { X86::SQRT_Fp80 , X86::SQRT_F },
733 { X86::ST_Fp32m , X86::ST_F32m },
734 { X86::ST_Fp64m , X86::ST_F64m },
735 { X86::ST_Fp64m32 , X86::ST_F32m },
736 { X86::ST_Fp80m32 , X86::ST_F32m },
737 { X86::ST_Fp80m64 , X86::ST_F64m },
738 { X86::ST_FpP80m , X86::ST_FP80m },
739 { X86::SUBR_Fp32m , X86::SUBR_F32m },
740 { X86::SUBR_Fp64m , X86::SUBR_F64m },
741 { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
742 { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
743 { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
744 { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
745 { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
746 { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
747 { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
748 { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
749 { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
750 { X86::SUB_Fp32m , X86::SUB_F32m },
751 { X86::SUB_Fp64m , X86::SUB_F64m },
752 { X86::SUB_Fp64m32 , X86::SUB_F32m },
753 { X86::SUB_Fp80m32 , X86::SUB_F32m },
754 { X86::SUB_Fp80m64 , X86::SUB_F64m },
755 { X86::SUB_FpI16m32 , X86::SUB_FI16m },
756 { X86::SUB_FpI16m64 , X86::SUB_FI16m },
757 { X86::SUB_FpI16m80 , X86::SUB_FI16m },
758 { X86::SUB_FpI32m32 , X86::SUB_FI32m },
759 { X86::SUB_FpI32m64 , X86::SUB_FI32m },
760 { X86::SUB_FpI32m80 , X86::SUB_FI32m },
761 { X86::TST_Fp32 , X86::TST_F },
762 { X86::TST_Fp64 , X86::TST_F },
763 { X86::TST_Fp80 , X86::TST_F },
764 { X86::UCOM_FpIr32 , X86::UCOM_FIr },
765 { X86::UCOM_FpIr64 , X86::UCOM_FIr },
766 { X86::UCOM_FpIr80 , X86::UCOM_FIr },
767 { X86::UCOM_Fpr32 , X86::UCOM_Fr },
768 { X86::UCOM_Fpr64 , X86::UCOM_Fr },
769 { X86::UCOM_Fpr80 , X86::UCOM_Fr },
772 static unsigned getConcreteOpcode(unsigned Opcode) {
773 ASSERT_SORTED(OpcodeTable);
774 int Opc = Lookup(OpcodeTable, Opcode);
775 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
779 //===----------------------------------------------------------------------===//
781 //===----------------------------------------------------------------------===//
783 // PopTable - Sorted map of instructions to their popping version. The first
784 // element is an instruction, the second is the version which pops.
786 static const TableEntry PopTable[] = {
787 { X86::ADD_FrST0 , X86::ADD_FPrST0 },
789 { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
790 { X86::DIV_FrST0 , X86::DIV_FPrST0 },
792 { X86::IST_F16m , X86::IST_FP16m },
793 { X86::IST_F32m , X86::IST_FP32m },
795 { X86::MUL_FrST0 , X86::MUL_FPrST0 },
797 { X86::ST_F32m , X86::ST_FP32m },
798 { X86::ST_F64m , X86::ST_FP64m },
799 { X86::ST_Frr , X86::ST_FPrr },
801 { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
802 { X86::SUB_FrST0 , X86::SUB_FPrST0 },
804 { X86::UCOM_FIr , X86::UCOM_FIPr },
806 { X86::UCOM_FPr , X86::UCOM_FPPr },
807 { X86::UCOM_Fr , X86::UCOM_FPr },
810 /// popStackAfter - Pop the current value off of the top of the FP stack after
811 /// the specified instruction. This attempts to be sneaky and combine the pop
812 /// into the instruction itself if possible. The iterator is left pointing to
813 /// the last instruction, be it a new pop instruction inserted, or the old
814 /// instruction if it was modified in place.
816 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
817 MachineInstr &MI = *I;
818 const DebugLoc &dl = MI.getDebugLoc();
819 ASSERT_SORTED(PopTable);
823 // Check to see if there is a popping version of this instruction...
824 int Opcode = Lookup(PopTable, I->getOpcode());
826 I->setDesc(TII->get(Opcode));
827 if (Opcode == X86::UCOM_FPPr)
829 } else { // Insert an explicit pop
830 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
834 /// freeStackSlotAfter - Free the specified register from the register stack, so
835 /// that it is no longer in a register. If the register is currently at the top
836 /// of the stack, we just pop the current instruction, otherwise we store the
837 /// current top-of-stack into the specified slot, then pop the top of stack.
838 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
839 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
844 // Otherwise, store the top of stack into the dead slot, killing the operand
845 // without having to add in an explicit xchg then pop.
847 I = freeStackSlotBefore(++I, FPRegNo);
850 /// freeStackSlotBefore - Free the specified register without trying any
852 MachineBasicBlock::iterator
853 FPS::freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo) {
854 unsigned STReg = getSTReg(FPRegNo);
855 unsigned OldSlot = getSlot(FPRegNo);
856 unsigned TopReg = Stack[StackTop-1];
857 Stack[OldSlot] = TopReg;
858 RegMap[TopReg] = OldSlot;
859 RegMap[FPRegNo] = ~0;
860 Stack[--StackTop] = ~0;
861 return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr))
866 /// adjustLiveRegs - Kill and revive registers such that exactly the FP
867 /// registers with a bit in Mask are live.
868 void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) {
869 unsigned Defs = Mask;
871 for (unsigned i = 0; i < StackTop; ++i) {
872 unsigned RegNo = Stack[i];
873 if (!(Defs & (1 << RegNo)))
874 // This register is live, but we don't want it.
875 Kills |= (1 << RegNo);
877 // We don't need to imp-def this live register.
878 Defs &= ~(1 << RegNo);
880 assert((Kills & Defs) == 0 && "Register needs killing and def'ing?");
882 // Produce implicit-defs for free by using killed registers.
883 while (Kills && Defs) {
884 unsigned KReg = countTrailingZeros(Kills);
885 unsigned DReg = countTrailingZeros(Defs);
886 DEBUG(dbgs() << "Renaming %FP" << KReg << " as imp %FP" << DReg << "\n");
887 std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]);
888 std::swap(RegMap[KReg], RegMap[DReg]);
889 Kills &= ~(1 << KReg);
890 Defs &= ~(1 << DReg);
893 // Kill registers by popping.
894 if (Kills && I != MBB->begin()) {
895 MachineBasicBlock::iterator I2 = std::prev(I);
897 unsigned KReg = getStackEntry(0);
898 if (!(Kills & (1 << KReg)))
900 DEBUG(dbgs() << "Popping %FP" << KReg << "\n");
902 Kills &= ~(1 << KReg);
906 // Manually kill the rest.
908 unsigned KReg = countTrailingZeros(Kills);
909 DEBUG(dbgs() << "Killing %FP" << KReg << "\n");
910 freeStackSlotBefore(I, KReg);
911 Kills &= ~(1 << KReg);
914 // Load zeros for all the imp-defs.
916 unsigned DReg = countTrailingZeros(Defs);
917 DEBUG(dbgs() << "Defining %FP" << DReg << " as 0\n");
918 BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0));
920 Defs &= ~(1 << DReg);
923 // Now we should have the correct registers live.
925 assert(StackTop == countPopulation(Mask) && "Live count mismatch");
928 /// shuffleStackTop - emit fxch instructions before I to shuffle the top
929 /// FixCount entries into the order given by FixStack.
930 /// FIXME: Is there a better algorithm than insertion sort?
931 void FPS::shuffleStackTop(const unsigned char *FixStack,
933 MachineBasicBlock::iterator I) {
934 // Move items into place, starting from the desired stack bottom.
936 // Old register at position FixCount.
937 unsigned OldReg = getStackEntry(FixCount);
938 // Desired register at position FixCount.
939 unsigned Reg = FixStack[FixCount];
942 // (Reg st0) (OldReg st0) = (Reg OldReg st0)
945 moveToTop(OldReg, I);
951 //===----------------------------------------------------------------------===//
952 // Instruction transformation implementation
953 //===----------------------------------------------------------------------===//
955 void FPS::handleCall(MachineBasicBlock::iterator &I) {
956 unsigned STReturns = 0;
957 const MachineFunction* MF = I->getParent()->getParent();
959 for (const auto &MO : I->operands()) {
963 unsigned R = MO.getReg() - X86::FP0;
966 if (MF->getFunction()->getCallingConv() != CallingConv::X86_RegCall) {
967 assert(MO.isDef() && MO.isImplicit());
974 unsigned N = countTrailingOnes(STReturns);
976 // FP registers used for function return must be consecutive starting at
978 assert(STReturns == 0 || (isMask_32(STReturns) && N <= 2));
980 // Reset the FP Stack - It is required because of possible leftovers from
981 // passed arguments. The caller should assume that the FP stack is
982 // returned empty (unless the callee returns values on FP stack).
986 for (unsigned I = 0; I < N; ++I)
990 /// If RET has an FP register use operand, pass the first one in ST(0) and
991 /// the second one in ST(1).
992 void FPS::handleReturn(MachineBasicBlock::iterator &I) {
993 MachineInstr &MI = *I;
995 // Find the register operands.
996 unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
997 unsigned LiveMask = 0;
999 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1000 MachineOperand &Op = MI.getOperand(i);
1001 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1003 // FP Register uses must be kills unless there are two uses of the same
1004 // register, in which case only one will be a kill.
1005 assert(Op.isUse() &&
1006 (Op.isKill() || // Marked kill.
1007 getFPReg(Op) == FirstFPRegOp || // Second instance.
1008 MI.killsRegister(Op.getReg())) && // Later use is marked kill.
1009 "Ret only defs operands, and values aren't live beyond it");
1011 if (FirstFPRegOp == ~0U)
1012 FirstFPRegOp = getFPReg(Op);
1014 assert(SecondFPRegOp == ~0U && "More than two fp operands!");
1015 SecondFPRegOp = getFPReg(Op);
1017 LiveMask |= (1 << getFPReg(Op));
1019 // Remove the operand so that later passes don't see it.
1020 MI.RemoveOperand(i);
1025 // We may have been carrying spurious live-ins, so make sure only the
1026 // returned registers are left live.
1027 adjustLiveRegs(LiveMask, MI);
1028 if (!LiveMask) return; // Quick check to see if any are possible.
1030 // There are only four possibilities here:
1031 // 1) we are returning a single FP value. In this case, it has to be in
1032 // ST(0) already, so just declare success by removing the value from the
1034 if (SecondFPRegOp == ~0U) {
1035 // Assert that the top of stack contains the right FP register.
1036 assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
1037 "Top of stack not the right register for RET!");
1039 // Ok, everything is good, mark the value as not being on the stack
1040 // anymore so that our assertion about the stack being empty at end of
1041 // block doesn't fire.
1046 // Otherwise, we are returning two values:
1047 // 2) If returning the same value for both, we only have one thing in the FP
1048 // stack. Consider: RET FP1, FP1
1049 if (StackTop == 1) {
1050 assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
1051 "Stack misconfiguration for RET!");
1053 // Duplicate the TOS so that we return it twice. Just pick some other FPx
1054 // register to hold it.
1055 unsigned NewReg = ScratchFPReg;
1056 duplicateToTop(FirstFPRegOp, NewReg, MI);
1057 FirstFPRegOp = NewReg;
1060 /// Okay we know we have two different FPx operands now:
1061 assert(StackTop == 2 && "Must have two values live!");
1063 /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently
1064 /// in ST(1). In this case, emit an fxch.
1065 if (getStackEntry(0) == SecondFPRegOp) {
1066 assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live");
1067 moveToTop(FirstFPRegOp, MI);
1070 /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in
1071 /// ST(1). Just remove both from our understanding of the stack and return.
1072 assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
1073 assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live");
1077 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
1079 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
1080 MachineInstr &MI = *I;
1081 unsigned DestReg = getFPReg(MI.getOperand(0));
1083 // Change from the pseudo instruction to the concrete instruction.
1084 MI.RemoveOperand(0); // Remove the explicit ST(0) operand
1085 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1087 // Result gets pushed on the stack.
1091 /// handleOneArgFP - fst <mem>, ST(0)
1093 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
1094 MachineInstr &MI = *I;
1095 unsigned NumOps = MI.getDesc().getNumOperands();
1096 assert((NumOps == X86::AddrNumOperands + 1 || NumOps == 1) &&
1097 "Can only handle fst* & ftst instructions!");
1099 // Is this the last use of the source register?
1100 unsigned Reg = getFPReg(MI.getOperand(NumOps - 1));
1101 bool KillsSrc = MI.killsRegister(X86::FP0 + Reg);
1103 // FISTP64m is strange because there isn't a non-popping versions.
1104 // If we have one _and_ we don't want to pop the operand, duplicate the value
1105 // on the stack instead of moving it. This ensure that popping the value is
1107 // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
1109 if (!KillsSrc && (MI.getOpcode() == X86::IST_Fp64m32 ||
1110 MI.getOpcode() == X86::ISTT_Fp16m32 ||
1111 MI.getOpcode() == X86::ISTT_Fp32m32 ||
1112 MI.getOpcode() == X86::ISTT_Fp64m32 ||
1113 MI.getOpcode() == X86::IST_Fp64m64 ||
1114 MI.getOpcode() == X86::ISTT_Fp16m64 ||
1115 MI.getOpcode() == X86::ISTT_Fp32m64 ||
1116 MI.getOpcode() == X86::ISTT_Fp64m64 ||
1117 MI.getOpcode() == X86::IST_Fp64m80 ||
1118 MI.getOpcode() == X86::ISTT_Fp16m80 ||
1119 MI.getOpcode() == X86::ISTT_Fp32m80 ||
1120 MI.getOpcode() == X86::ISTT_Fp64m80 ||
1121 MI.getOpcode() == X86::ST_FpP80m)) {
1122 duplicateToTop(Reg, ScratchFPReg, I);
1124 moveToTop(Reg, I); // Move to the top of the stack...
1127 // Convert from the pseudo instruction to the concrete instruction.
1128 MI.RemoveOperand(NumOps - 1); // Remove explicit ST(0) operand
1129 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1131 if (MI.getOpcode() == X86::IST_FP64m || MI.getOpcode() == X86::ISTT_FP16m ||
1132 MI.getOpcode() == X86::ISTT_FP32m || MI.getOpcode() == X86::ISTT_FP64m ||
1133 MI.getOpcode() == X86::ST_FP80m) {
1135 report_fatal_error("Stack empty??");
1137 } else if (KillsSrc) { // Last use of operand?
1143 /// handleOneArgFPRW: Handle instructions that read from the top of stack and
1144 /// replace the value with a newly computed value. These instructions may have
1145 /// non-fp operands after their FP operands.
1149 /// R1 = fadd R2, [mem]
1151 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
1152 MachineInstr &MI = *I;
1154 unsigned NumOps = MI.getDesc().getNumOperands();
1155 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
1158 // Is this the last use of the source register?
1159 unsigned Reg = getFPReg(MI.getOperand(1));
1160 bool KillsSrc = MI.killsRegister(X86::FP0 + Reg);
1163 // If this is the last use of the source register, just make sure it's on
1164 // the top of the stack.
1167 report_fatal_error("Stack cannot be empty!");
1169 pushReg(getFPReg(MI.getOperand(0)));
1171 // If this is not the last use of the source register, _copy_ it to the top
1173 duplicateToTop(Reg, getFPReg(MI.getOperand(0)), I);
1176 // Change from the pseudo instruction to the concrete instruction.
1177 MI.RemoveOperand(1); // Drop the source operand.
1178 MI.RemoveOperand(0); // Drop the destination operand.
1179 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1183 //===----------------------------------------------------------------------===//
1184 // Define tables of various ways to map pseudo instructions
1187 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
1188 static const TableEntry ForwardST0Table[] = {
1189 { X86::ADD_Fp32 , X86::ADD_FST0r },
1190 { X86::ADD_Fp64 , X86::ADD_FST0r },
1191 { X86::ADD_Fp80 , X86::ADD_FST0r },
1192 { X86::DIV_Fp32 , X86::DIV_FST0r },
1193 { X86::DIV_Fp64 , X86::DIV_FST0r },
1194 { X86::DIV_Fp80 , X86::DIV_FST0r },
1195 { X86::MUL_Fp32 , X86::MUL_FST0r },
1196 { X86::MUL_Fp64 , X86::MUL_FST0r },
1197 { X86::MUL_Fp80 , X86::MUL_FST0r },
1198 { X86::SUB_Fp32 , X86::SUB_FST0r },
1199 { X86::SUB_Fp64 , X86::SUB_FST0r },
1200 { X86::SUB_Fp80 , X86::SUB_FST0r },
1203 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
1204 static const TableEntry ReverseST0Table[] = {
1205 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative
1206 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative
1207 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative
1208 { X86::DIV_Fp32 , X86::DIVR_FST0r },
1209 { X86::DIV_Fp64 , X86::DIVR_FST0r },
1210 { X86::DIV_Fp80 , X86::DIVR_FST0r },
1211 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative
1212 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative
1213 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative
1214 { X86::SUB_Fp32 , X86::SUBR_FST0r },
1215 { X86::SUB_Fp64 , X86::SUBR_FST0r },
1216 { X86::SUB_Fp80 , X86::SUBR_FST0r },
1219 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
1220 static const TableEntry ForwardSTiTable[] = {
1221 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative
1222 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative
1223 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative
1224 { X86::DIV_Fp32 , X86::DIVR_FrST0 },
1225 { X86::DIV_Fp64 , X86::DIVR_FrST0 },
1226 { X86::DIV_Fp80 , X86::DIVR_FrST0 },
1227 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative
1228 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative
1229 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative
1230 { X86::SUB_Fp32 , X86::SUBR_FrST0 },
1231 { X86::SUB_Fp64 , X86::SUBR_FrST0 },
1232 { X86::SUB_Fp80 , X86::SUBR_FrST0 },
1235 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
1236 static const TableEntry ReverseSTiTable[] = {
1237 { X86::ADD_Fp32 , X86::ADD_FrST0 },
1238 { X86::ADD_Fp64 , X86::ADD_FrST0 },
1239 { X86::ADD_Fp80 , X86::ADD_FrST0 },
1240 { X86::DIV_Fp32 , X86::DIV_FrST0 },
1241 { X86::DIV_Fp64 , X86::DIV_FrST0 },
1242 { X86::DIV_Fp80 , X86::DIV_FrST0 },
1243 { X86::MUL_Fp32 , X86::MUL_FrST0 },
1244 { X86::MUL_Fp64 , X86::MUL_FrST0 },
1245 { X86::MUL_Fp80 , X86::MUL_FrST0 },
1246 { X86::SUB_Fp32 , X86::SUB_FrST0 },
1247 { X86::SUB_Fp64 , X86::SUB_FrST0 },
1248 { X86::SUB_Fp80 , X86::SUB_FrST0 },
1252 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
1253 /// instructions which need to be simplified and possibly transformed.
1255 /// Result: ST(0) = fsub ST(0), ST(i)
1256 /// ST(i) = fsub ST(0), ST(i)
1257 /// ST(0) = fsubr ST(0), ST(i)
1258 /// ST(i) = fsubr ST(0), ST(i)
1260 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
1261 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
1262 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
1263 MachineInstr &MI = *I;
1265 unsigned NumOperands = MI.getDesc().getNumOperands();
1266 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
1267 unsigned Dest = getFPReg(MI.getOperand(0));
1268 unsigned Op0 = getFPReg(MI.getOperand(NumOperands - 2));
1269 unsigned Op1 = getFPReg(MI.getOperand(NumOperands - 1));
1270 bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0);
1271 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1272 DebugLoc dl = MI.getDebugLoc();
1274 unsigned TOS = getStackEntry(0);
1276 // One of our operands must be on the top of the stack. If neither is yet, we
1277 // need to move one.
1278 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
1279 // We can choose to move either operand to the top of the stack. If one of
1280 // the operands is killed by this instruction, we want that one so that we
1281 // can update right on top of the old version.
1283 moveToTop(Op0, I); // Move dead operand to TOS.
1285 } else if (KillsOp1) {
1289 // All of the operands are live after this instruction executes, so we
1290 // cannot update on top of any operand. Because of this, we must
1291 // duplicate one of the stack elements to the top. It doesn't matter
1292 // which one we pick.
1294 duplicateToTop(Op0, Dest, I);
1298 } else if (!KillsOp0 && !KillsOp1) {
1299 // If we DO have one of our operands at the top of the stack, but we don't
1300 // have a dead operand, we must duplicate one of the operands to a new slot
1302 duplicateToTop(Op0, Dest, I);
1307 // Now we know that one of our operands is on the top of the stack, and at
1308 // least one of our operands is killed by this instruction.
1309 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
1310 "Stack conditions not set up right!");
1312 // We decide which form to use based on what is on the top of the stack, and
1313 // which operand is killed by this instruction.
1314 ArrayRef<TableEntry> InstTable;
1315 bool isForward = TOS == Op0;
1316 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
1319 InstTable = ForwardST0Table;
1321 InstTable = ReverseST0Table;
1324 InstTable = ForwardSTiTable;
1326 InstTable = ReverseSTiTable;
1329 int Opcode = Lookup(InstTable, MI.getOpcode());
1330 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
1332 // NotTOS - The register which is not on the top of stack...
1333 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
1335 // Replace the old instruction with a new instruction
1337 I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
1339 // If both operands are killed, pop one off of the stack in addition to
1340 // overwriting the other one.
1341 if (KillsOp0 && KillsOp1 && Op0 != Op1) {
1342 assert(!updateST0 && "Should have updated other operand!");
1343 popStackAfter(I); // Pop the top of stack
1346 // Update stack information so that we know the destination register is now on
1348 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
1349 assert(UpdatedSlot < StackTop && Dest < 7);
1350 Stack[UpdatedSlot] = Dest;
1351 RegMap[Dest] = UpdatedSlot;
1352 MBB->getParent()->DeleteMachineInstr(&MI); // Remove the old instruction
1355 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
1356 /// register arguments and no explicit destinations.
1358 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
1359 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
1360 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
1361 MachineInstr &MI = *I;
1363 unsigned NumOperands = MI.getDesc().getNumOperands();
1364 assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
1365 unsigned Op0 = getFPReg(MI.getOperand(NumOperands - 2));
1366 unsigned Op1 = getFPReg(MI.getOperand(NumOperands - 1));
1367 bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0);
1368 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1370 // Make sure the first operand is on the top of stack, the other one can be
1374 // Change from the pseudo instruction to the concrete instruction.
1375 MI.getOperand(0).setReg(getSTReg(Op1));
1376 MI.RemoveOperand(1);
1377 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1379 // If any of the operands are killed by this instruction, free them.
1380 if (KillsOp0) freeStackSlotAfter(I, Op0);
1381 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
1384 /// handleCondMovFP - Handle two address conditional move instructions. These
1385 /// instructions move a st(i) register to st(0) iff a condition is true. These
1386 /// instructions require that the first operand is at the top of the stack, but
1387 /// otherwise don't modify the stack at all.
1388 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
1389 MachineInstr &MI = *I;
1391 unsigned Op0 = getFPReg(MI.getOperand(0));
1392 unsigned Op1 = getFPReg(MI.getOperand(2));
1393 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1395 // The first operand *must* be on the top of the stack.
1398 // Change the second operand to the stack register that the operand is in.
1399 // Change from the pseudo instruction to the concrete instruction.
1400 MI.RemoveOperand(0);
1401 MI.RemoveOperand(1);
1402 MI.getOperand(0).setReg(getSTReg(Op1));
1403 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1405 // If we kill the second operand, make sure to pop it from the stack.
1406 if (Op0 != Op1 && KillsOp1) {
1407 // Get this value off of the register stack.
1408 freeStackSlotAfter(I, Op1);
1413 /// handleSpecialFP - Handle special instructions which behave unlike other
1414 /// floating point instructions. This is primarily intended for use by pseudo
1417 void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) {
1418 MachineInstr &MI = *Inst;
1425 if (MI.isReturn()) {
1430 switch (MI.getOpcode()) {
1431 default: llvm_unreachable("Unknown SpecialFP instruction!");
1432 case TargetOpcode::COPY: {
1433 // We handle three kinds of copies: FP <- FP, FP <- ST, and ST <- FP.
1434 const MachineOperand &MO1 = MI.getOperand(1);
1435 const MachineOperand &MO0 = MI.getOperand(0);
1436 bool KillsSrc = MI.killsRegister(MO1.getReg());
1439 unsigned DstFP = getFPReg(MO0);
1440 unsigned SrcFP = getFPReg(MO1);
1441 assert(isLive(SrcFP) && "Cannot copy dead register");
1443 // If the input operand is killed, we can just change the owner of the
1444 // incoming stack slot into the result.
1445 unsigned Slot = getSlot(SrcFP);
1446 Stack[Slot] = DstFP;
1447 RegMap[DstFP] = Slot;
1449 // For COPY we just duplicate the specified value to a new stack slot.
1450 // This could be made better, but would require substantial changes.
1451 duplicateToTop(SrcFP, DstFP, Inst);
1456 case TargetOpcode::IMPLICIT_DEF: {
1457 // All FP registers must be explicitly defined, so load a 0 instead.
1458 unsigned Reg = MI.getOperand(0).getReg() - X86::FP0;
1459 DEBUG(dbgs() << "Emitting LD_F0 for implicit FP" << Reg << '\n');
1460 BuildMI(*MBB, Inst, MI.getDebugLoc(), TII->get(X86::LD_F0));
1465 case TargetOpcode::INLINEASM: {
1466 // The inline asm MachineInstr currently only *uses* FP registers for the
1467 // 'f' constraint. These should be turned into the current ST(x) register
1468 // in the machine instr.
1470 // There are special rules for x87 inline assembly. The compiler must know
1471 // exactly how many registers are popped and pushed implicitly by the asm.
1472 // Otherwise it is not possible to restore the stack state after the inline
1475 // There are 3 kinds of input operands:
1477 // 1. Popped inputs. These must appear at the stack top in ST0-STn. A
1478 // popped input operand must be in a fixed stack slot, and it is either
1479 // tied to an output operand, or in the clobber list. The MI has ST use
1480 // and def operands for these inputs.
1482 // 2. Fixed inputs. These inputs appear in fixed stack slots, but are
1483 // preserved by the inline asm. The fixed stack slots must be STn-STm
1484 // following the popped inputs. A fixed input operand cannot be tied to
1485 // an output or appear in the clobber list. The MI has ST use operands
1486 // and no defs for these inputs.
1488 // 3. Preserved inputs. These inputs use the "f" constraint which is
1489 // represented as an FP register. The inline asm won't change these
1492 // Outputs must be in ST registers, FP outputs are not allowed. Clobbered
1493 // registers do not count as output operands. The inline asm changes the
1494 // stack as if it popped all the popped inputs and then pushed all the
1497 // Scan the assembly for ST registers used, defined and clobbered. We can
1498 // only tell clobbers from defs by looking at the asm descriptor.
1499 unsigned STUses = 0, STDefs = 0, STClobbers = 0, STDeadDefs = 0;
1500 unsigned NumOps = 0;
1501 SmallSet<unsigned, 1> FRegIdx;
1504 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI.getNumOperands();
1505 i != e && MI.getOperand(i).isImm(); i += 1 + NumOps) {
1506 unsigned Flags = MI.getOperand(i).getImm();
1508 NumOps = InlineAsm::getNumOperandRegisters(Flags);
1511 const MachineOperand &MO = MI.getOperand(i + 1);
1514 unsigned STReg = MO.getReg() - X86::FP0;
1518 // If the flag has a register class constraint, this must be an operand
1519 // with constraint "f". Record its index and continue.
1520 if (InlineAsm::hasRegClassConstraint(Flags, RCID)) {
1521 FRegIdx.insert(i + 1);
1525 switch (InlineAsm::getKind(Flags)) {
1526 case InlineAsm::Kind_RegUse:
1527 STUses |= (1u << STReg);
1529 case InlineAsm::Kind_RegDef:
1530 case InlineAsm::Kind_RegDefEarlyClobber:
1531 STDefs |= (1u << STReg);
1533 STDeadDefs |= (1u << STReg);
1535 case InlineAsm::Kind_Clobber:
1536 STClobbers |= (1u << STReg);
1543 if (STUses && !isMask_32(STUses))
1544 MI.emitError("fixed input regs must be last on the x87 stack");
1545 unsigned NumSTUses = countTrailingOnes(STUses);
1547 // Defs must be contiguous from the stack top. ST0-STn.
1548 if (STDefs && !isMask_32(STDefs)) {
1549 MI.emitError("output regs must be last on the x87 stack");
1550 STDefs = NextPowerOf2(STDefs) - 1;
1552 unsigned NumSTDefs = countTrailingOnes(STDefs);
1554 // So must the clobbered stack slots. ST0-STm, m >= n.
1555 if (STClobbers && !isMask_32(STDefs | STClobbers))
1556 MI.emitError("clobbers must be last on the x87 stack");
1558 // Popped inputs are the ones that are also clobbered or defined.
1559 unsigned STPopped = STUses & (STDefs | STClobbers);
1560 if (STPopped && !isMask_32(STPopped))
1561 MI.emitError("implicitly popped regs must be last on the x87 stack");
1562 unsigned NumSTPopped = countTrailingOnes(STPopped);
1564 DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops "
1565 << NumSTPopped << ", and defines " << NumSTDefs << " regs.\n");
1568 // If any input operand uses constraint "f", all output register
1569 // constraints must be early-clobber defs.
1570 for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I)
1571 if (FRegIdx.count(I)) {
1572 assert((1 << getFPReg(MI.getOperand(I)) & STDefs) == 0 &&
1573 "Operands with constraint \"f\" cannot overlap with defs");
1577 // Collect all FP registers (register operands with constraints "t", "u",
1578 // and "f") to kill afer the instruction.
1579 unsigned FPKills = ((1u << NumFPRegs) - 1) & ~0xff;
1580 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1581 MachineOperand &Op = MI.getOperand(i);
1582 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1584 unsigned FPReg = getFPReg(Op);
1586 // If we kill this operand, make sure to pop it from the stack after the
1587 // asm. We just remember it for now, and pop them all off at the end in
1589 if (Op.isUse() && Op.isKill())
1590 FPKills |= 1U << FPReg;
1593 // Do not include registers that are implicitly popped by defs/clobbers.
1594 FPKills &= ~(STDefs | STClobbers);
1596 // Now we can rearrange the live registers to match what was requested.
1597 unsigned char STUsesArray[8];
1599 for (unsigned I = 0; I < NumSTUses; ++I)
1602 shuffleStackTop(STUsesArray, NumSTUses, Inst);
1603 DEBUG({dbgs() << "Before asm: "; dumpStack();});
1605 // With the stack layout fixed, rewrite the FP registers.
1606 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1607 MachineOperand &Op = MI.getOperand(i);
1608 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1611 unsigned FPReg = getFPReg(Op);
1613 if (FRegIdx.count(i))
1614 // Operand with constraint "f".
1615 Op.setReg(getSTReg(FPReg));
1617 // Operand with a single register class constraint ("t" or "u").
1618 Op.setReg(X86::ST0 + FPReg);
1621 // Simulate the inline asm popping its inputs and pushing its outputs.
1622 StackTop -= NumSTPopped;
1624 for (unsigned i = 0; i < NumSTDefs; ++i)
1625 pushReg(NumSTDefs - i - 1);
1627 // If this asm kills any FP registers (is the last use of them) we must
1628 // explicitly emit pop instructions for them. Do this now after the asm has
1629 // executed so that the ST(x) numbers are not off (which would happen if we
1630 // did this inline with operand rewriting).
1632 // Note: this might be a non-optimal pop sequence. We might be able to do
1633 // better by trying to pop in stack order or something.
1635 unsigned FPReg = countTrailingZeros(FPKills);
1637 freeStackSlotAfter(Inst, FPReg);
1638 FPKills &= ~(1U << FPReg);
1641 // Don't delete the inline asm!
1646 Inst = MBB->erase(Inst); // Remove the pseudo instruction
1648 // We want to leave I pointing to the previous instruction, but what if we
1649 // just erased the first instruction?
1650 if (Inst == MBB->begin()) {
1651 DEBUG(dbgs() << "Inserting dummy KILL\n");
1652 Inst = BuildMI(*MBB, Inst, DebugLoc(), TII->get(TargetOpcode::KILL));
1657 void FPS::setKillFlags(MachineBasicBlock &MBB) const {
1658 const TargetRegisterInfo *TRI =
1659 MBB.getParent()->getSubtarget().getRegisterInfo();
1660 LivePhysRegs LPR(TRI);
1662 LPR.addLiveOuts(MBB);
1664 for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend();
1666 if (I->isDebugValue())
1669 std::bitset<8> Defs;
1670 SmallVector<MachineOperand *, 2> Uses;
1671 MachineInstr &MI = *I;
1673 for (auto &MO : I->operands()) {
1677 unsigned Reg = MO.getReg() - X86::FP0;
1684 if (!LPR.contains(MO.getReg()))
1687 Uses.push_back(&MO);
1690 for (auto *MO : Uses)
1691 if (Defs.test(getFPReg(*MO)) || !LPR.contains(MO->getReg()))
1694 LPR.stepBackward(MI);