1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the pass which converts floating point instructions from
11 // pseudo registers into register stack instructions. This pass uses live
12 // variable information to indicate where the FPn registers are used and their
15 // The x87 hardware tracks liveness of the stack registers, so it is necessary
16 // to implement exact liveness tracking between basic blocks. The CFG edges are
17 // partitioned into bundles where the same FP registers must be live in
18 // identical stack positions. Instructions are inserted at the end of each basic
19 // block to rearrange the live registers to match the outgoing bundle.
21 // This approach avoids splitting critical edges at the potential cost of more
22 // live register shuffling instructions when critical edges are present.
24 //===----------------------------------------------------------------------===//
27 #include "X86InstrInfo.h"
28 #include "llvm/ADT/DepthFirstIterator.h"
29 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/ADT/SmallPtrSet.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/CodeGen/EdgeBundles.h"
35 #include "llvm/CodeGen/LivePhysRegs.h"
36 #include "llvm/CodeGen/MachineFunctionPass.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/Passes.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/raw_ostream.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetSubtargetInfo.h"
51 #define DEBUG_TYPE "x86-codegen"
53 STATISTIC(NumFXCH, "Number of fxch instructions inserted");
54 STATISTIC(NumFP , "Number of floating point instructions");
57 const unsigned ScratchFPReg = 7;
59 struct FPS : public MachineFunctionPass {
61 FPS() : MachineFunctionPass(ID) {
62 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
63 // This is really only to keep valgrind quiet.
64 // The logic in isLive() is too much for it.
65 memset(Stack, 0, sizeof(Stack));
66 memset(RegMap, 0, sizeof(RegMap));
69 void getAnalysisUsage(AnalysisUsage &AU) const override {
71 AU.addRequired<EdgeBundles>();
72 AU.addPreservedID(MachineLoopInfoID);
73 AU.addPreservedID(MachineDominatorsID);
74 MachineFunctionPass::getAnalysisUsage(AU);
77 bool runOnMachineFunction(MachineFunction &MF) override;
79 const char *getPassName() const override { return "X86 FP Stackifier"; }
82 const TargetInstrInfo *TII; // Machine instruction info.
84 // Two CFG edges are related if they leave the same block, or enter the same
85 // block. The transitive closure of an edge under this relation is a
86 // LiveBundle. It represents a set of CFG edges where the live FP stack
87 // registers must be allocated identically in the x87 stack.
89 // A LiveBundle is usually all the edges leaving a block, or all the edges
90 // entering a block, but it can contain more edges if critical edges are
93 // The set of live FP registers in a LiveBundle is calculated by bundleCFG,
94 // but the exact mapping of FP registers to stack slots is fixed later.
96 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c.
99 // Number of pre-assigned live registers in FixStack. This is 0 when the
100 // stack order has not yet been fixed.
103 // Assigned stack order for live-in registers.
104 // FixStack[i] == getStackEntry(i) for all i < FixCount.
105 unsigned char FixStack[8];
107 LiveBundle() : Mask(0), FixCount(0) {}
109 // Have the live registers been assigned a stack order yet?
110 bool isFixed() const { return !Mask || FixCount; }
113 // Numbered LiveBundle structs. LiveBundles[0] is used for all CFG edges
114 // with no live FP registers.
115 SmallVector<LiveBundle, 8> LiveBundles;
117 // The edge bundle analysis provides indices into the LiveBundles vector.
118 EdgeBundles *Bundles;
120 // Return a bitmask of FP registers in block's live-in list.
121 static unsigned calcLiveInMask(MachineBasicBlock *MBB) {
123 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
124 E = MBB->livein_end(); I != E; ++I) {
126 if (Reg < X86::FP0 || Reg > X86::FP6)
128 Mask |= 1 << (Reg - X86::FP0);
133 // Partition all the CFG edges into LiveBundles.
134 void bundleCFG(MachineFunction &MF);
136 MachineBasicBlock *MBB; // Current basic block
138 // The hardware keeps track of how many FP registers are live, so we have
139 // to model that exactly. Usually, each live register corresponds to an
140 // FP<n> register, but when dealing with calls, returns, and inline
141 // assembly, it is sometimes necessary to have live scratch registers.
142 unsigned Stack[8]; // FP<n> Registers in each stack slot...
143 unsigned StackTop; // The current top of the FP stack.
146 NumFPRegs = 8 // Including scratch pseudo-registers.
149 // For each live FP<n> register, point to its Stack[] entry.
150 // The first entries correspond to FP0-FP6, the rest are scratch registers
151 // used when we need slightly different live registers than what the
152 // register allocator thinks.
153 unsigned RegMap[NumFPRegs];
155 // Set up our stack model to match the incoming registers to MBB.
156 void setupBlockStack();
158 // Shuffle live registers to match the expectations of successor blocks.
159 void finishBlockStack();
161 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
162 void dumpStack() const {
163 dbgs() << "Stack contents:";
164 for (unsigned i = 0; i != StackTop; ++i) {
165 dbgs() << " FP" << Stack[i];
166 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
171 /// getSlot - Return the stack slot number a particular register number is
173 unsigned getSlot(unsigned RegNo) const {
174 assert(RegNo < NumFPRegs && "Regno out of range!");
175 return RegMap[RegNo];
178 /// isLive - Is RegNo currently live in the stack?
179 bool isLive(unsigned RegNo) const {
180 unsigned Slot = getSlot(RegNo);
181 return Slot < StackTop && Stack[Slot] == RegNo;
184 /// getStackEntry - Return the X86::FP<n> register in register ST(i).
185 unsigned getStackEntry(unsigned STi) const {
187 report_fatal_error("Access past stack top!");
188 return Stack[StackTop-1-STi];
191 /// getSTReg - Return the X86::ST(i) register which contains the specified
192 /// FP<RegNo> register.
193 unsigned getSTReg(unsigned RegNo) const {
194 return StackTop - 1 - getSlot(RegNo) + X86::ST0;
197 // pushReg - Push the specified FP<n> register onto the stack.
198 void pushReg(unsigned Reg) {
199 assert(Reg < NumFPRegs && "Register number out of range!");
201 report_fatal_error("Stack overflow!");
202 Stack[StackTop] = Reg;
203 RegMap[Reg] = StackTop++;
206 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
207 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
208 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
209 if (isAtTop(RegNo)) return;
211 unsigned STReg = getSTReg(RegNo);
212 unsigned RegOnTop = getStackEntry(0);
214 // Swap the slots the regs are in.
215 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
217 // Swap stack slot contents.
218 if (RegMap[RegOnTop] >= StackTop)
219 report_fatal_error("Access past stack top!");
220 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
222 // Emit an fxch to update the runtime processors version of the state.
223 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
227 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
228 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
229 unsigned STReg = getSTReg(RegNo);
230 pushReg(AsReg); // New register on top of stack
232 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
235 /// popStackAfter - Pop the current value off of the top of the FP stack
236 /// after the specified instruction.
237 void popStackAfter(MachineBasicBlock::iterator &I);
239 /// freeStackSlotAfter - Free the specified register from the register
240 /// stack, so that it is no longer in a register. If the register is
241 /// currently at the top of the stack, we just pop the current instruction,
242 /// otherwise we store the current top-of-stack into the specified slot,
243 /// then pop the top of stack.
244 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
246 /// freeStackSlotBefore - Just the pop, no folding. Return the inserted
248 MachineBasicBlock::iterator
249 freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo);
251 /// Adjust the live registers to be the set in Mask.
252 void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I);
254 /// Shuffle the top FixCount stack entries such that FP reg FixStack[0] is
255 /// st(0), FP reg FixStack[1] is st(1) etc.
256 void shuffleStackTop(const unsigned char *FixStack, unsigned FixCount,
257 MachineBasicBlock::iterator I);
259 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
261 void handleCall(MachineBasicBlock::iterator &I);
262 void handleZeroArgFP(MachineBasicBlock::iterator &I);
263 void handleOneArgFP(MachineBasicBlock::iterator &I);
264 void handleOneArgFPRW(MachineBasicBlock::iterator &I);
265 void handleTwoArgFP(MachineBasicBlock::iterator &I);
266 void handleCompareFP(MachineBasicBlock::iterator &I);
267 void handleCondMovFP(MachineBasicBlock::iterator &I);
268 void handleSpecialFP(MachineBasicBlock::iterator &I);
270 // Check if a COPY instruction is using FP registers.
271 static bool isFPCopy(MachineInstr *MI) {
272 unsigned DstReg = MI->getOperand(0).getReg();
273 unsigned SrcReg = MI->getOperand(1).getReg();
275 return X86::RFP80RegClass.contains(DstReg) ||
276 X86::RFP80RegClass.contains(SrcReg);
279 void setKillFlags(MachineBasicBlock &MBB) const;
284 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
286 /// getFPReg - Return the X86::FPx register number for the specified operand.
287 /// For example, this returns 3 for X86::FP3.
288 static unsigned getFPReg(const MachineOperand &MO) {
289 assert(MO.isReg() && "Expected an FP register!");
290 unsigned Reg = MO.getReg();
291 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
292 return Reg - X86::FP0;
295 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
296 /// register references into FP stack references.
298 bool FPS::runOnMachineFunction(MachineFunction &MF) {
299 // We only need to run this pass if there are any FP registers used in this
300 // function. If it is all integer, there is nothing for us to do!
301 bool FPIsUsed = false;
303 static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!");
304 const MachineRegisterInfo &MRI = MF.getRegInfo();
305 for (unsigned i = 0; i <= 6; ++i)
306 if (!MRI.reg_nodbg_empty(X86::FP0 + i)) {
312 if (!FPIsUsed) return false;
314 Bundles = &getAnalysis<EdgeBundles>();
315 TII = MF.getSubtarget().getInstrInfo();
317 // Prepare cross-MBB liveness.
322 // Process the function in depth first order so that we process at least one
323 // of the predecessors for every reachable block in the function.
324 SmallPtrSet<MachineBasicBlock*, 8> Processed;
325 MachineBasicBlock *Entry = MF.begin();
327 bool Changed = false;
328 for (MachineBasicBlock *BB : depth_first_ext(Entry, Processed))
329 Changed |= processBasicBlock(MF, *BB);
331 // Process any unreachable blocks in arbitrary order now.
332 if (MF.size() != Processed.size())
333 for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
334 if (Processed.insert(BB).second)
335 Changed |= processBasicBlock(MF, *BB);
342 /// bundleCFG - Scan all the basic blocks to determine consistent live-in and
343 /// live-out sets for the FP registers. Consistent means that the set of
344 /// registers live-out from a block is identical to the live-in set of all
345 /// successors. This is not enforced by the normal live-in lists since
346 /// registers may be implicitly defined, or not used by all successors.
347 void FPS::bundleCFG(MachineFunction &MF) {
348 assert(LiveBundles.empty() && "Stale data in LiveBundles");
349 LiveBundles.resize(Bundles->getNumBundles());
351 // Gather the actual live-in masks for all MBBs.
352 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
353 MachineBasicBlock *MBB = I;
354 const unsigned Mask = calcLiveInMask(MBB);
357 // Update MBB ingoing bundle mask.
358 LiveBundles[Bundles->getBundle(MBB->getNumber(), false)].Mask |= Mask;
362 /// processBasicBlock - Loop over all of the instructions in the basic block,
363 /// transforming FP instructions into their stack form.
365 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
366 bool Changed = false;
372 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
373 MachineInstr *MI = I;
374 uint64_t Flags = MI->getDesc().TSFlags;
376 unsigned FPInstClass = Flags & X86II::FPTypeMask;
377 if (MI->isInlineAsm())
378 FPInstClass = X86II::SpecialFP;
380 if (MI->isCopy() && isFPCopy(MI))
381 FPInstClass = X86II::SpecialFP;
383 if (MI->isImplicitDef() &&
384 X86::RFP80RegClass.contains(MI->getOperand(0).getReg()))
385 FPInstClass = X86II::SpecialFP;
388 FPInstClass = X86II::SpecialFP;
390 if (FPInstClass == X86II::NotFP)
391 continue; // Efficiently ignore non-fp insts!
393 MachineInstr *PrevMI = nullptr;
395 PrevMI = std::prev(I);
397 ++NumFP; // Keep track of # of pseudo instrs
398 DEBUG(dbgs() << "\nFPInst:\t" << *MI);
400 // Get dead variables list now because the MI pointer may be deleted as part
402 SmallVector<unsigned, 8> DeadRegs;
403 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
404 const MachineOperand &MO = MI->getOperand(i);
405 if (MO.isReg() && MO.isDead())
406 DeadRegs.push_back(MO.getReg());
409 switch (FPInstClass) {
410 case X86II::ZeroArgFP: handleZeroArgFP(I); break;
411 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
412 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
413 case X86II::TwoArgFP: handleTwoArgFP(I); break;
414 case X86II::CompareFP: handleCompareFP(I); break;
415 case X86II::CondMovFP: handleCondMovFP(I); break;
416 case X86II::SpecialFP: handleSpecialFP(I); break;
417 default: llvm_unreachable("Unknown FP Type!");
420 // Check to see if any of the values defined by this instruction are dead
421 // after definition. If so, pop them.
422 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
423 unsigned Reg = DeadRegs[i];
424 // Check if Reg is live on the stack. An inline-asm register operand that
425 // is in the clobber list and marked dead might not be live on the stack.
426 if (Reg >= X86::FP0 && Reg <= X86::FP6 && isLive(Reg-X86::FP0)) {
427 DEBUG(dbgs() << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
428 freeStackSlotAfter(I, Reg-X86::FP0);
432 // Print out all of the instructions expanded to if -debug
434 MachineBasicBlock::iterator PrevI(PrevMI);
436 dbgs() << "Just deleted pseudo instruction\n";
438 MachineBasicBlock::iterator Start = I;
439 // Rewind to first instruction newly inserted.
440 while (Start != BB.begin() && std::prev(Start) != PrevI) --Start;
441 dbgs() << "Inserted instructions:\n\t";
442 Start->print(dbgs());
443 while (++Start != std::next(I)) {}
457 /// setupBlockStack - Use the live bundles to set up our model of the stack
458 /// to match predecessors' live out stack.
459 void FPS::setupBlockStack() {
460 DEBUG(dbgs() << "\nSetting up live-ins for BB#" << MBB->getNumber()
461 << " derived from " << MBB->getName() << ".\n");
463 // Get the live-in bundle for MBB.
464 const LiveBundle &Bundle =
465 LiveBundles[Bundles->getBundle(MBB->getNumber(), false)];
468 DEBUG(dbgs() << "Block has no FP live-ins.\n");
472 // Depth-first iteration should ensure that we always have an assigned stack.
473 assert(Bundle.isFixed() && "Reached block before any predecessors");
475 // Push the fixed live-in registers.
476 for (unsigned i = Bundle.FixCount; i > 0; --i) {
477 MBB->addLiveIn(X86::ST0+i-1);
478 DEBUG(dbgs() << "Live-in st(" << (i-1) << "): %FP"
479 << unsigned(Bundle.FixStack[i-1]) << '\n');
480 pushReg(Bundle.FixStack[i-1]);
483 // Kill off unwanted live-ins. This can happen with a critical edge.
484 // FIXME: We could keep these live registers around as zombies. They may need
485 // to be revived at the end of a short block. It might save a few instrs.
486 adjustLiveRegs(calcLiveInMask(MBB), MBB->begin());
490 /// finishBlockStack - Revive live-outs that are implicitly defined out of
491 /// MBB. Shuffle live registers to match the expected fixed stack of any
492 /// predecessors, and ensure that all predecessors are expecting the same
494 void FPS::finishBlockStack() {
495 // The RET handling below takes care of return blocks for us.
496 if (MBB->succ_empty())
499 DEBUG(dbgs() << "Setting up live-outs for BB#" << MBB->getNumber()
500 << " derived from " << MBB->getName() << ".\n");
502 // Get MBB's live-out bundle.
503 unsigned BundleIdx = Bundles->getBundle(MBB->getNumber(), true);
504 LiveBundle &Bundle = LiveBundles[BundleIdx];
506 // We may need to kill and define some registers to match successors.
507 // FIXME: This can probably be combined with the shuffle below.
508 MachineBasicBlock::iterator Term = MBB->getFirstTerminator();
509 adjustLiveRegs(Bundle.Mask, Term);
512 DEBUG(dbgs() << "No live-outs.\n");
516 // Has the stack order been fixed yet?
517 DEBUG(dbgs() << "LB#" << BundleIdx << ": ");
518 if (Bundle.isFixed()) {
519 DEBUG(dbgs() << "Shuffling stack to match.\n");
520 shuffleStackTop(Bundle.FixStack, Bundle.FixCount, Term);
522 // Not fixed yet, we get to choose.
523 DEBUG(dbgs() << "Fixing stack order now.\n");
524 Bundle.FixCount = StackTop;
525 for (unsigned i = 0; i < StackTop; ++i)
526 Bundle.FixStack[i] = getStackEntry(i);
531 //===----------------------------------------------------------------------===//
532 // Efficient Lookup Table Support
533 //===----------------------------------------------------------------------===//
539 bool operator<(const TableEntry &TE) const { return from < TE.from; }
540 friend bool operator<(const TableEntry &TE, unsigned V) {
543 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned V,
544 const TableEntry &TE) {
551 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
552 for (unsigned i = 0; i != NumEntries-1; ++i)
553 if (!(Table[i] < Table[i+1])) return false;
558 static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
559 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
560 if (I != Table+N && I->from == Opcode)
566 #define ASSERT_SORTED(TABLE)
568 #define ASSERT_SORTED(TABLE) \
569 { static bool TABLE##Checked = false; \
570 if (!TABLE##Checked) { \
571 assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \
572 "All lookup tables must be sorted for efficient access!"); \
573 TABLE##Checked = true; \
578 //===----------------------------------------------------------------------===//
579 // Register File -> Register Stack Mapping Methods
580 //===----------------------------------------------------------------------===//
582 // OpcodeTable - Sorted map of register instructions to their stack version.
583 // The first element is an register file pseudo instruction, the second is the
584 // concrete X86 instruction which uses the register stack.
586 static const TableEntry OpcodeTable[] = {
587 { X86::ABS_Fp32 , X86::ABS_F },
588 { X86::ABS_Fp64 , X86::ABS_F },
589 { X86::ABS_Fp80 , X86::ABS_F },
590 { X86::ADD_Fp32m , X86::ADD_F32m },
591 { X86::ADD_Fp64m , X86::ADD_F64m },
592 { X86::ADD_Fp64m32 , X86::ADD_F32m },
593 { X86::ADD_Fp80m32 , X86::ADD_F32m },
594 { X86::ADD_Fp80m64 , X86::ADD_F64m },
595 { X86::ADD_FpI16m32 , X86::ADD_FI16m },
596 { X86::ADD_FpI16m64 , X86::ADD_FI16m },
597 { X86::ADD_FpI16m80 , X86::ADD_FI16m },
598 { X86::ADD_FpI32m32 , X86::ADD_FI32m },
599 { X86::ADD_FpI32m64 , X86::ADD_FI32m },
600 { X86::ADD_FpI32m80 , X86::ADD_FI32m },
601 { X86::CHS_Fp32 , X86::CHS_F },
602 { X86::CHS_Fp64 , X86::CHS_F },
603 { X86::CHS_Fp80 , X86::CHS_F },
604 { X86::CMOVBE_Fp32 , X86::CMOVBE_F },
605 { X86::CMOVBE_Fp64 , X86::CMOVBE_F },
606 { X86::CMOVBE_Fp80 , X86::CMOVBE_F },
607 { X86::CMOVB_Fp32 , X86::CMOVB_F },
608 { X86::CMOVB_Fp64 , X86::CMOVB_F },
609 { X86::CMOVB_Fp80 , X86::CMOVB_F },
610 { X86::CMOVE_Fp32 , X86::CMOVE_F },
611 { X86::CMOVE_Fp64 , X86::CMOVE_F },
612 { X86::CMOVE_Fp80 , X86::CMOVE_F },
613 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
614 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
615 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
616 { X86::CMOVNB_Fp32 , X86::CMOVNB_F },
617 { X86::CMOVNB_Fp64 , X86::CMOVNB_F },
618 { X86::CMOVNB_Fp80 , X86::CMOVNB_F },
619 { X86::CMOVNE_Fp32 , X86::CMOVNE_F },
620 { X86::CMOVNE_Fp64 , X86::CMOVNE_F },
621 { X86::CMOVNE_Fp80 , X86::CMOVNE_F },
622 { X86::CMOVNP_Fp32 , X86::CMOVNP_F },
623 { X86::CMOVNP_Fp64 , X86::CMOVNP_F },
624 { X86::CMOVNP_Fp80 , X86::CMOVNP_F },
625 { X86::CMOVP_Fp32 , X86::CMOVP_F },
626 { X86::CMOVP_Fp64 , X86::CMOVP_F },
627 { X86::CMOVP_Fp80 , X86::CMOVP_F },
628 { X86::COS_Fp32 , X86::COS_F },
629 { X86::COS_Fp64 , X86::COS_F },
630 { X86::COS_Fp80 , X86::COS_F },
631 { X86::DIVR_Fp32m , X86::DIVR_F32m },
632 { X86::DIVR_Fp64m , X86::DIVR_F64m },
633 { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
634 { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
635 { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
636 { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
637 { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
638 { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
639 { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
640 { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
641 { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
642 { X86::DIV_Fp32m , X86::DIV_F32m },
643 { X86::DIV_Fp64m , X86::DIV_F64m },
644 { X86::DIV_Fp64m32 , X86::DIV_F32m },
645 { X86::DIV_Fp80m32 , X86::DIV_F32m },
646 { X86::DIV_Fp80m64 , X86::DIV_F64m },
647 { X86::DIV_FpI16m32 , X86::DIV_FI16m },
648 { X86::DIV_FpI16m64 , X86::DIV_FI16m },
649 { X86::DIV_FpI16m80 , X86::DIV_FI16m },
650 { X86::DIV_FpI32m32 , X86::DIV_FI32m },
651 { X86::DIV_FpI32m64 , X86::DIV_FI32m },
652 { X86::DIV_FpI32m80 , X86::DIV_FI32m },
653 { X86::ILD_Fp16m32 , X86::ILD_F16m },
654 { X86::ILD_Fp16m64 , X86::ILD_F16m },
655 { X86::ILD_Fp16m80 , X86::ILD_F16m },
656 { X86::ILD_Fp32m32 , X86::ILD_F32m },
657 { X86::ILD_Fp32m64 , X86::ILD_F32m },
658 { X86::ILD_Fp32m80 , X86::ILD_F32m },
659 { X86::ILD_Fp64m32 , X86::ILD_F64m },
660 { X86::ILD_Fp64m64 , X86::ILD_F64m },
661 { X86::ILD_Fp64m80 , X86::ILD_F64m },
662 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
663 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
664 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
665 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
666 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
667 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
668 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
669 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
670 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
671 { X86::IST_Fp16m32 , X86::IST_F16m },
672 { X86::IST_Fp16m64 , X86::IST_F16m },
673 { X86::IST_Fp16m80 , X86::IST_F16m },
674 { X86::IST_Fp32m32 , X86::IST_F32m },
675 { X86::IST_Fp32m64 , X86::IST_F32m },
676 { X86::IST_Fp32m80 , X86::IST_F32m },
677 { X86::IST_Fp64m32 , X86::IST_FP64m },
678 { X86::IST_Fp64m64 , X86::IST_FP64m },
679 { X86::IST_Fp64m80 , X86::IST_FP64m },
680 { X86::LD_Fp032 , X86::LD_F0 },
681 { X86::LD_Fp064 , X86::LD_F0 },
682 { X86::LD_Fp080 , X86::LD_F0 },
683 { X86::LD_Fp132 , X86::LD_F1 },
684 { X86::LD_Fp164 , X86::LD_F1 },
685 { X86::LD_Fp180 , X86::LD_F1 },
686 { X86::LD_Fp32m , X86::LD_F32m },
687 { X86::LD_Fp32m64 , X86::LD_F32m },
688 { X86::LD_Fp32m80 , X86::LD_F32m },
689 { X86::LD_Fp64m , X86::LD_F64m },
690 { X86::LD_Fp64m80 , X86::LD_F64m },
691 { X86::LD_Fp80m , X86::LD_F80m },
692 { X86::MUL_Fp32m , X86::MUL_F32m },
693 { X86::MUL_Fp64m , X86::MUL_F64m },
694 { X86::MUL_Fp64m32 , X86::MUL_F32m },
695 { X86::MUL_Fp80m32 , X86::MUL_F32m },
696 { X86::MUL_Fp80m64 , X86::MUL_F64m },
697 { X86::MUL_FpI16m32 , X86::MUL_FI16m },
698 { X86::MUL_FpI16m64 , X86::MUL_FI16m },
699 { X86::MUL_FpI16m80 , X86::MUL_FI16m },
700 { X86::MUL_FpI32m32 , X86::MUL_FI32m },
701 { X86::MUL_FpI32m64 , X86::MUL_FI32m },
702 { X86::MUL_FpI32m80 , X86::MUL_FI32m },
703 { X86::SIN_Fp32 , X86::SIN_F },
704 { X86::SIN_Fp64 , X86::SIN_F },
705 { X86::SIN_Fp80 , X86::SIN_F },
706 { X86::SQRT_Fp32 , X86::SQRT_F },
707 { X86::SQRT_Fp64 , X86::SQRT_F },
708 { X86::SQRT_Fp80 , X86::SQRT_F },
709 { X86::ST_Fp32m , X86::ST_F32m },
710 { X86::ST_Fp64m , X86::ST_F64m },
711 { X86::ST_Fp64m32 , X86::ST_F32m },
712 { X86::ST_Fp80m32 , X86::ST_F32m },
713 { X86::ST_Fp80m64 , X86::ST_F64m },
714 { X86::ST_FpP80m , X86::ST_FP80m },
715 { X86::SUBR_Fp32m , X86::SUBR_F32m },
716 { X86::SUBR_Fp64m , X86::SUBR_F64m },
717 { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
718 { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
719 { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
720 { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
721 { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
722 { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
723 { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
724 { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
725 { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
726 { X86::SUB_Fp32m , X86::SUB_F32m },
727 { X86::SUB_Fp64m , X86::SUB_F64m },
728 { X86::SUB_Fp64m32 , X86::SUB_F32m },
729 { X86::SUB_Fp80m32 , X86::SUB_F32m },
730 { X86::SUB_Fp80m64 , X86::SUB_F64m },
731 { X86::SUB_FpI16m32 , X86::SUB_FI16m },
732 { X86::SUB_FpI16m64 , X86::SUB_FI16m },
733 { X86::SUB_FpI16m80 , X86::SUB_FI16m },
734 { X86::SUB_FpI32m32 , X86::SUB_FI32m },
735 { X86::SUB_FpI32m64 , X86::SUB_FI32m },
736 { X86::SUB_FpI32m80 , X86::SUB_FI32m },
737 { X86::TST_Fp32 , X86::TST_F },
738 { X86::TST_Fp64 , X86::TST_F },
739 { X86::TST_Fp80 , X86::TST_F },
740 { X86::UCOM_FpIr32 , X86::UCOM_FIr },
741 { X86::UCOM_FpIr64 , X86::UCOM_FIr },
742 { X86::UCOM_FpIr80 , X86::UCOM_FIr },
743 { X86::UCOM_Fpr32 , X86::UCOM_Fr },
744 { X86::UCOM_Fpr64 , X86::UCOM_Fr },
745 { X86::UCOM_Fpr80 , X86::UCOM_Fr },
748 static unsigned getConcreteOpcode(unsigned Opcode) {
749 ASSERT_SORTED(OpcodeTable);
750 int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode);
751 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
755 //===----------------------------------------------------------------------===//
757 //===----------------------------------------------------------------------===//
759 // PopTable - Sorted map of instructions to their popping version. The first
760 // element is an instruction, the second is the version which pops.
762 static const TableEntry PopTable[] = {
763 { X86::ADD_FrST0 , X86::ADD_FPrST0 },
765 { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
766 { X86::DIV_FrST0 , X86::DIV_FPrST0 },
768 { X86::IST_F16m , X86::IST_FP16m },
769 { X86::IST_F32m , X86::IST_FP32m },
771 { X86::MUL_FrST0 , X86::MUL_FPrST0 },
773 { X86::ST_F32m , X86::ST_FP32m },
774 { X86::ST_F64m , X86::ST_FP64m },
775 { X86::ST_Frr , X86::ST_FPrr },
777 { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
778 { X86::SUB_FrST0 , X86::SUB_FPrST0 },
780 { X86::UCOM_FIr , X86::UCOM_FIPr },
782 { X86::UCOM_FPr , X86::UCOM_FPPr },
783 { X86::UCOM_Fr , X86::UCOM_FPr },
786 /// popStackAfter - Pop the current value off of the top of the FP stack after
787 /// the specified instruction. This attempts to be sneaky and combine the pop
788 /// into the instruction itself if possible. The iterator is left pointing to
789 /// the last instruction, be it a new pop instruction inserted, or the old
790 /// instruction if it was modified in place.
792 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
793 MachineInstr* MI = I;
794 DebugLoc dl = MI->getDebugLoc();
795 ASSERT_SORTED(PopTable);
797 report_fatal_error("Cannot pop empty stack!");
798 RegMap[Stack[--StackTop]] = ~0; // Update state
800 // Check to see if there is a popping version of this instruction...
801 int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode());
803 I->setDesc(TII->get(Opcode));
804 if (Opcode == X86::UCOM_FPPr)
806 } else { // Insert an explicit pop
807 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
811 /// freeStackSlotAfter - Free the specified register from the register stack, so
812 /// that it is no longer in a register. If the register is currently at the top
813 /// of the stack, we just pop the current instruction, otherwise we store the
814 /// current top-of-stack into the specified slot, then pop the top of stack.
815 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
816 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
821 // Otherwise, store the top of stack into the dead slot, killing the operand
822 // without having to add in an explicit xchg then pop.
824 I = freeStackSlotBefore(++I, FPRegNo);
827 /// freeStackSlotBefore - Free the specified register without trying any
829 MachineBasicBlock::iterator
830 FPS::freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo) {
831 unsigned STReg = getSTReg(FPRegNo);
832 unsigned OldSlot = getSlot(FPRegNo);
833 unsigned TopReg = Stack[StackTop-1];
834 Stack[OldSlot] = TopReg;
835 RegMap[TopReg] = OldSlot;
836 RegMap[FPRegNo] = ~0;
837 Stack[--StackTop] = ~0;
838 return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr))
843 /// adjustLiveRegs - Kill and revive registers such that exactly the FP
844 /// registers with a bit in Mask are live.
845 void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) {
846 unsigned Defs = Mask;
848 for (unsigned i = 0; i < StackTop; ++i) {
849 unsigned RegNo = Stack[i];
850 if (!(Defs & (1 << RegNo)))
851 // This register is live, but we don't want it.
852 Kills |= (1 << RegNo);
854 // We don't need to imp-def this live register.
855 Defs &= ~(1 << RegNo);
857 assert((Kills & Defs) == 0 && "Register needs killing and def'ing?");
859 // Produce implicit-defs for free by using killed registers.
860 while (Kills && Defs) {
861 unsigned KReg = countTrailingZeros(Kills);
862 unsigned DReg = countTrailingZeros(Defs);
863 DEBUG(dbgs() << "Renaming %FP" << KReg << " as imp %FP" << DReg << "\n");
864 std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]);
865 std::swap(RegMap[KReg], RegMap[DReg]);
866 Kills &= ~(1 << KReg);
867 Defs &= ~(1 << DReg);
870 // Kill registers by popping.
871 if (Kills && I != MBB->begin()) {
872 MachineBasicBlock::iterator I2 = std::prev(I);
874 unsigned KReg = getStackEntry(0);
875 if (!(Kills & (1 << KReg)))
877 DEBUG(dbgs() << "Popping %FP" << KReg << "\n");
879 Kills &= ~(1 << KReg);
883 // Manually kill the rest.
885 unsigned KReg = countTrailingZeros(Kills);
886 DEBUG(dbgs() << "Killing %FP" << KReg << "\n");
887 freeStackSlotBefore(I, KReg);
888 Kills &= ~(1 << KReg);
891 // Load zeros for all the imp-defs.
893 unsigned DReg = countTrailingZeros(Defs);
894 DEBUG(dbgs() << "Defining %FP" << DReg << " as 0\n");
895 BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0));
897 Defs &= ~(1 << DReg);
900 // Now we should have the correct registers live.
902 assert(StackTop == countPopulation(Mask) && "Live count mismatch");
905 /// shuffleStackTop - emit fxch instructions before I to shuffle the top
906 /// FixCount entries into the order given by FixStack.
907 /// FIXME: Is there a better algorithm than insertion sort?
908 void FPS::shuffleStackTop(const unsigned char *FixStack,
910 MachineBasicBlock::iterator I) {
911 // Move items into place, starting from the desired stack bottom.
913 // Old register at position FixCount.
914 unsigned OldReg = getStackEntry(FixCount);
915 // Desired register at position FixCount.
916 unsigned Reg = FixStack[FixCount];
919 // (Reg st0) (OldReg st0) = (Reg OldReg st0)
922 moveToTop(OldReg, I);
928 //===----------------------------------------------------------------------===//
929 // Instruction transformation implementation
930 //===----------------------------------------------------------------------===//
932 void FPS::handleCall(MachineBasicBlock::iterator &I) {
933 unsigned STReturns = 0;
935 for (const auto &MO : I->operands()) {
939 unsigned R = MO.getReg() - X86::FP0;
942 assert(MO.isDef() && MO.isImplicit());
947 unsigned N = countTrailingOnes(STReturns);
949 // FP registers used for function return must be consecutive starting at
951 assert(STReturns == 0 || (isMask_32(STReturns) && N <= 2));
953 for (unsigned I = 0; I < N; ++I)
957 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
959 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
960 MachineInstr *MI = I;
961 unsigned DestReg = getFPReg(MI->getOperand(0));
963 // Change from the pseudo instruction to the concrete instruction.
964 MI->RemoveOperand(0); // Remove the explicit ST(0) operand
965 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
967 // Result gets pushed on the stack.
971 /// handleOneArgFP - fst <mem>, ST(0)
973 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
974 MachineInstr *MI = I;
975 unsigned NumOps = MI->getDesc().getNumOperands();
976 assert((NumOps == X86::AddrNumOperands + 1 || NumOps == 1) &&
977 "Can only handle fst* & ftst instructions!");
979 // Is this the last use of the source register?
980 unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
981 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
983 // FISTP64m is strange because there isn't a non-popping versions.
984 // If we have one _and_ we don't want to pop the operand, duplicate the value
985 // on the stack instead of moving it. This ensure that popping the value is
987 // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
990 (MI->getOpcode() == X86::IST_Fp64m32 ||
991 MI->getOpcode() == X86::ISTT_Fp16m32 ||
992 MI->getOpcode() == X86::ISTT_Fp32m32 ||
993 MI->getOpcode() == X86::ISTT_Fp64m32 ||
994 MI->getOpcode() == X86::IST_Fp64m64 ||
995 MI->getOpcode() == X86::ISTT_Fp16m64 ||
996 MI->getOpcode() == X86::ISTT_Fp32m64 ||
997 MI->getOpcode() == X86::ISTT_Fp64m64 ||
998 MI->getOpcode() == X86::IST_Fp64m80 ||
999 MI->getOpcode() == X86::ISTT_Fp16m80 ||
1000 MI->getOpcode() == X86::ISTT_Fp32m80 ||
1001 MI->getOpcode() == X86::ISTT_Fp64m80 ||
1002 MI->getOpcode() == X86::ST_FpP80m)) {
1003 duplicateToTop(Reg, ScratchFPReg, I);
1005 moveToTop(Reg, I); // Move to the top of the stack...
1008 // Convert from the pseudo instruction to the concrete instruction.
1009 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand
1010 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1012 if (MI->getOpcode() == X86::IST_FP64m ||
1013 MI->getOpcode() == X86::ISTT_FP16m ||
1014 MI->getOpcode() == X86::ISTT_FP32m ||
1015 MI->getOpcode() == X86::ISTT_FP64m ||
1016 MI->getOpcode() == X86::ST_FP80m) {
1018 report_fatal_error("Stack empty??");
1020 } else if (KillsSrc) { // Last use of operand?
1026 /// handleOneArgFPRW: Handle instructions that read from the top of stack and
1027 /// replace the value with a newly computed value. These instructions may have
1028 /// non-fp operands after their FP operands.
1032 /// R1 = fadd R2, [mem]
1034 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
1035 MachineInstr *MI = I;
1037 unsigned NumOps = MI->getDesc().getNumOperands();
1038 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
1041 // Is this the last use of the source register?
1042 unsigned Reg = getFPReg(MI->getOperand(1));
1043 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
1046 // If this is the last use of the source register, just make sure it's on
1047 // the top of the stack.
1050 report_fatal_error("Stack cannot be empty!");
1052 pushReg(getFPReg(MI->getOperand(0)));
1054 // If this is not the last use of the source register, _copy_ it to the top
1056 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
1059 // Change from the pseudo instruction to the concrete instruction.
1060 MI->RemoveOperand(1); // Drop the source operand.
1061 MI->RemoveOperand(0); // Drop the destination operand.
1062 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1066 //===----------------------------------------------------------------------===//
1067 // Define tables of various ways to map pseudo instructions
1070 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
1071 static const TableEntry ForwardST0Table[] = {
1072 { X86::ADD_Fp32 , X86::ADD_FST0r },
1073 { X86::ADD_Fp64 , X86::ADD_FST0r },
1074 { X86::ADD_Fp80 , X86::ADD_FST0r },
1075 { X86::DIV_Fp32 , X86::DIV_FST0r },
1076 { X86::DIV_Fp64 , X86::DIV_FST0r },
1077 { X86::DIV_Fp80 , X86::DIV_FST0r },
1078 { X86::MUL_Fp32 , X86::MUL_FST0r },
1079 { X86::MUL_Fp64 , X86::MUL_FST0r },
1080 { X86::MUL_Fp80 , X86::MUL_FST0r },
1081 { X86::SUB_Fp32 , X86::SUB_FST0r },
1082 { X86::SUB_Fp64 , X86::SUB_FST0r },
1083 { X86::SUB_Fp80 , X86::SUB_FST0r },
1086 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
1087 static const TableEntry ReverseST0Table[] = {
1088 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative
1089 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative
1090 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative
1091 { X86::DIV_Fp32 , X86::DIVR_FST0r },
1092 { X86::DIV_Fp64 , X86::DIVR_FST0r },
1093 { X86::DIV_Fp80 , X86::DIVR_FST0r },
1094 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative
1095 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative
1096 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative
1097 { X86::SUB_Fp32 , X86::SUBR_FST0r },
1098 { X86::SUB_Fp64 , X86::SUBR_FST0r },
1099 { X86::SUB_Fp80 , X86::SUBR_FST0r },
1102 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
1103 static const TableEntry ForwardSTiTable[] = {
1104 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative
1105 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative
1106 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative
1107 { X86::DIV_Fp32 , X86::DIVR_FrST0 },
1108 { X86::DIV_Fp64 , X86::DIVR_FrST0 },
1109 { X86::DIV_Fp80 , X86::DIVR_FrST0 },
1110 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative
1111 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative
1112 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative
1113 { X86::SUB_Fp32 , X86::SUBR_FrST0 },
1114 { X86::SUB_Fp64 , X86::SUBR_FrST0 },
1115 { X86::SUB_Fp80 , X86::SUBR_FrST0 },
1118 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
1119 static const TableEntry ReverseSTiTable[] = {
1120 { X86::ADD_Fp32 , X86::ADD_FrST0 },
1121 { X86::ADD_Fp64 , X86::ADD_FrST0 },
1122 { X86::ADD_Fp80 , X86::ADD_FrST0 },
1123 { X86::DIV_Fp32 , X86::DIV_FrST0 },
1124 { X86::DIV_Fp64 , X86::DIV_FrST0 },
1125 { X86::DIV_Fp80 , X86::DIV_FrST0 },
1126 { X86::MUL_Fp32 , X86::MUL_FrST0 },
1127 { X86::MUL_Fp64 , X86::MUL_FrST0 },
1128 { X86::MUL_Fp80 , X86::MUL_FrST0 },
1129 { X86::SUB_Fp32 , X86::SUB_FrST0 },
1130 { X86::SUB_Fp64 , X86::SUB_FrST0 },
1131 { X86::SUB_Fp80 , X86::SUB_FrST0 },
1135 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
1136 /// instructions which need to be simplified and possibly transformed.
1138 /// Result: ST(0) = fsub ST(0), ST(i)
1139 /// ST(i) = fsub ST(0), ST(i)
1140 /// ST(0) = fsubr ST(0), ST(i)
1141 /// ST(i) = fsubr ST(0), ST(i)
1143 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
1144 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
1145 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
1146 MachineInstr *MI = I;
1148 unsigned NumOperands = MI->getDesc().getNumOperands();
1149 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
1150 unsigned Dest = getFPReg(MI->getOperand(0));
1151 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
1152 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
1153 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
1154 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1155 DebugLoc dl = MI->getDebugLoc();
1157 unsigned TOS = getStackEntry(0);
1159 // One of our operands must be on the top of the stack. If neither is yet, we
1160 // need to move one.
1161 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
1162 // We can choose to move either operand to the top of the stack. If one of
1163 // the operands is killed by this instruction, we want that one so that we
1164 // can update right on top of the old version.
1166 moveToTop(Op0, I); // Move dead operand to TOS.
1168 } else if (KillsOp1) {
1172 // All of the operands are live after this instruction executes, so we
1173 // cannot update on top of any operand. Because of this, we must
1174 // duplicate one of the stack elements to the top. It doesn't matter
1175 // which one we pick.
1177 duplicateToTop(Op0, Dest, I);
1181 } else if (!KillsOp0 && !KillsOp1) {
1182 // If we DO have one of our operands at the top of the stack, but we don't
1183 // have a dead operand, we must duplicate one of the operands to a new slot
1185 duplicateToTop(Op0, Dest, I);
1190 // Now we know that one of our operands is on the top of the stack, and at
1191 // least one of our operands is killed by this instruction.
1192 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
1193 "Stack conditions not set up right!");
1195 // We decide which form to use based on what is on the top of the stack, and
1196 // which operand is killed by this instruction.
1197 const TableEntry *InstTable;
1198 bool isForward = TOS == Op0;
1199 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
1202 InstTable = ForwardST0Table;
1204 InstTable = ReverseST0Table;
1207 InstTable = ForwardSTiTable;
1209 InstTable = ReverseSTiTable;
1212 int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table),
1214 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
1216 // NotTOS - The register which is not on the top of stack...
1217 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
1219 // Replace the old instruction with a new instruction
1221 I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
1223 // If both operands are killed, pop one off of the stack in addition to
1224 // overwriting the other one.
1225 if (KillsOp0 && KillsOp1 && Op0 != Op1) {
1226 assert(!updateST0 && "Should have updated other operand!");
1227 popStackAfter(I); // Pop the top of stack
1230 // Update stack information so that we know the destination register is now on
1232 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
1233 assert(UpdatedSlot < StackTop && Dest < 7);
1234 Stack[UpdatedSlot] = Dest;
1235 RegMap[Dest] = UpdatedSlot;
1236 MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction
1239 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
1240 /// register arguments and no explicit destinations.
1242 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
1243 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
1244 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
1245 MachineInstr *MI = I;
1247 unsigned NumOperands = MI->getDesc().getNumOperands();
1248 assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
1249 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
1250 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
1251 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
1252 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1254 // Make sure the first operand is on the top of stack, the other one can be
1258 // Change from the pseudo instruction to the concrete instruction.
1259 MI->getOperand(0).setReg(getSTReg(Op1));
1260 MI->RemoveOperand(1);
1261 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1263 // If any of the operands are killed by this instruction, free them.
1264 if (KillsOp0) freeStackSlotAfter(I, Op0);
1265 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
1268 /// handleCondMovFP - Handle two address conditional move instructions. These
1269 /// instructions move a st(i) register to st(0) iff a condition is true. These
1270 /// instructions require that the first operand is at the top of the stack, but
1271 /// otherwise don't modify the stack at all.
1272 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
1273 MachineInstr *MI = I;
1275 unsigned Op0 = getFPReg(MI->getOperand(0));
1276 unsigned Op1 = getFPReg(MI->getOperand(2));
1277 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1279 // The first operand *must* be on the top of the stack.
1282 // Change the second operand to the stack register that the operand is in.
1283 // Change from the pseudo instruction to the concrete instruction.
1284 MI->RemoveOperand(0);
1285 MI->RemoveOperand(1);
1286 MI->getOperand(0).setReg(getSTReg(Op1));
1287 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1289 // If we kill the second operand, make sure to pop it from the stack.
1290 if (Op0 != Op1 && KillsOp1) {
1291 // Get this value off of the register stack.
1292 freeStackSlotAfter(I, Op1);
1297 /// handleSpecialFP - Handle special instructions which behave unlike other
1298 /// floating point instructions. This is primarily intended for use by pseudo
1301 void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) {
1302 MachineInstr *MI = Inst;
1309 switch (MI->getOpcode()) {
1310 default: llvm_unreachable("Unknown SpecialFP instruction!");
1311 case TargetOpcode::COPY: {
1312 // We handle three kinds of copies: FP <- FP, FP <- ST, and ST <- FP.
1313 const MachineOperand &MO1 = MI->getOperand(1);
1314 const MachineOperand &MO0 = MI->getOperand(0);
1315 bool KillsSrc = MI->killsRegister(MO1.getReg());
1318 unsigned DstFP = getFPReg(MO0);
1319 unsigned SrcFP = getFPReg(MO1);
1320 assert(isLive(SrcFP) && "Cannot copy dead register");
1322 // If the input operand is killed, we can just change the owner of the
1323 // incoming stack slot into the result.
1324 unsigned Slot = getSlot(SrcFP);
1325 Stack[Slot] = DstFP;
1326 RegMap[DstFP] = Slot;
1328 // For COPY we just duplicate the specified value to a new stack slot.
1329 // This could be made better, but would require substantial changes.
1330 duplicateToTop(SrcFP, DstFP, Inst);
1335 case TargetOpcode::IMPLICIT_DEF: {
1336 // All FP registers must be explicitly defined, so load a 0 instead.
1337 unsigned Reg = MI->getOperand(0).getReg() - X86::FP0;
1338 DEBUG(dbgs() << "Emitting LD_F0 for implicit FP" << Reg << '\n');
1339 BuildMI(*MBB, Inst, MI->getDebugLoc(), TII->get(X86::LD_F0));
1344 case TargetOpcode::INLINEASM: {
1345 // The inline asm MachineInstr currently only *uses* FP registers for the
1346 // 'f' constraint. These should be turned into the current ST(x) register
1347 // in the machine instr.
1349 // There are special rules for x87 inline assembly. The compiler must know
1350 // exactly how many registers are popped and pushed implicitly by the asm.
1351 // Otherwise it is not possible to restore the stack state after the inline
1354 // There are 3 kinds of input operands:
1356 // 1. Popped inputs. These must appear at the stack top in ST0-STn. A
1357 // popped input operand must be in a fixed stack slot, and it is either
1358 // tied to an output operand, or in the clobber list. The MI has ST use
1359 // and def operands for these inputs.
1361 // 2. Fixed inputs. These inputs appear in fixed stack slots, but are
1362 // preserved by the inline asm. The fixed stack slots must be STn-STm
1363 // following the popped inputs. A fixed input operand cannot be tied to
1364 // an output or appear in the clobber list. The MI has ST use operands
1365 // and no defs for these inputs.
1367 // 3. Preserved inputs. These inputs use the "f" constraint which is
1368 // represented as an FP register. The inline asm won't change these
1371 // Outputs must be in ST registers, FP outputs are not allowed. Clobbered
1372 // registers do not count as output operands. The inline asm changes the
1373 // stack as if it popped all the popped inputs and then pushed all the
1376 // Scan the assembly for ST registers used, defined and clobbered. We can
1377 // only tell clobbers from defs by looking at the asm descriptor.
1378 unsigned STUses = 0, STDefs = 0, STClobbers = 0, STDeadDefs = 0;
1379 unsigned NumOps = 0;
1380 SmallSet<unsigned, 1> FRegIdx;
1383 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI->getNumOperands();
1384 i != e && MI->getOperand(i).isImm(); i += 1 + NumOps) {
1385 unsigned Flags = MI->getOperand(i).getImm();
1387 NumOps = InlineAsm::getNumOperandRegisters(Flags);
1390 const MachineOperand &MO = MI->getOperand(i + 1);
1393 unsigned STReg = MO.getReg() - X86::FP0;
1397 // If the flag has a register class constraint, this must be an operand
1398 // with constraint "f". Record its index and continue.
1399 if (InlineAsm::hasRegClassConstraint(Flags, RCID)) {
1400 FRegIdx.insert(i + 1);
1404 switch (InlineAsm::getKind(Flags)) {
1405 case InlineAsm::Kind_RegUse:
1406 STUses |= (1u << STReg);
1408 case InlineAsm::Kind_RegDef:
1409 case InlineAsm::Kind_RegDefEarlyClobber:
1410 STDefs |= (1u << STReg);
1412 STDeadDefs |= (1u << STReg);
1414 case InlineAsm::Kind_Clobber:
1415 STClobbers |= (1u << STReg);
1422 if (STUses && !isMask_32(STUses))
1423 MI->emitError("fixed input regs must be last on the x87 stack");
1424 unsigned NumSTUses = countTrailingOnes(STUses);
1426 // Defs must be contiguous from the stack top. ST0-STn.
1427 if (STDefs && !isMask_32(STDefs)) {
1428 MI->emitError("output regs must be last on the x87 stack");
1429 STDefs = NextPowerOf2(STDefs) - 1;
1431 unsigned NumSTDefs = countTrailingOnes(STDefs);
1433 // So must the clobbered stack slots. ST0-STm, m >= n.
1434 if (STClobbers && !isMask_32(STDefs | STClobbers))
1435 MI->emitError("clobbers must be last on the x87 stack");
1437 // Popped inputs are the ones that are also clobbered or defined.
1438 unsigned STPopped = STUses & (STDefs | STClobbers);
1439 if (STPopped && !isMask_32(STPopped))
1440 MI->emitError("implicitly popped regs must be last on the x87 stack");
1441 unsigned NumSTPopped = countTrailingOnes(STPopped);
1443 DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops "
1444 << NumSTPopped << ", and defines " << NumSTDefs << " regs.\n");
1447 // If any input operand uses constraint "f", all output register
1448 // constraints must be early-clobber defs.
1449 for (unsigned I = 0, E = MI->getNumOperands(); I < E; ++I)
1450 if (FRegIdx.count(I)) {
1451 assert((1 << getFPReg(MI->getOperand(I)) & STDefs) == 0 &&
1452 "Operands with constraint \"f\" cannot overlap with defs");
1456 // Collect all FP registers (register operands with constraints "t", "u",
1457 // and "f") to kill afer the instruction.
1458 unsigned FPKills = ((1u << NumFPRegs) - 1) & ~0xff;
1459 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1460 MachineOperand &Op = MI->getOperand(i);
1461 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1463 unsigned FPReg = getFPReg(Op);
1465 // If we kill this operand, make sure to pop it from the stack after the
1466 // asm. We just remember it for now, and pop them all off at the end in
1468 if (Op.isUse() && Op.isKill())
1469 FPKills |= 1U << FPReg;
1472 // Do not include registers that are implicitly popped by defs/clobbers.
1473 FPKills &= ~(STDefs | STClobbers);
1475 // Now we can rearrange the live registers to match what was requested.
1476 unsigned char STUsesArray[8];
1478 for (unsigned I = 0; I < NumSTUses; ++I)
1481 shuffleStackTop(STUsesArray, NumSTUses, Inst);
1482 DEBUG({dbgs() << "Before asm: "; dumpStack();});
1484 // With the stack layout fixed, rewrite the FP registers.
1485 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1486 MachineOperand &Op = MI->getOperand(i);
1487 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1490 unsigned FPReg = getFPReg(Op);
1492 if (FRegIdx.count(i))
1493 // Operand with constraint "f".
1494 Op.setReg(getSTReg(FPReg));
1496 // Operand with a single register class constraint ("t" or "u").
1497 Op.setReg(X86::ST0 + FPReg);
1500 // Simulate the inline asm popping its inputs and pushing its outputs.
1501 StackTop -= NumSTPopped;
1503 for (unsigned i = 0; i < NumSTDefs; ++i)
1504 pushReg(NumSTDefs - i - 1);
1506 // If this asm kills any FP registers (is the last use of them) we must
1507 // explicitly emit pop instructions for them. Do this now after the asm has
1508 // executed so that the ST(x) numbers are not off (which would happen if we
1509 // did this inline with operand rewriting).
1511 // Note: this might be a non-optimal pop sequence. We might be able to do
1512 // better by trying to pop in stack order or something.
1514 unsigned FPReg = countTrailingZeros(FPKills);
1516 freeStackSlotAfter(Inst, FPReg);
1517 FPKills &= ~(1U << FPReg);
1520 // Don't delete the inline asm!
1524 case X86::WIN_FTOL_32:
1525 case X86::WIN_FTOL_64: {
1526 // Push the operand into ST0.
1527 MachineOperand &Op = MI->getOperand(0);
1528 assert(Op.isUse() && Op.isReg() &&
1529 Op.getReg() >= X86::FP0 && Op.getReg() <= X86::FP6);
1530 unsigned FPReg = getFPReg(Op);
1532 moveToTop(FPReg, Inst);
1534 duplicateToTop(FPReg, ScratchFPReg, Inst);
1536 // Emit the call. This will pop the operand.
1537 BuildMI(*MBB, Inst, MI->getDebugLoc(), TII->get(X86::CALLpcrel32))
1538 .addExternalSymbol("_ftol2")
1539 .addReg(X86::ST0, RegState::ImplicitKill)
1540 .addReg(X86::ECX, RegState::ImplicitDefine)
1541 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
1542 .addReg(X86::EDX, RegState::Define | RegState::Implicit)
1543 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
1553 // If RET has an FP register use operand, pass the first one in ST(0) and
1554 // the second one in ST(1).
1556 // Find the register operands.
1557 unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
1558 unsigned LiveMask = 0;
1560 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1561 MachineOperand &Op = MI->getOperand(i);
1562 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1564 // FP Register uses must be kills unless there are two uses of the same
1565 // register, in which case only one will be a kill.
1566 assert(Op.isUse() &&
1567 (Op.isKill() || // Marked kill.
1568 getFPReg(Op) == FirstFPRegOp || // Second instance.
1569 MI->killsRegister(Op.getReg())) && // Later use is marked kill.
1570 "Ret only defs operands, and values aren't live beyond it");
1572 if (FirstFPRegOp == ~0U)
1573 FirstFPRegOp = getFPReg(Op);
1575 assert(SecondFPRegOp == ~0U && "More than two fp operands!");
1576 SecondFPRegOp = getFPReg(Op);
1578 LiveMask |= (1 << getFPReg(Op));
1580 // Remove the operand so that later passes don't see it.
1581 MI->RemoveOperand(i);
1585 // We may have been carrying spurious live-ins, so make sure only the returned
1586 // registers are left live.
1587 adjustLiveRegs(LiveMask, MI);
1588 if (!LiveMask) return; // Quick check to see if any are possible.
1590 // There are only four possibilities here:
1591 // 1) we are returning a single FP value. In this case, it has to be in
1592 // ST(0) already, so just declare success by removing the value from the
1594 if (SecondFPRegOp == ~0U) {
1595 // Assert that the top of stack contains the right FP register.
1596 assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
1597 "Top of stack not the right register for RET!");
1599 // Ok, everything is good, mark the value as not being on the stack
1600 // anymore so that our assertion about the stack being empty at end of
1601 // block doesn't fire.
1606 // Otherwise, we are returning two values:
1607 // 2) If returning the same value for both, we only have one thing in the FP
1608 // stack. Consider: RET FP1, FP1
1609 if (StackTop == 1) {
1610 assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
1611 "Stack misconfiguration for RET!");
1613 // Duplicate the TOS so that we return it twice. Just pick some other FPx
1614 // register to hold it.
1615 unsigned NewReg = ScratchFPReg;
1616 duplicateToTop(FirstFPRegOp, NewReg, MI);
1617 FirstFPRegOp = NewReg;
1620 /// Okay we know we have two different FPx operands now:
1621 assert(StackTop == 2 && "Must have two values live!");
1623 /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently
1624 /// in ST(1). In this case, emit an fxch.
1625 if (getStackEntry(0) == SecondFPRegOp) {
1626 assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live");
1627 moveToTop(FirstFPRegOp, MI);
1630 /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in
1631 /// ST(1). Just remove both from our understanding of the stack and return.
1632 assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
1633 assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live");
1638 Inst = MBB->erase(Inst); // Remove the pseudo instruction
1640 // We want to leave I pointing to the previous instruction, but what if we
1641 // just erased the first instruction?
1642 if (Inst == MBB->begin()) {
1643 DEBUG(dbgs() << "Inserting dummy KILL\n");
1644 Inst = BuildMI(*MBB, Inst, DebugLoc(), TII->get(TargetOpcode::KILL));
1649 void FPS::setKillFlags(MachineBasicBlock &MBB) const {
1650 const TargetRegisterInfo *TRI =
1651 MBB.getParent()->getSubtarget().getRegisterInfo();
1652 LivePhysRegs LPR(TRI);
1654 LPR.addLiveOuts(&MBB);
1656 for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend();
1658 if (I->isDebugValue())
1661 std::bitset<8> Defs;
1662 SmallVector<MachineOperand *, 2> Uses;
1663 MachineInstr &MI = *I;
1665 for (auto &MO : I->operands()) {
1669 unsigned Reg = MO.getReg() - X86::FP0;
1676 if (!LPR.contains(MO.getReg()))
1679 Uses.push_back(&MO);
1682 for (auto *MO : Uses)
1683 if (Defs.test(getFPReg(*MO)) || !LPR.contains(MO->getReg()))
1686 LPR.stepBackward(MI);