1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/Analysis/EHPersonalities.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/WinEHFuncInfo.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCSymbol.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Target/TargetOptions.h"
38 X86FrameLowering::X86FrameLowering(const X86Subtarget &STI,
39 unsigned StackAlignOverride)
40 : TargetFrameLowering(StackGrowsDown, StackAlignOverride,
41 STI.is64Bit() ? -8 : -4),
42 STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
43 // Cache a bunch of frame-related predicates for this subtarget.
44 SlotSize = TRI->getSlotSize();
45 Is64Bit = STI.is64Bit();
46 IsLP64 = STI.isTarget64BitLP64();
47 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
48 Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
49 StackPtr = TRI->getStackRegister();
52 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
53 return !MF.getFrameInfo().hasVarSizedObjects() &&
54 !MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
57 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
58 /// call frame pseudos can be simplified. Having a FP, as in the default
59 /// implementation, is not sufficient here since we can't always use it.
60 /// Use a more nuanced condition.
62 X86FrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
63 return hasReservedCallFrame(MF) ||
64 (hasFP(MF) && !TRI->needsStackRealignment(MF)) ||
65 TRI->hasBasePointer(MF);
68 // needsFrameIndexResolution - Do we need to perform FI resolution for
69 // this function. Normally, this is required only when the function
70 // has any stack objects. However, FI resolution actually has another job,
71 // not apparent from the title - it resolves callframesetup/destroy
72 // that were not simplified earlier.
73 // So, this is required for x86 functions that have push sequences even
74 // when there are no stack objects.
76 X86FrameLowering::needsFrameIndexResolution(const MachineFunction &MF) const {
77 return MF.getFrameInfo().hasStackObjects() ||
78 MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
81 /// hasFP - Return true if the specified function should have a dedicated frame
82 /// pointer register. This is true if the function has variable sized allocas
83 /// or if frame pointer elimination is disabled.
84 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
85 const MachineFrameInfo &MFI = MF.getFrameInfo();
86 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
87 TRI->needsStackRealignment(MF) ||
88 MFI.hasVarSizedObjects() ||
89 MFI.isFrameAddressTaken() || MFI.hasOpaqueSPAdjustment() ||
90 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
91 MF.callsUnwindInit() || MF.hasEHFunclets() || MF.callsEHReturn() ||
92 MFI.hasStackMap() || MFI.hasPatchPoint() ||
93 MFI.hasCopyImplyingStackAdjustment());
96 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
100 return X86::SUB64ri32;
103 return X86::SUB32ri8;
108 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
111 return X86::ADD64ri8;
112 return X86::ADD64ri32;
115 return X86::ADD32ri8;
120 static unsigned getSUBrrOpcode(unsigned isLP64) {
121 return isLP64 ? X86::SUB64rr : X86::SUB32rr;
124 static unsigned getADDrrOpcode(unsigned isLP64) {
125 return isLP64 ? X86::ADD64rr : X86::ADD32rr;
128 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
131 return X86::AND64ri8;
132 return X86::AND64ri32;
135 return X86::AND32ri8;
139 static unsigned getLEArOpcode(unsigned IsLP64) {
140 return IsLP64 ? X86::LEA64r : X86::LEA32r;
143 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
144 /// when it reaches the "return" instruction. We can then pop a stack object
145 /// to this register without worry about clobbering it.
146 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
147 MachineBasicBlock::iterator &MBBI,
148 const X86RegisterInfo *TRI,
150 const MachineFunction *MF = MBB.getParent();
151 if (MF->callsEHReturn())
154 const TargetRegisterClass &AvailableRegs = *TRI->getGPRsForTailCall(*MF);
156 if (MBBI == MBB.end())
159 switch (MBBI->getOpcode()) {
161 case TargetOpcode::PATCHABLE_RET:
167 case X86::TCRETURNdi:
168 case X86::TCRETURNri:
169 case X86::TCRETURNmi:
170 case X86::TCRETURNdi64:
171 case X86::TCRETURNri64:
172 case X86::TCRETURNmi64:
174 case X86::EH_RETURN64: {
175 SmallSet<uint16_t, 8> Uses;
176 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
177 MachineOperand &MO = MBBI->getOperand(i);
178 if (!MO.isReg() || MO.isDef())
180 unsigned Reg = MO.getReg();
183 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
187 for (auto CS : AvailableRegs)
188 if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP &&
197 static bool isEAXLiveIn(MachineBasicBlock &MBB) {
198 for (MachineBasicBlock::RegisterMaskPair RegMask : MBB.liveins()) {
199 unsigned Reg = RegMask.PhysReg;
201 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
202 Reg == X86::AH || Reg == X86::AL)
209 /// Check if the flags need to be preserved before the terminators.
210 /// This would be the case, if the eflags is live-in of the region
211 /// composed by the terminators or live-out of that region, without
212 /// being defined by a terminator.
214 flagsNeedToBePreservedBeforeTheTerminators(const MachineBasicBlock &MBB) {
215 for (const MachineInstr &MI : MBB.terminators()) {
216 bool BreakNext = false;
217 for (const MachineOperand &MO : MI.operands()) {
220 unsigned Reg = MO.getReg();
221 if (Reg != X86::EFLAGS)
224 // This terminator needs an eflags that is not defined
225 // by a previous another terminator:
226 // EFLAGS is live-in of the region composed by the terminators.
229 // This terminator defines the eflags, i.e., we don't need to preserve it.
230 // However, we still need to check this specific terminator does not
231 // read a live-in value.
234 // We found a definition of the eflags, no need to preserve them.
239 // None of the terminators use or define the eflags.
240 // Check if they are live-out, that would imply we need to preserve them.
241 for (const MachineBasicBlock *Succ : MBB.successors())
242 if (Succ->isLiveIn(X86::EFLAGS))
248 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
249 /// stack pointer by a constant value.
250 void X86FrameLowering::emitSPUpdate(MachineBasicBlock &MBB,
251 MachineBasicBlock::iterator &MBBI,
253 int64_t NumBytes, bool InEpilogue) const {
254 bool isSub = NumBytes < 0;
255 uint64_t Offset = isSub ? -NumBytes : NumBytes;
256 MachineInstr::MIFlag Flag =
257 isSub ? MachineInstr::FrameSetup : MachineInstr::FrameDestroy;
259 uint64_t Chunk = (1LL << 31) - 1;
261 if (Offset > Chunk) {
262 // Rather than emit a long series of instructions for large offsets,
263 // load the offset into a register and do one sub/add
265 unsigned Rax = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
267 if (isSub && !isEAXLiveIn(MBB))
270 Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
272 unsigned MovRIOpc = Is64Bit ? X86::MOV64ri : X86::MOV32ri;
273 unsigned AddSubRROpc =
274 isSub ? getSUBrrOpcode(Is64Bit) : getADDrrOpcode(Is64Bit);
276 BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Reg)
279 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr)
282 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
284 } else if (Offset > 8 * Chunk) {
285 // If we would need more than 8 add or sub instructions (a >16GB stack
286 // frame), it's worth spilling RAX to materialize this immediate.
288 // movabsq +-$Offset+-SlotSize, %rax
292 assert(Is64Bit && "can't have 32-bit 16GB stack frame");
293 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
294 .addReg(Rax, RegState::Kill)
296 // Subtract is not commutative, so negate the offset and always use add.
297 // Subtract 8 less and add 8 more to account for the PUSH we just did.
299 Offset = -(Offset - SlotSize);
301 Offset = Offset + SlotSize;
302 BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Rax)
305 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(X86::ADD64rr), Rax)
308 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
309 // Exchange the new SP in RAX with the top of the stack.
311 BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax),
313 // Load new SP from the top of the stack into RSP.
314 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr),
321 uint64_t ThisVal = std::min(Offset, Chunk);
322 if (ThisVal == SlotSize) {
323 // Use push / pop for slot sized adjustments as a size optimization. We
324 // need to find a dead register when using pop.
326 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
327 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
330 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
331 : (Is64Bit ? X86::POP64r : X86::POP32r);
332 BuildMI(MBB, MBBI, DL, TII.get(Opc))
333 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub))
340 BuildStackAdjustment(MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue)
347 MachineInstrBuilder X86FrameLowering::BuildStackAdjustment(
348 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
349 const DebugLoc &DL, int64_t Offset, bool InEpilogue) const {
350 assert(Offset != 0 && "zero offset stack adjustment requested");
352 // On Atom, using LEA to adjust SP is preferred, but using it in the epilogue
356 // Check if inserting the prologue at the beginning
357 // of MBB would require to use LEA operations.
358 // We need to use LEA operations if EFLAGS is live in, because
359 // it means an instruction will read it before it gets defined.
360 UseLEA = STI.useLeaForSP() || MBB.isLiveIn(X86::EFLAGS);
362 // If we can use LEA for SP but we shouldn't, check that none
363 // of the terminators uses the eflags. Otherwise we will insert
364 // a ADD that will redefine the eflags and break the condition.
365 // Alternatively, we could move the ADD, but this may not be possible
366 // and is an optimization anyway.
367 UseLEA = canUseLEAForSPInEpilogue(*MBB.getParent());
368 if (UseLEA && !STI.useLeaForSP())
369 UseLEA = flagsNeedToBePreservedBeforeTheTerminators(MBB);
370 // If that assert breaks, that means we do not do the right thing
371 // in canUseAsEpilogue.
372 assert((UseLEA || !flagsNeedToBePreservedBeforeTheTerminators(MBB)) &&
373 "We shouldn't have allowed this insertion point");
376 MachineInstrBuilder MI;
378 MI = addRegOffset(BuildMI(MBB, MBBI, DL,
379 TII.get(getLEArOpcode(Uses64BitFramePtr)),
381 StackPtr, false, Offset);
383 bool IsSub = Offset < 0;
384 uint64_t AbsOffset = IsSub ? -Offset : Offset;
385 unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset)
386 : getADDriOpcode(Uses64BitFramePtr, AbsOffset);
387 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
390 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
395 int X86FrameLowering::mergeSPUpdates(MachineBasicBlock &MBB,
396 MachineBasicBlock::iterator &MBBI,
397 bool doMergeWithPrevious) const {
398 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
399 (!doMergeWithPrevious && MBBI == MBB.end()))
402 MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
404 PI = skipDebugInstructionsBackward(PI, MBB.begin());
405 // It is assumed that ADD/SUB/LEA instruction is succeded by one CFI
406 // instruction, and that there are no DBG_VALUE or other instructions between
407 // ADD/SUB/LEA and its corresponding CFI instruction.
408 /* TODO: Add support for the case where there are multiple CFI instructions
409 below the ADD/SUB/LEA, e.g.:
416 if (doMergeWithPrevious && PI != MBB.begin() && PI->isCFIInstruction())
419 unsigned Opc = PI->getOpcode();
422 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
423 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
424 PI->getOperand(0).getReg() == StackPtr){
425 assert(PI->getOperand(1).getReg() == StackPtr);
426 Offset = PI->getOperand(2).getImm();
427 } else if ((Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
428 PI->getOperand(0).getReg() == StackPtr &&
429 PI->getOperand(1).getReg() == StackPtr &&
430 PI->getOperand(2).getImm() == 1 &&
431 PI->getOperand(3).getReg() == X86::NoRegister &&
432 PI->getOperand(5).getReg() == X86::NoRegister) {
433 // For LEAs we have: def = lea SP, FI, noreg, Offset, noreg.
434 Offset = PI->getOperand(4).getImm();
435 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
436 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
437 PI->getOperand(0).getReg() == StackPtr) {
438 assert(PI->getOperand(1).getReg() == StackPtr);
439 Offset = -PI->getOperand(2).getImm();
444 if (PI != MBB.end() && PI->isCFIInstruction()) PI = MBB.erase(PI);
445 if (!doMergeWithPrevious)
446 MBBI = skipDebugInstructionsForward(PI, MBB.end());
451 void X86FrameLowering::BuildCFI(MachineBasicBlock &MBB,
452 MachineBasicBlock::iterator MBBI,
454 const MCCFIInstruction &CFIInst) const {
455 MachineFunction &MF = *MBB.getParent();
456 unsigned CFIIndex = MF.addFrameInst(CFIInst);
457 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
458 .addCFIIndex(CFIIndex);
461 void X86FrameLowering::emitCalleeSavedFrameMoves(
462 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
463 const DebugLoc &DL) const {
464 MachineFunction &MF = *MBB.getParent();
465 MachineFrameInfo &MFI = MF.getFrameInfo();
466 MachineModuleInfo &MMI = MF.getMMI();
467 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
469 // Add callee saved registers to move list.
470 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
471 if (CSI.empty()) return;
473 // Calculate offsets.
474 for (std::vector<CalleeSavedInfo>::const_iterator
475 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
476 int64_t Offset = MFI.getObjectOffset(I->getFrameIdx());
477 unsigned Reg = I->getReg();
479 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
480 BuildCFI(MBB, MBBI, DL,
481 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
485 void X86FrameLowering::emitStackProbe(MachineFunction &MF,
486 MachineBasicBlock &MBB,
487 MachineBasicBlock::iterator MBBI,
488 const DebugLoc &DL, bool InProlog) const {
489 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
490 if (STI.isTargetWindowsCoreCLR()) {
492 emitStackProbeInlineStub(MF, MBB, MBBI, DL, true);
494 emitStackProbeInline(MF, MBB, MBBI, DL, false);
497 emitStackProbeCall(MF, MBB, MBBI, DL, InProlog);
501 void X86FrameLowering::inlineStackProbe(MachineFunction &MF,
502 MachineBasicBlock &PrologMBB) const {
503 const StringRef ChkStkStubSymbol = "__chkstk_stub";
504 MachineInstr *ChkStkStub = nullptr;
506 for (MachineInstr &MI : PrologMBB) {
507 if (MI.isCall() && MI.getOperand(0).isSymbol() &&
508 ChkStkStubSymbol == MI.getOperand(0).getSymbolName()) {
514 if (ChkStkStub != nullptr) {
515 assert(!ChkStkStub->isBundled() &&
516 "Not expecting bundled instructions here");
517 MachineBasicBlock::iterator MBBI = std::next(ChkStkStub->getIterator());
518 assert(std::prev(MBBI) == ChkStkStub &&
519 "MBBI expected after __chkstk_stub.");
520 DebugLoc DL = PrologMBB.findDebugLoc(MBBI);
521 emitStackProbeInline(MF, PrologMBB, MBBI, DL, true);
522 ChkStkStub->eraseFromParent();
526 void X86FrameLowering::emitStackProbeInline(MachineFunction &MF,
527 MachineBasicBlock &MBB,
528 MachineBasicBlock::iterator MBBI,
530 bool InProlog) const {
531 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
532 assert(STI.is64Bit() && "different expansion needed for 32 bit");
533 assert(STI.isTargetWindowsCoreCLR() && "custom expansion expects CoreCLR");
534 const TargetInstrInfo &TII = *STI.getInstrInfo();
535 const BasicBlock *LLVM_BB = MBB.getBasicBlock();
537 // RAX contains the number of bytes of desired stack adjustment.
538 // The handling here assumes this value has already been updated so as to
539 // maintain stack alignment.
541 // We need to exit with RSP modified by this amount and execute suitable
542 // page touches to notify the OS that we're growing the stack responsibly.
543 // All stack probing must be done without modifying RSP.
549 // Flags, TestReg = CopyReg - SizeReg
550 // FinalReg = !Flags.Ovf ? TestReg : ZeroReg
551 // LimitReg = gs magic thread env access
552 // if FinalReg >= LimitReg goto ContinueMBB
554 // RoundReg = page address of FinalReg
556 // LoopReg = PHI(LimitReg,ProbeReg)
557 // ProbeReg = LoopReg - PageSize
559 // if (ProbeReg > RoundReg) goto LoopMBB
562 // [rest of original MBB]
564 // Set up the new basic blocks
565 MachineBasicBlock *RoundMBB = MF.CreateMachineBasicBlock(LLVM_BB);
566 MachineBasicBlock *LoopMBB = MF.CreateMachineBasicBlock(LLVM_BB);
567 MachineBasicBlock *ContinueMBB = MF.CreateMachineBasicBlock(LLVM_BB);
569 MachineFunction::iterator MBBIter = std::next(MBB.getIterator());
570 MF.insert(MBBIter, RoundMBB);
571 MF.insert(MBBIter, LoopMBB);
572 MF.insert(MBBIter, ContinueMBB);
574 // Split MBB and move the tail portion down to ContinueMBB.
575 MachineBasicBlock::iterator BeforeMBBI = std::prev(MBBI);
576 ContinueMBB->splice(ContinueMBB->begin(), &MBB, MBBI, MBB.end());
577 ContinueMBB->transferSuccessorsAndUpdatePHIs(&MBB);
579 // Some useful constants
580 const int64_t ThreadEnvironmentStackLimit = 0x10;
581 const int64_t PageSize = 0x1000;
582 const int64_t PageMask = ~(PageSize - 1);
584 // Registers we need. For the normal case we use virtual
585 // registers. For the prolog expansion we use RAX, RCX and RDX.
586 MachineRegisterInfo &MRI = MF.getRegInfo();
587 const TargetRegisterClass *RegClass = &X86::GR64RegClass;
588 const unsigned SizeReg = InProlog ? (unsigned)X86::RAX
589 : MRI.createVirtualRegister(RegClass),
590 ZeroReg = InProlog ? (unsigned)X86::RCX
591 : MRI.createVirtualRegister(RegClass),
592 CopyReg = InProlog ? (unsigned)X86::RDX
593 : MRI.createVirtualRegister(RegClass),
594 TestReg = InProlog ? (unsigned)X86::RDX
595 : MRI.createVirtualRegister(RegClass),
596 FinalReg = InProlog ? (unsigned)X86::RDX
597 : MRI.createVirtualRegister(RegClass),
598 RoundedReg = InProlog ? (unsigned)X86::RDX
599 : MRI.createVirtualRegister(RegClass),
600 LimitReg = InProlog ? (unsigned)X86::RCX
601 : MRI.createVirtualRegister(RegClass),
602 JoinReg = InProlog ? (unsigned)X86::RCX
603 : MRI.createVirtualRegister(RegClass),
604 ProbeReg = InProlog ? (unsigned)X86::RCX
605 : MRI.createVirtualRegister(RegClass);
607 // SP-relative offsets where we can save RCX and RDX.
608 int64_t RCXShadowSlot = 0;
609 int64_t RDXShadowSlot = 0;
611 // If inlining in the prolog, save RCX and RDX.
613 // Compute the offsets. We need to account for things already
614 // pushed onto the stack at this point: return address, frame
615 // pointer (if used), and callee saves.
616 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
617 const int64_t CalleeSaveSize = X86FI->getCalleeSavedFrameSize();
618 const bool HasFP = hasFP(MF);
620 // Check if we need to spill RCX and/or RDX.
621 // Here we assume that no earlier prologue instruction changes RCX and/or
622 // RDX, so checking the block live-ins is enough.
623 const bool IsRCXLiveIn = MBB.isLiveIn(X86::RCX);
624 const bool IsRDXLiveIn = MBB.isLiveIn(X86::RDX);
625 int64_t InitSlot = 8 + CalleeSaveSize + (HasFP ? 8 : 0);
626 // Assign the initial slot to both registers, then change RDX's slot if both
627 // need to be spilled.
629 RCXShadowSlot = InitSlot;
631 RDXShadowSlot = InitSlot;
632 if (IsRDXLiveIn && IsRCXLiveIn)
634 // Emit the saves if needed.
636 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
640 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
644 // Not in the prolog. Copy RAX to a virtual reg.
645 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX);
648 // Add code to MBB to check for overflow and set the new target stack pointer
650 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg)
651 .addReg(ZeroReg, RegState::Undef)
652 .addReg(ZeroReg, RegState::Undef);
653 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), CopyReg).addReg(X86::RSP);
654 BuildMI(&MBB, DL, TII.get(X86::SUB64rr), TestReg)
657 BuildMI(&MBB, DL, TII.get(X86::CMOVB64rr), FinalReg)
661 // FinalReg now holds final stack pointer value, or zero if
662 // allocation would overflow. Compare against the current stack
663 // limit from the thread environment block. Note this limit is the
664 // lowest touched page on the stack, not the point at which the OS
665 // will cause an overflow exception, so this is just an optimization
666 // to avoid unnecessarily touching pages that are below the current
667 // SP but already committed to the stack by the OS.
668 BuildMI(&MBB, DL, TII.get(X86::MOV64rm), LimitReg)
672 .addImm(ThreadEnvironmentStackLimit)
674 BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg);
675 // Jump if the desired stack pointer is at or above the stack limit.
676 BuildMI(&MBB, DL, TII.get(X86::JAE_1)).addMBB(ContinueMBB);
678 // Add code to roundMBB to round the final stack pointer to a page boundary.
679 RoundMBB->addLiveIn(FinalReg);
680 BuildMI(RoundMBB, DL, TII.get(X86::AND64ri32), RoundedReg)
683 BuildMI(RoundMBB, DL, TII.get(X86::JMP_1)).addMBB(LoopMBB);
685 // LimitReg now holds the current stack limit, RoundedReg page-rounded
686 // final RSP value. Add code to loopMBB to decrement LimitReg page-by-page
687 // and probe until we reach RoundedReg.
689 BuildMI(LoopMBB, DL, TII.get(X86::PHI), JoinReg)
696 LoopMBB->addLiveIn(JoinReg);
697 addRegOffset(BuildMI(LoopMBB, DL, TII.get(X86::LEA64r), ProbeReg), JoinReg,
700 // Probe by storing a byte onto the stack.
701 BuildMI(LoopMBB, DL, TII.get(X86::MOV8mi))
709 LoopMBB->addLiveIn(RoundedReg);
710 BuildMI(LoopMBB, DL, TII.get(X86::CMP64rr))
713 BuildMI(LoopMBB, DL, TII.get(X86::JNE_1)).addMBB(LoopMBB);
715 MachineBasicBlock::iterator ContinueMBBI = ContinueMBB->getFirstNonPHI();
717 // If in prolog, restore RDX and RCX.
719 if (RCXShadowSlot) // It means we spilled RCX in the prologue.
720 addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL,
721 TII.get(X86::MOV64rm), X86::RCX),
722 X86::RSP, false, RCXShadowSlot);
723 if (RDXShadowSlot) // It means we spilled RDX in the prologue.
724 addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL,
725 TII.get(X86::MOV64rm), X86::RDX),
726 X86::RSP, false, RDXShadowSlot);
729 // Now that the probing is done, add code to continueMBB to update
730 // the stack pointer for real.
731 ContinueMBB->addLiveIn(SizeReg);
732 BuildMI(*ContinueMBB, ContinueMBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
736 // Add the control flow edges we need.
737 MBB.addSuccessor(ContinueMBB);
738 MBB.addSuccessor(RoundMBB);
739 RoundMBB->addSuccessor(LoopMBB);
740 LoopMBB->addSuccessor(ContinueMBB);
741 LoopMBB->addSuccessor(LoopMBB);
743 // Mark all the instructions added to the prolog as frame setup.
745 for (++BeforeMBBI; BeforeMBBI != MBB.end(); ++BeforeMBBI) {
746 BeforeMBBI->setFlag(MachineInstr::FrameSetup);
748 for (MachineInstr &MI : *RoundMBB) {
749 MI.setFlag(MachineInstr::FrameSetup);
751 for (MachineInstr &MI : *LoopMBB) {
752 MI.setFlag(MachineInstr::FrameSetup);
754 for (MachineBasicBlock::iterator CMBBI = ContinueMBB->begin();
755 CMBBI != ContinueMBBI; ++CMBBI) {
756 CMBBI->setFlag(MachineInstr::FrameSetup);
761 void X86FrameLowering::emitStackProbeCall(MachineFunction &MF,
762 MachineBasicBlock &MBB,
763 MachineBasicBlock::iterator MBBI,
765 bool InProlog) const {
766 bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
768 // FIXME: Add retpoline support and remove this.
769 if (Is64Bit && IsLargeCodeModel && STI.useRetpolineIndirectCalls())
770 report_fatal_error("Emitting stack probe calls on 64-bit with the large "
771 "code model and retpoline not yet implemented.");
775 CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
777 CallOp = X86::CALLpcrel32;
779 StringRef Symbol = STI.getTargetLowering()->getStackProbeSymbolName(MF);
781 MachineInstrBuilder CI;
782 MachineBasicBlock::iterator ExpansionMBBI = std::prev(MBBI);
784 // All current stack probes take AX and SP as input, clobber flags, and
785 // preserve all registers. x86_64 probes leave RSP unmodified.
786 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
787 // For the large code model, we have to call through a register. Use R11,
788 // as it is scratch in all supported calling conventions.
789 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
790 .addExternalSymbol(MF.createExternalSymbolName(Symbol));
791 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
793 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp))
794 .addExternalSymbol(MF.createExternalSymbolName(Symbol));
797 unsigned AX = Is64Bit ? X86::RAX : X86::EAX;
798 unsigned SP = Is64Bit ? X86::RSP : X86::ESP;
799 CI.addReg(AX, RegState::Implicit)
800 .addReg(SP, RegState::Implicit)
801 .addReg(AX, RegState::Define | RegState::Implicit)
802 .addReg(SP, RegState::Define | RegState::Implicit)
803 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
805 if (STI.isTargetWin64() || !STI.isOSWindows()) {
806 // MSVC x32's _chkstk and cygwin/mingw's _alloca adjust %esp themselves.
807 // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
808 // themselves. They also does not clobber %rax so we can reuse it when
810 // All other platforms do not specify a particular ABI for the stack probe
811 // function, so we arbitrarily define it to not adjust %esp/%rsp itself.
812 BuildMI(MBB, MBBI, DL, TII.get(getSUBrrOpcode(Is64Bit)), SP)
818 // Apply the frame setup flag to all inserted instrs.
819 for (++ExpansionMBBI; ExpansionMBBI != MBBI; ++ExpansionMBBI)
820 ExpansionMBBI->setFlag(MachineInstr::FrameSetup);
824 void X86FrameLowering::emitStackProbeInlineStub(
825 MachineFunction &MF, MachineBasicBlock &MBB,
826 MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog) const {
828 assert(InProlog && "ChkStkStub called outside prolog!");
830 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
831 .addExternalSymbol("__chkstk_stub");
834 static unsigned calculateSetFPREG(uint64_t SPAdjust) {
835 // Win64 ABI has a less restrictive limitation of 240; 128 works equally well
836 // and might require smaller successive adjustments.
837 const uint64_t Win64MaxSEHOffset = 128;
838 uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
839 // Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
840 return SEHFrameOffset & -16;
843 // If we're forcing a stack realignment we can't rely on just the frame
844 // info, we need to know the ABI stack alignment as well in case we
845 // have a call out. Otherwise just make sure we have some alignment - we'll
846 // go with the minimum SlotSize.
847 uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
848 const MachineFrameInfo &MFI = MF.getFrameInfo();
849 uint64_t MaxAlign = MFI.getMaxAlignment(); // Desired stack alignment.
850 unsigned StackAlign = getStackAlignment();
851 if (MF.getFunction().hasFnAttribute("stackrealign")) {
853 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
854 else if (MaxAlign < SlotSize)
860 void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
861 MachineBasicBlock::iterator MBBI,
862 const DebugLoc &DL, unsigned Reg,
863 uint64_t MaxAlign) const {
864 uint64_t Val = -MaxAlign;
865 unsigned AndOp = getANDriOpcode(Uses64BitFramePtr, Val);
866 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AndOp), Reg)
869 .setMIFlag(MachineInstr::FrameSetup);
871 // The EFLAGS implicit def is dead.
872 MI->getOperand(3).setIsDead();
875 /// emitPrologue - Push callee-saved registers onto the stack, which
876 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
877 /// space for local variables. Also emit labels used by the exception handler to
878 /// generate the exception handling frames.
881 Here's a gist of what gets emitted:
883 ; Establish frame pointer, if needed
886 .cfi_def_cfa_offset 16
887 .cfi_offset %rbp, -16
890 .cfi_def_cfa_register %rbp
892 ; Spill general-purpose registers
893 [for all callee-saved GPRs]
896 .cfi_def_cfa_offset (offset from RETADDR)
899 ; If the required stack alignment > default stack alignment
900 ; rsp needs to be re-aligned. This creates a "re-alignment gap"
901 ; of unknown size in the stack frame.
902 [if stack needs re-alignment]
905 ; Allocate space for locals
906 [if target is Windows and allocated space > 4096 bytes]
907 ; Windows needs special care for allocations larger
910 call ___chkstk_ms/___chkstk
916 .seh_stackalloc (size of XMM spill slots)
917 .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
922 ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
923 ; they may get spilled on any platform, if the current function
924 ; calls @llvm.eh.unwind.init
926 [for all callee-saved XMM registers]
927 movaps %<xmm reg>, -MMM(%rbp)
928 [for all callee-saved XMM registers]
929 .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
930 ; i.e. the offset relative to (%rbp - SEHFrameOffset)
932 [for all callee-saved XMM registers]
933 movaps %<xmm reg>, KKK(%rsp)
934 [for all callee-saved XMM registers]
935 .seh_savexmm %<xmm reg>, KKK
939 [if needs base pointer]
941 [if needs to restore base pointer]
946 [for all callee-saved registers]
947 .cfi_offset %<reg>, (offset from %rbp)
949 .cfi_def_cfa_offset (offset from RETADDR)
950 [for all callee-saved registers]
951 .cfi_offset %<reg>, (offset from %rsp)
954 - .seh directives are emitted only for Windows 64 ABI
955 - .cv_fpo directives are emitted on win32 when emitting CodeView
956 - .cfi directives are emitted for all other ABIs
957 - for 32-bit code, substitute %e?? registers for %r??
960 void X86FrameLowering::emitPrologue(MachineFunction &MF,
961 MachineBasicBlock &MBB) const {
962 assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
963 "MF used frame lowering for wrong subtarget");
964 MachineBasicBlock::iterator MBBI = MBB.begin();
965 MachineFrameInfo &MFI = MF.getFrameInfo();
966 const Function &Fn = MF.getFunction();
967 MachineModuleInfo &MMI = MF.getMMI();
968 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
969 uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
970 uint64_t StackSize = MFI.getStackSize(); // Number of bytes to allocate.
971 bool IsFunclet = MBB.isEHFuncletEntry();
972 EHPersonality Personality = EHPersonality::Unknown;
973 if (Fn.hasPersonalityFn())
974 Personality = classifyEHPersonality(Fn.getPersonalityFn());
975 bool FnHasClrFunclet =
976 MF.hasEHFunclets() && Personality == EHPersonality::CoreCLR;
977 bool IsClrFunclet = IsFunclet && FnHasClrFunclet;
978 bool HasFP = hasFP(MF);
979 bool IsWin64CC = STI.isCallingConvWin64(Fn.getCallingConv());
980 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
981 bool NeedsWin64CFI = IsWin64Prologue && Fn.needsUnwindTableEntry();
982 // FIXME: Emit FPO data for EH funclets.
984 !IsFunclet && STI.isTargetWin32() && MMI.getModule()->getCodeViewFlag();
985 bool NeedsWinCFI = NeedsWin64CFI || NeedsWinFPO;
987 !IsWin64Prologue && (MMI.hasDebugInfo() || Fn.needsUnwindTableEntry());
988 unsigned FramePtr = TRI->getFrameRegister(MF);
989 const unsigned MachineFramePtr =
990 STI.isTarget64BitILP32()
991 ? getX86SubSuperRegister(FramePtr, 64) : FramePtr;
992 unsigned BasePtr = TRI->getBaseRegister();
993 bool HasWinCFI = false;
995 // Debug location must be unknown since the first debug location is used
996 // to determine the end of the prologue.
999 // Add RETADDR move area to callee saved frame size.
1000 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1001 if (TailCallReturnAddrDelta && IsWin64Prologue)
1002 report_fatal_error("Can't handle guaranteed tail call under win64 yet");
1004 if (TailCallReturnAddrDelta < 0)
1005 X86FI->setCalleeSavedFrameSize(
1006 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
1008 bool UseStackProbe = !STI.getTargetLowering()->getStackProbeSymbolName(MF).empty();
1010 // The default stack probe size is 4096 if the function has no stackprobesize
1012 unsigned StackProbeSize = 4096;
1013 if (Fn.hasFnAttribute("stack-probe-size"))
1014 Fn.getFnAttribute("stack-probe-size")
1016 .getAsInteger(0, StackProbeSize);
1018 // Re-align the stack on 64-bit if the x86-interrupt calling convention is
1019 // used and an error code was pushed, since the x86-64 ABI requires a 16-byte
1021 if (Fn.getCallingConv() == CallingConv::X86_INTR && Is64Bit &&
1022 Fn.arg_size() == 2) {
1024 MFI.setStackSize(StackSize);
1025 emitSPUpdate(MBB, MBBI, DL, -8, /*InEpilogue=*/false);
1028 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
1029 // function, and use up to 128 bytes of stack space, don't have a frame
1030 // pointer, calls, or dynamic alloca then we do not need to adjust the
1031 // stack pointer (we fit in the Red Zone). We also check that we don't
1032 // push and pop from the stack.
1033 if (Is64Bit && !Fn.hasFnAttribute(Attribute::NoRedZone) &&
1034 !TRI->needsStackRealignment(MF) &&
1035 !MFI.hasVarSizedObjects() && // No dynamic alloca.
1036 !MFI.adjustsStack() && // No calls.
1037 !UseStackProbe && // No stack probes.
1038 !IsWin64CC && // Win64 has no Red Zone
1039 !MFI.hasCopyImplyingStackAdjustment() && // Don't push and pop.
1040 !MF.shouldSplitStack()) { // Regular stack
1041 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
1042 if (HasFP) MinSize += SlotSize;
1043 X86FI->setUsesRedZone(MinSize > 0 || StackSize > 0);
1044 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
1045 MFI.setStackSize(StackSize);
1048 // Insert stack pointer adjustment for later moving of return addr. Only
1049 // applies to tail call optimized functions where the callee argument stack
1050 // size is bigger than the callers.
1051 if (TailCallReturnAddrDelta < 0) {
1052 BuildStackAdjustment(MBB, MBBI, DL, TailCallReturnAddrDelta,
1053 /*InEpilogue=*/false)
1054 .setMIFlag(MachineInstr::FrameSetup);
1057 // Mapping for machine moves:
1059 // DST: VirtualFP AND
1060 // SRC: VirtualFP => DW_CFA_def_cfa_offset
1061 // ELSE => DW_CFA_def_cfa
1063 // SRC: VirtualFP AND
1064 // DST: Register => DW_CFA_def_cfa_register
1067 // OFFSET < 0 => DW_CFA_offset_extended_sf
1068 // REG < 64 => DW_CFA_offset + Reg
1069 // ELSE => DW_CFA_offset_extended
1071 uint64_t NumBytes = 0;
1072 int stackGrowth = -SlotSize;
1074 // Find the funclet establisher parameter
1075 unsigned Establisher = X86::NoRegister;
1077 Establisher = Uses64BitFramePtr ? X86::RCX : X86::ECX;
1079 Establisher = Uses64BitFramePtr ? X86::RDX : X86::EDX;
1081 if (IsWin64Prologue && IsFunclet && !IsClrFunclet) {
1082 // Immediately spill establisher into the home slot.
1083 // The runtime cares about this.
1084 // MOV64mr %rdx, 16(%rsp)
1085 unsigned MOVmr = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1086 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MOVmr)), StackPtr, true, 16)
1087 .addReg(Establisher)
1088 .setMIFlag(MachineInstr::FrameSetup);
1089 MBB.addLiveIn(Establisher);
1093 assert(MF.getRegInfo().isReserved(MachineFramePtr) && "FP reserved");
1095 // Calculate required stack adjustment.
1096 uint64_t FrameSize = StackSize - SlotSize;
1097 // If required, include space for extra hidden slot for stashing base pointer.
1098 if (X86FI->getRestoreBasePointer())
1099 FrameSize += SlotSize;
1101 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
1103 // Callee-saved registers are pushed on stack before the stack is realigned.
1104 if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
1105 NumBytes = alignTo(NumBytes, MaxAlign);
1107 // Save EBP/RBP into the appropriate stack slot.
1108 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
1109 .addReg(MachineFramePtr, RegState::Kill)
1110 .setMIFlag(MachineInstr::FrameSetup);
1112 if (NeedsDwarfCFI) {
1113 // Mark the place where EBP/RBP was saved.
1114 // Define the current CFA rule to use the provided offset.
1116 BuildCFI(MBB, MBBI, DL,
1117 MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
1119 // Change the rule for the FramePtr to be an "offset" rule.
1120 unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
1121 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createOffset(
1122 nullptr, DwarfFramePtr, 2 * stackGrowth));
1127 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1129 .setMIFlag(MachineInstr::FrameSetup);
1132 if (!IsWin64Prologue && !IsFunclet) {
1133 // Update EBP with the new base value.
1134 BuildMI(MBB, MBBI, DL,
1135 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
1138 .setMIFlag(MachineInstr::FrameSetup);
1140 if (NeedsDwarfCFI) {
1141 // Mark effective beginning of when frame pointer becomes valid.
1142 // Define the current CFA to use the EBP/RBP register.
1143 unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
1144 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfaRegister(
1145 nullptr, DwarfFramePtr));
1149 // .cv_fpo_setframe $FramePtr
1151 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1154 .setMIFlag(MachineInstr::FrameSetup);
1158 assert(!IsFunclet && "funclets without FPs not yet implemented");
1159 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1162 // Update the offset adjustment, which is mainly used by codeview to translate
1163 // from ESP to VFRAME relative local variable offsets.
1165 if (HasFP && TRI->needsStackRealignment(MF))
1166 MFI.setOffsetAdjustment(-NumBytes);
1168 MFI.setOffsetAdjustment(-StackSize);
1171 // For EH funclets, only allocate enough space for outgoing calls. Save the
1172 // NumBytes value that we would've used for the parent frame.
1173 unsigned ParentFrameNumBytes = NumBytes;
1175 NumBytes = getWinEHFuncletFrameSize(MF);
1177 // Skip the callee-saved push instructions.
1178 bool PushedRegs = false;
1179 int StackOffset = 2 * stackGrowth;
1181 while (MBBI != MBB.end() &&
1182 MBBI->getFlag(MachineInstr::FrameSetup) &&
1183 (MBBI->getOpcode() == X86::PUSH32r ||
1184 MBBI->getOpcode() == X86::PUSH64r)) {
1186 unsigned Reg = MBBI->getOperand(0).getReg();
1189 if (!HasFP && NeedsDwarfCFI) {
1190 // Mark callee-saved push instruction.
1191 // Define the current CFA rule to use the provided offset.
1193 BuildCFI(MBB, MBBI, DL,
1194 MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
1195 StackOffset += stackGrowth;
1200 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1202 .setMIFlag(MachineInstr::FrameSetup);
1206 // Realign stack after we pushed callee-saved registers (so that we'll be
1207 // able to calculate their offsets from the frame pointer).
1208 // Don't do this for Win64, it needs to realign the stack after the prologue.
1209 if (!IsWin64Prologue && !IsFunclet && TRI->needsStackRealignment(MF)) {
1210 assert(HasFP && "There should be a frame pointer if stack is realigned.");
1211 BuildStackAlignAND(MBB, MBBI, DL, StackPtr, MaxAlign);
1215 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlign))
1217 .setMIFlag(MachineInstr::FrameSetup);
1221 // If there is an SUB32ri of ESP immediately before this instruction, merge
1222 // the two. This can be the case when tail call elimination is enabled and
1223 // the callee has more arguments then the caller.
1224 NumBytes -= mergeSPUpdates(MBB, MBBI, true);
1226 // Adjust stack pointer: ESP -= numbytes.
1228 // Windows and cygwin/mingw require a prologue helper routine when allocating
1229 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
1230 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
1231 // stack and adjust the stack pointer in one go. The 64-bit version of
1232 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
1233 // responsible for adjusting the stack pointer. Touching the stack at 4K
1234 // increments is necessary to ensure that the guard pages used by the OS
1235 // virtual memory manager are allocated in correct sequence.
1236 uint64_t AlignedNumBytes = NumBytes;
1237 if (IsWin64Prologue && !IsFunclet && TRI->needsStackRealignment(MF))
1238 AlignedNumBytes = alignTo(AlignedNumBytes, MaxAlign);
1239 if (AlignedNumBytes >= StackProbeSize && UseStackProbe) {
1240 assert(!X86FI->getUsesRedZone() &&
1241 "The Red Zone is not accounted for in stack probes");
1243 // Check whether EAX is livein for this block.
1244 bool isEAXAlive = isEAXLiveIn(MBB);
1249 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
1250 .addReg(X86::RAX, RegState::Kill)
1251 .setMIFlag(MachineInstr::FrameSetup);
1254 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1255 .addReg(X86::EAX, RegState::Kill)
1256 .setMIFlag(MachineInstr::FrameSetup);
1261 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
1262 // Function prologue is responsible for adjusting the stack pointer.
1263 int Alloc = isEAXAlive ? NumBytes - 8 : NumBytes;
1264 if (isUInt<32>(Alloc)) {
1265 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1267 .setMIFlag(MachineInstr::FrameSetup);
1268 } else if (isInt<32>(Alloc)) {
1269 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX)
1271 .setMIFlag(MachineInstr::FrameSetup);
1273 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
1275 .setMIFlag(MachineInstr::FrameSetup);
1278 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
1279 // We'll also use 4 already allocated bytes for EAX.
1280 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1281 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
1282 .setMIFlag(MachineInstr::FrameSetup);
1285 // Call __chkstk, __chkstk_ms, or __alloca.
1286 emitStackProbe(MF, MBB, MBBI, DL, true);
1292 MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV64rm), X86::RAX),
1293 StackPtr, false, NumBytes - 8);
1295 MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), X86::EAX),
1296 StackPtr, false, NumBytes - 4);
1297 MI->setFlag(MachineInstr::FrameSetup);
1298 MBB.insert(MBBI, MI);
1300 } else if (NumBytes) {
1301 emitSPUpdate(MBB, MBBI, DL, -(int64_t)NumBytes, /*InEpilogue=*/false);
1304 if (NeedsWinCFI && NumBytes) {
1306 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
1308 .setMIFlag(MachineInstr::FrameSetup);
1311 int SEHFrameOffset = 0;
1312 unsigned SPOrEstablisher;
1315 // The establisher parameter passed to a CLR funclet is actually a pointer
1316 // to the (mostly empty) frame of its nearest enclosing funclet; we have
1317 // to find the root function establisher frame by loading the PSPSym from
1318 // the intermediate frame.
1319 unsigned PSPSlotOffset = getPSPSlotOffsetFromSP(MF);
1320 MachinePointerInfo NoInfo;
1321 MBB.addLiveIn(Establisher);
1322 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), Establisher),
1323 Establisher, false, PSPSlotOffset)
1324 .addMemOperand(MF.getMachineMemOperand(
1325 NoInfo, MachineMemOperand::MOLoad, SlotSize, SlotSize));
1327 // Save the root establisher back into the current funclet's (mostly
1328 // empty) frame, in case a sub-funclet or the GC needs it.
1329 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr,
1330 false, PSPSlotOffset)
1331 .addReg(Establisher)
1333 MF.getMachineMemOperand(NoInfo, MachineMemOperand::MOStore |
1334 MachineMemOperand::MOVolatile,
1335 SlotSize, SlotSize));
1337 SPOrEstablisher = Establisher;
1339 SPOrEstablisher = StackPtr;
1342 if (IsWin64Prologue && HasFP) {
1343 // Set RBP to a small fixed offset from RSP. In the funclet case, we base
1344 // this calculation on the incoming establisher, which holds the value of
1345 // RSP from the parent frame at the end of the prologue.
1346 SEHFrameOffset = calculateSetFPREG(ParentFrameNumBytes);
1348 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
1349 SPOrEstablisher, false, SEHFrameOffset);
1351 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr)
1352 .addReg(SPOrEstablisher);
1354 // If this is not a funclet, emit the CFI describing our frame pointer.
1355 if (NeedsWinCFI && !IsFunclet) {
1356 assert(!NeedsWinFPO && "this setframe incompatible with FPO data");
1358 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1360 .addImm(SEHFrameOffset)
1361 .setMIFlag(MachineInstr::FrameSetup);
1362 if (isAsynchronousEHPersonality(Personality))
1363 MF.getWinEHFuncInfo()->SEHSetFrameOffset = SEHFrameOffset;
1365 } else if (IsFunclet && STI.is32Bit()) {
1366 // Reset EBP / ESI to something good for funclets.
1367 MBBI = restoreWin32EHStackPointers(MBB, MBBI, DL);
1368 // If we're a catch funclet, we can be returned to via catchret. Save ESP
1369 // into the registration node so that the runtime will restore it for us.
1370 if (!MBB.isCleanupFuncletEntry()) {
1371 assert(Personality == EHPersonality::MSVC_CXX);
1373 int FI = MF.getWinEHFuncInfo()->EHRegNodeFrameIndex;
1374 int64_t EHRegOffset = getFrameIndexReference(MF, FI, FrameReg);
1375 // ESP is the first field, so no extra displacement is needed.
1376 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32mr)), FrameReg,
1382 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
1383 const MachineInstr &FrameInstr = *MBBI;
1388 if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
1389 if (X86::FR64RegClass.contains(Reg)) {
1390 unsigned IgnoredFrameReg;
1391 int Offset = getFrameIndexReference(MF, FI, IgnoredFrameReg);
1392 Offset += SEHFrameOffset;
1395 assert(!NeedsWinFPO && "SEH_SaveXMM incompatible with FPO data");
1396 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
1399 .setMIFlag(MachineInstr::FrameSetup);
1405 if (NeedsWinCFI && HasWinCFI)
1406 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
1407 .setMIFlag(MachineInstr::FrameSetup);
1409 if (FnHasClrFunclet && !IsFunclet) {
1410 // Save the so-called Initial-SP (i.e. the value of the stack pointer
1411 // immediately after the prolog) into the PSPSlot so that funclets
1412 // and the GC can recover it.
1413 unsigned PSPSlotOffset = getPSPSlotOffsetFromSP(MF);
1414 auto PSPInfo = MachinePointerInfo::getFixedStack(
1415 MF, MF.getWinEHFuncInfo()->PSPSymFrameIdx);
1416 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr, false,
1419 .addMemOperand(MF.getMachineMemOperand(
1420 PSPInfo, MachineMemOperand::MOStore | MachineMemOperand::MOVolatile,
1421 SlotSize, SlotSize));
1424 // Realign stack after we spilled callee-saved registers (so that we'll be
1425 // able to calculate their offsets from the frame pointer).
1426 // Win64 requires aligning the stack after the prologue.
1427 if (IsWin64Prologue && TRI->needsStackRealignment(MF)) {
1428 assert(HasFP && "There should be a frame pointer if stack is realigned.");
1429 BuildStackAlignAND(MBB, MBBI, DL, SPOrEstablisher, MaxAlign);
1432 // We already dealt with stack realignment and funclets above.
1433 if (IsFunclet && STI.is32Bit())
1436 // If we need a base pointer, set it up here. It's whatever the value
1437 // of the stack pointer is at this point. Any variable size objects
1438 // will be allocated after this, so we can still use the base pointer
1439 // to reference locals.
1440 if (TRI->hasBasePointer(MF)) {
1441 // Update the base pointer with the current stack pointer.
1442 unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
1443 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
1444 .addReg(SPOrEstablisher)
1445 .setMIFlag(MachineInstr::FrameSetup);
1446 if (X86FI->getRestoreBasePointer()) {
1447 // Stash value of base pointer. Saving RSP instead of EBP shortens
1448 // dependence chain. Used by SjLj EH.
1449 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1450 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
1451 FramePtr, true, X86FI->getRestoreBasePointerOffset())
1452 .addReg(SPOrEstablisher)
1453 .setMIFlag(MachineInstr::FrameSetup);
1456 if (X86FI->getHasSEHFramePtrSave() && !IsFunclet) {
1457 // Stash the value of the frame pointer relative to the base pointer for
1458 // Win32 EH. This supports Win32 EH, which does the inverse of the above:
1459 // it recovers the frame pointer from the base pointer rather than the
1460 // other way around.
1461 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1464 getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg);
1465 assert(UsedReg == BasePtr);
1466 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), UsedReg, true, Offset)
1468 .setMIFlag(MachineInstr::FrameSetup);
1472 if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
1473 // Mark end of stack pointer adjustment.
1474 if (!HasFP && NumBytes) {
1475 // Define the current CFA rule to use the provided offset.
1477 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfaOffset(
1478 nullptr, -StackSize + stackGrowth));
1481 // Emit DWARF info specifying the offsets of the callee-saved registers.
1482 emitCalleeSavedFrameMoves(MBB, MBBI, DL);
1485 // X86 Interrupt handling function cannot assume anything about the direction
1486 // flag (DF in EFLAGS register). Clear this flag by creating "cld" instruction
1487 // in each prologue of interrupt handler function.
1489 // FIXME: Create "cld" instruction only in these cases:
1490 // 1. The interrupt handling function uses any of the "rep" instructions.
1491 // 2. Interrupt handling function calls another function.
1493 if (Fn.getCallingConv() == CallingConv::X86_INTR)
1494 BuildMI(MBB, MBBI, DL, TII.get(X86::CLD))
1495 .setMIFlag(MachineInstr::FrameSetup);
1497 // At this point we know if the function has WinCFI or not.
1498 MF.setHasWinCFI(HasWinCFI);
1501 bool X86FrameLowering::canUseLEAForSPInEpilogue(
1502 const MachineFunction &MF) const {
1503 // We can't use LEA instructions for adjusting the stack pointer if we don't
1504 // have a frame pointer in the Win64 ABI. Only ADD instructions may be used
1505 // to deallocate the stack.
1506 // This means that we can use LEA for SP in two situations:
1507 // 1. We *aren't* using the Win64 ABI which means we are free to use LEA.
1508 // 2. We *have* a frame pointer which means we are permitted to use LEA.
1509 return !MF.getTarget().getMCAsmInfo()->usesWindowsCFI() || hasFP(MF);
1512 static bool isFuncletReturnInstr(MachineInstr &MI) {
1513 switch (MI.getOpcode()) {
1515 case X86::CLEANUPRET:
1520 llvm_unreachable("impossible");
1523 // CLR funclets use a special "Previous Stack Pointer Symbol" slot on the
1524 // stack. It holds a pointer to the bottom of the root function frame. The
1525 // establisher frame pointer passed to a nested funclet may point to the
1526 // (mostly empty) frame of its parent funclet, but it will need to find
1527 // the frame of the root function to access locals. To facilitate this,
1528 // every funclet copies the pointer to the bottom of the root function
1529 // frame into a PSPSym slot in its own (mostly empty) stack frame. Using the
1530 // same offset for the PSPSym in the root function frame that's used in the
1531 // funclets' frames allows each funclet to dynamically accept any ancestor
1532 // frame as its establisher argument (the runtime doesn't guarantee the
1533 // immediate parent for some reason lost to history), and also allows the GC,
1534 // which uses the PSPSym for some bookkeeping, to find it in any funclet's
1535 // frame with only a single offset reported for the entire method.
1537 X86FrameLowering::getPSPSlotOffsetFromSP(const MachineFunction &MF) const {
1538 const WinEHFuncInfo &Info = *MF.getWinEHFuncInfo();
1540 int Offset = getFrameIndexReferencePreferSP(MF, Info.PSPSymFrameIdx, SPReg,
1541 /*IgnoreSPUpdates*/ true);
1542 assert(Offset >= 0 && SPReg == TRI->getStackRegister());
1543 return static_cast<unsigned>(Offset);
1547 X86FrameLowering::getWinEHFuncletFrameSize(const MachineFunction &MF) const {
1548 // This is the size of the pushed CSRs.
1550 MF.getInfo<X86MachineFunctionInfo>()->getCalleeSavedFrameSize();
1551 // This is the amount of stack a funclet needs to allocate.
1553 EHPersonality Personality =
1554 classifyEHPersonality(MF.getFunction().getPersonalityFn());
1555 if (Personality == EHPersonality::CoreCLR) {
1556 // CLR funclets need to hold enough space to include the PSPSym, at the
1557 // same offset from the stack pointer (immediately after the prolog) as it
1558 // resides at in the main function.
1559 UsedSize = getPSPSlotOffsetFromSP(MF) + SlotSize;
1561 // Other funclets just need enough stack for outgoing call arguments.
1562 UsedSize = MF.getFrameInfo().getMaxCallFrameSize();
1564 // RBP is not included in the callee saved register block. After pushing RBP,
1565 // everything is 16 byte aligned. Everything we allocate before an outgoing
1566 // call must also be 16 byte aligned.
1567 unsigned FrameSizeMinusRBP = alignTo(CSSize + UsedSize, getStackAlignment());
1568 // Subtract out the size of the callee saved registers. This is how much stack
1569 // each funclet will allocate.
1570 return FrameSizeMinusRBP - CSSize;
1573 static bool isTailCallOpcode(unsigned Opc) {
1574 return Opc == X86::TCRETURNri || Opc == X86::TCRETURNdi ||
1575 Opc == X86::TCRETURNmi ||
1576 Opc == X86::TCRETURNri64 || Opc == X86::TCRETURNdi64 ||
1577 Opc == X86::TCRETURNmi64;
1580 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
1581 MachineBasicBlock &MBB) const {
1582 const MachineFrameInfo &MFI = MF.getFrameInfo();
1583 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1584 MachineBasicBlock::iterator Terminator = MBB.getFirstTerminator();
1585 MachineBasicBlock::iterator MBBI = Terminator;
1587 if (MBBI != MBB.end())
1588 DL = MBBI->getDebugLoc();
1589 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
1590 const bool Is64BitILP32 = STI.isTarget64BitILP32();
1591 unsigned FramePtr = TRI->getFrameRegister(MF);
1592 unsigned MachineFramePtr =
1593 Is64BitILP32 ? getX86SubSuperRegister(FramePtr, 64) : FramePtr;
1595 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1596 bool NeedsWin64CFI =
1597 IsWin64Prologue && MF.getFunction().needsUnwindTableEntry();
1598 bool IsFunclet = MBBI == MBB.end() ? false : isFuncletReturnInstr(*MBBI);
1600 // Get the number of bytes to allocate from the FrameInfo.
1601 uint64_t StackSize = MFI.getStackSize();
1602 uint64_t MaxAlign = calculateMaxStackAlign(MF);
1603 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1604 bool HasFP = hasFP(MF);
1605 uint64_t NumBytes = 0;
1607 bool NeedsDwarfCFI =
1608 (!MF.getTarget().getTargetTriple().isOSDarwin() &&
1609 !MF.getTarget().getTargetTriple().isOSWindows()) &&
1610 (MF.getMMI().hasDebugInfo() || MF.getFunction().needsUnwindTableEntry());
1613 assert(HasFP && "EH funclets without FP not yet implemented");
1614 NumBytes = getWinEHFuncletFrameSize(MF);
1616 // Calculate required stack adjustment.
1617 uint64_t FrameSize = StackSize - SlotSize;
1618 NumBytes = FrameSize - CSSize;
1620 // Callee-saved registers were pushed on stack before the stack was
1622 if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
1623 NumBytes = alignTo(FrameSize, MaxAlign);
1625 NumBytes = StackSize - CSSize;
1627 uint64_t SEHStackAllocAmt = NumBytes;
1631 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),
1633 .setMIFlag(MachineInstr::FrameDestroy);
1634 if (NeedsDwarfCFI) {
1635 unsigned DwarfStackPtr =
1636 TRI->getDwarfRegNum(Is64Bit ? X86::RSP : X86::ESP, true);
1637 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfa(
1638 nullptr, DwarfStackPtr, -SlotSize));
1643 MachineBasicBlock::iterator FirstCSPop = MBBI;
1644 // Skip the callee-saved pop instructions.
1645 while (MBBI != MBB.begin()) {
1646 MachineBasicBlock::iterator PI = std::prev(MBBI);
1647 unsigned Opc = PI->getOpcode();
1649 if (Opc != X86::DBG_VALUE && !PI->isTerminator()) {
1650 if ((Opc != X86::POP32r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
1651 (Opc != X86::POP64r || !PI->getFlag(MachineInstr::FrameDestroy)))
1660 if (IsFunclet && Terminator->getOpcode() == X86::CATCHRET)
1661 emitCatchRetReturnValue(MBB, FirstCSPop, &*Terminator);
1663 if (MBBI != MBB.end())
1664 DL = MBBI->getDebugLoc();
1666 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1667 // instruction, merge the two instructions.
1668 if (NumBytes || MFI.hasVarSizedObjects())
1669 NumBytes += mergeSPUpdates(MBB, MBBI, true);
1671 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1672 // slot before popping them off! Same applies for the case, when stack was
1673 // realigned. Don't do this if this was a funclet epilogue, since the funclets
1674 // will not do realignment or dynamic stack allocation.
1675 if ((TRI->needsStackRealignment(MF) || MFI.hasVarSizedObjects()) &&
1677 if (TRI->needsStackRealignment(MF))
1679 unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);
1680 uint64_t LEAAmount =
1681 IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : -CSSize;
1683 // There are only two legal forms of epilogue:
1684 // - add SEHAllocationSize, %rsp
1685 // - lea SEHAllocationSize(%FramePtr), %rsp
1687 // 'mov %FramePtr, %rsp' will not be recognized as an epilogue sequence.
1688 // However, we may use this sequence if we have a frame pointer because the
1689 // effects of the prologue can safely be undone.
1690 if (LEAAmount != 0) {
1691 unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
1692 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1693 FramePtr, false, LEAAmount);
1696 unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
1697 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1701 } else if (NumBytes) {
1702 // Adjust stack pointer back: ESP += numbytes.
1703 emitSPUpdate(MBB, MBBI, DL, NumBytes, /*InEpilogue=*/true);
1704 if (!hasFP(MF) && NeedsDwarfCFI) {
1705 // Define the current CFA rule to use the provided offset.
1706 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfaOffset(
1707 nullptr, -CSSize - SlotSize));
1712 // Windows unwinder will not invoke function's exception handler if IP is
1713 // either in prologue or in epilogue. This behavior causes a problem when a
1714 // call immediately precedes an epilogue, because the return address points
1715 // into the epilogue. To cope with that, we insert an epilogue marker here,
1716 // then replace it with a 'nop' if it ends up immediately after a CALL in the
1717 // final emitted code.
1718 if (NeedsWin64CFI && MF.hasWinCFI())
1719 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
1721 if (!hasFP(MF) && NeedsDwarfCFI) {
1723 int64_t Offset = -CSSize - SlotSize;
1724 // Mark callee-saved pop instruction.
1725 // Define the current CFA rule to use the provided offset.
1726 while (MBBI != MBB.end()) {
1727 MachineBasicBlock::iterator PI = MBBI;
1728 unsigned Opc = PI->getOpcode();
1730 if (Opc == X86::POP32r || Opc == X86::POP64r) {
1732 BuildCFI(MBB, MBBI, DL,
1733 MCCFIInstruction::createDefCfaOffset(nullptr, Offset));
1738 if (Terminator == MBB.end() || !isTailCallOpcode(Terminator->getOpcode())) {
1739 // Add the return addr area delta back since we are not tail calling.
1740 int Offset = -1 * X86FI->getTCReturnAddrDelta();
1741 assert(Offset >= 0 && "TCDelta should never be positive");
1743 // Check for possible merge with preceding ADD instruction.
1744 Offset += mergeSPUpdates(MBB, Terminator, true);
1745 emitSPUpdate(MBB, Terminator, DL, Offset, /*InEpilogue=*/true);
1750 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1751 unsigned &FrameReg) const {
1752 const MachineFrameInfo &MFI = MF.getFrameInfo();
1754 bool IsFixed = MFI.isFixedObjectIndex(FI);
1755 // We can't calculate offset from frame pointer if the stack is realigned,
1756 // so enforce usage of stack/base pointer. The base pointer is used when we
1757 // have dynamic allocas in addition to dynamic realignment.
1758 if (TRI->hasBasePointer(MF))
1759 FrameReg = IsFixed ? TRI->getFramePtr() : TRI->getBaseRegister();
1760 else if (TRI->needsStackRealignment(MF))
1761 FrameReg = IsFixed ? TRI->getFramePtr() : TRI->getStackRegister();
1763 FrameReg = TRI->getFrameRegister(MF);
1765 // Offset will hold the offset from the stack pointer at function entry to the
1767 // We need to factor in additional offsets applied during the prologue to the
1768 // frame, base, and stack pointer depending on which is used.
1769 int Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea();
1770 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1771 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1772 uint64_t StackSize = MFI.getStackSize();
1773 bool HasFP = hasFP(MF);
1774 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1775 int64_t FPDelta = 0;
1777 if (IsWin64Prologue) {
1778 assert(!MFI.hasCalls() || (StackSize % 16) == 8);
1780 // Calculate required stack adjustment.
1781 uint64_t FrameSize = StackSize - SlotSize;
1782 // If required, include space for extra hidden slot for stashing base pointer.
1783 if (X86FI->getRestoreBasePointer())
1784 FrameSize += SlotSize;
1785 uint64_t NumBytes = FrameSize - CSSize;
1787 uint64_t SEHFrameOffset = calculateSetFPREG(NumBytes);
1788 if (FI && FI == X86FI->getFAIndex())
1789 return -SEHFrameOffset;
1791 // FPDelta is the offset from the "traditional" FP location of the old base
1792 // pointer followed by return address and the location required by the
1793 // restricted Win64 prologue.
1794 // Add FPDelta to all offsets below that go through the frame pointer.
1795 FPDelta = FrameSize - SEHFrameOffset;
1796 assert((!MFI.hasCalls() || (FPDelta % 16) == 0) &&
1797 "FPDelta isn't aligned per the Win64 ABI!");
1801 if (TRI->hasBasePointer(MF)) {
1802 assert(HasFP && "VLAs and dynamic stack realign, but no FP?!");
1804 // Skip the saved EBP.
1805 return Offset + SlotSize + FPDelta;
1807 assert((-(Offset + StackSize)) % MFI.getObjectAlignment(FI) == 0);
1808 return Offset + StackSize;
1810 } else if (TRI->needsStackRealignment(MF)) {
1812 // Skip the saved EBP.
1813 return Offset + SlotSize + FPDelta;
1815 assert((-(Offset + StackSize)) % MFI.getObjectAlignment(FI) == 0);
1816 return Offset + StackSize;
1818 // FIXME: Support tail calls
1821 return Offset + StackSize;
1823 // Skip the saved EBP.
1826 // Skip the RETADDR move area
1827 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1828 if (TailCallReturnAddrDelta < 0)
1829 Offset -= TailCallReturnAddrDelta;
1832 return Offset + FPDelta;
1835 int X86FrameLowering::getFrameIndexReferenceSP(const MachineFunction &MF,
1836 int FI, unsigned &FrameReg,
1837 int Adjustment) const {
1838 const MachineFrameInfo &MFI = MF.getFrameInfo();
1839 FrameReg = TRI->getStackRegister();
1840 return MFI.getObjectOffset(FI) - getOffsetOfLocalArea() + Adjustment;
1844 X86FrameLowering::getFrameIndexReferencePreferSP(const MachineFunction &MF,
1845 int FI, unsigned &FrameReg,
1846 bool IgnoreSPUpdates) const {
1848 const MachineFrameInfo &MFI = MF.getFrameInfo();
1849 // Does not include any dynamic realign.
1850 const uint64_t StackSize = MFI.getStackSize();
1851 // LLVM arranges the stack as follows:
1856 // PUSH RBP <-- RBP points here
1858 // ~~~~~~~ <-- possible stack realignment (non-win64)
1861 // ... <-- RSP after prologue points here
1862 // ~~~~~~~ <-- possible stack realignment (win64)
1864 // if (hasVarSizedObjects()):
1865 // ... <-- "base pointer" (ESI/RBX) points here
1867 // ... <-- RSP points here
1869 // Case 1: In the simple case of no stack realignment and no dynamic
1870 // allocas, both "fixed" stack objects (arguments and CSRs) are addressable
1871 // with fixed offsets from RSP.
1873 // Case 2: In the case of stack realignment with no dynamic allocas, fixed
1874 // stack objects are addressed with RBP and regular stack objects with RSP.
1876 // Case 3: In the case of dynamic allocas and stack realignment, RSP is used
1877 // to address stack arguments for outgoing calls and nothing else. The "base
1878 // pointer" points to local variables, and RBP points to fixed objects.
1880 // In cases 2 and 3, we can only answer for non-fixed stack objects, and the
1881 // answer we give is relative to the SP after the prologue, and not the
1882 // SP in the middle of the function.
1884 if (MFI.isFixedObjectIndex(FI) && TRI->needsStackRealignment(MF) &&
1885 !STI.isTargetWin64())
1886 return getFrameIndexReference(MF, FI, FrameReg);
1888 // If !hasReservedCallFrame the function might have SP adjustement in the
1889 // body. So, even though the offset is statically known, it depends on where
1890 // we are in the function.
1891 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
1892 if (!IgnoreSPUpdates && !TFI->hasReservedCallFrame(MF))
1893 return getFrameIndexReference(MF, FI, FrameReg);
1895 // We don't handle tail calls, and shouldn't be seeing them either.
1896 assert(MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta() >= 0 &&
1897 "we don't handle this case!");
1899 // This is how the math works out:
1901 // %rsp grows (i.e. gets lower) left to right. Each box below is
1902 // one word (eight bytes). Obj0 is the stack slot we're trying to
1905 // ----------------------------------
1906 // | BP | Obj0 | Obj1 | ... | ObjN |
1907 // ----------------------------------
1911 // A is the incoming stack pointer.
1912 // (B - A) is the local area offset (-8 for x86-64) [1]
1913 // (C - A) is the Offset returned by MFI.getObjectOffset for Obj0 [2]
1915 // |(E - B)| is the StackSize (absolute value, positive). For a
1916 // stack that grown down, this works out to be (B - E). [3]
1918 // E is also the value of %rsp after stack has been set up, and we
1919 // want (C - E) -- the value we can add to %rsp to get to Obj0. Now
1920 // (C - E) == (C - A) - (B - A) + (B - E)
1921 // { Using [1], [2] and [3] above }
1922 // == getObjectOffset - LocalAreaOffset + StackSize
1924 return getFrameIndexReferenceSP(MF, FI, FrameReg, StackSize);
1927 bool X86FrameLowering::assignCalleeSavedSpillSlots(
1928 MachineFunction &MF, const TargetRegisterInfo *TRI,
1929 std::vector<CalleeSavedInfo> &CSI) const {
1930 MachineFrameInfo &MFI = MF.getFrameInfo();
1931 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1933 unsigned CalleeSavedFrameSize = 0;
1934 int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1936 int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1938 if (TailCallReturnAddrDelta < 0) {
1939 // create RETURNADDR area
1948 MFI.CreateFixedObject(-TailCallReturnAddrDelta,
1949 TailCallReturnAddrDelta - SlotSize, true);
1952 // Spill the BasePtr if it's used.
1953 if (this->TRI->hasBasePointer(MF)) {
1954 // Allocate a spill slot for EBP if we have a base pointer and EH funclets.
1955 if (MF.hasEHFunclets()) {
1956 int FI = MFI.CreateSpillStackObject(SlotSize, SlotSize);
1957 X86FI->setHasSEHFramePtrSave(true);
1958 X86FI->setSEHFramePtrSaveIndex(FI);
1963 // emitPrologue always spills frame register the first thing.
1964 SpillSlotOffset -= SlotSize;
1965 MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1967 // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1968 // the frame register, we can delete it from CSI list and not have to worry
1969 // about avoiding it later.
1970 unsigned FPReg = TRI->getFrameRegister(MF);
1971 for (unsigned i = 0; i < CSI.size(); ++i) {
1972 if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
1973 CSI.erase(CSI.begin() + i);
1979 // Assign slots for GPRs. It increases frame size.
1980 for (unsigned i = CSI.size(); i != 0; --i) {
1981 unsigned Reg = CSI[i - 1].getReg();
1983 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1986 SpillSlotOffset -= SlotSize;
1987 CalleeSavedFrameSize += SlotSize;
1989 int SlotIndex = MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1990 CSI[i - 1].setFrameIdx(SlotIndex);
1993 X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
1994 MFI.setCVBytesOfCalleeSavedRegisters(CalleeSavedFrameSize);
1996 // Assign slots for XMMs.
1997 for (unsigned i = CSI.size(); i != 0; --i) {
1998 unsigned Reg = CSI[i - 1].getReg();
1999 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2002 // If this is k-register make sure we lookup via the largest legal type.
2003 MVT VT = MVT::Other;
2004 if (X86::VK16RegClass.contains(Reg))
2005 VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2007 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2008 unsigned Size = TRI->getSpillSize(*RC);
2009 unsigned Align = TRI->getSpillAlignment(*RC);
2011 SpillSlotOffset -= std::abs(SpillSlotOffset) % Align;
2013 SpillSlotOffset -= Size;
2014 int SlotIndex = MFI.CreateFixedSpillStackObject(Size, SpillSlotOffset);
2015 CSI[i - 1].setFrameIdx(SlotIndex);
2016 MFI.ensureMaxAlignment(Align);
2022 bool X86FrameLowering::spillCalleeSavedRegisters(
2023 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
2024 const std::vector<CalleeSavedInfo> &CSI,
2025 const TargetRegisterInfo *TRI) const {
2026 DebugLoc DL = MBB.findDebugLoc(MI);
2028 // Don't save CSRs in 32-bit EH funclets. The caller saves EBX, EBP, ESI, EDI
2029 // for us, and there are no XMM CSRs on Win32.
2030 if (MBB.isEHFuncletEntry() && STI.is32Bit() && STI.isOSWindows())
2033 // Push GPRs. It increases frame size.
2034 const MachineFunction &MF = *MBB.getParent();
2035 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
2036 for (unsigned i = CSI.size(); i != 0; --i) {
2037 unsigned Reg = CSI[i - 1].getReg();
2039 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
2042 const MachineRegisterInfo &MRI = MF.getRegInfo();
2043 bool isLiveIn = MRI.isLiveIn(Reg);
2047 // Decide whether we can add a kill flag to the use.
2048 bool CanKill = !isLiveIn;
2049 // Check if any subregister is live-in
2051 for (MCRegAliasIterator AReg(Reg, TRI, false); AReg.isValid(); ++AReg) {
2052 if (MRI.isLiveIn(*AReg)) {
2059 // Do not set a kill flag on values that are also marked as live-in. This
2060 // happens with the @llvm-returnaddress intrinsic and with arguments
2061 // passed in callee saved registers.
2062 // Omitting the kill flags is conservatively correct even if the live-in
2063 // is not used after all.
2064 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, getKillRegState(CanKill))
2065 .setMIFlag(MachineInstr::FrameSetup);
2068 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
2069 // It can be done by spilling XMMs to stack frame.
2070 for (unsigned i = CSI.size(); i != 0; --i) {
2071 unsigned Reg = CSI[i-1].getReg();
2072 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2075 // If this is k-register make sure we lookup via the largest legal type.
2076 MVT VT = MVT::Other;
2077 if (X86::VK16RegClass.contains(Reg))
2078 VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2080 // Add the callee-saved register as live-in. It's killed at the spill.
2082 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2084 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
2087 MI->setFlag(MachineInstr::FrameSetup);
2094 void X86FrameLowering::emitCatchRetReturnValue(MachineBasicBlock &MBB,
2095 MachineBasicBlock::iterator MBBI,
2096 MachineInstr *CatchRet) const {
2097 // SEH shouldn't use catchret.
2098 assert(!isAsynchronousEHPersonality(classifyEHPersonality(
2099 MBB.getParent()->getFunction().getPersonalityFn())) &&
2100 "SEH should not use CATCHRET");
2101 DebugLoc DL = CatchRet->getDebugLoc();
2102 MachineBasicBlock *CatchRetTarget = CatchRet->getOperand(0).getMBB();
2104 // Fill EAX/RAX with the address of the target block.
2105 if (STI.is64Bit()) {
2106 // LEA64r CatchRetTarget(%rip), %rax
2107 BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), X86::RAX)
2111 .addMBB(CatchRetTarget)
2114 // MOV32ri $CatchRetTarget, %eax
2115 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
2116 .addMBB(CatchRetTarget);
2119 // Record that we've taken the address of CatchRetTarget and no longer just
2120 // reference it in a terminator.
2121 CatchRetTarget->setHasAddressTaken();
2124 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2125 MachineBasicBlock::iterator MI,
2126 std::vector<CalleeSavedInfo> &CSI,
2127 const TargetRegisterInfo *TRI) const {
2131 if (MI != MBB.end() && isFuncletReturnInstr(*MI) && STI.isOSWindows()) {
2132 // Don't restore CSRs in 32-bit EH funclets. Matches
2133 // spillCalleeSavedRegisters.
2136 // Don't restore CSRs before an SEH catchret. SEH except blocks do not form
2137 // funclets. emitEpilogue transforms these to normal jumps.
2138 if (MI->getOpcode() == X86::CATCHRET) {
2139 const Function &F = MBB.getParent()->getFunction();
2140 bool IsSEH = isAsynchronousEHPersonality(
2141 classifyEHPersonality(F.getPersonalityFn()));
2147 DebugLoc DL = MBB.findDebugLoc(MI);
2149 // Reload XMMs from stack frame.
2150 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2151 unsigned Reg = CSI[i].getReg();
2152 if (X86::GR64RegClass.contains(Reg) ||
2153 X86::GR32RegClass.contains(Reg))
2156 // If this is k-register make sure we lookup via the largest legal type.
2157 MVT VT = MVT::Other;
2158 if (X86::VK16RegClass.contains(Reg))
2159 VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2161 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2162 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
2166 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
2167 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2168 unsigned Reg = CSI[i].getReg();
2169 if (!X86::GR64RegClass.contains(Reg) &&
2170 !X86::GR32RegClass.contains(Reg))
2173 BuildMI(MBB, MI, DL, TII.get(Opc), Reg)
2174 .setMIFlag(MachineInstr::FrameDestroy);
2179 void X86FrameLowering::determineCalleeSaves(MachineFunction &MF,
2180 BitVector &SavedRegs,
2181 RegScavenger *RS) const {
2182 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
2184 // Spill the BasePtr if it's used.
2185 if (TRI->hasBasePointer(MF)){
2186 unsigned BasePtr = TRI->getBaseRegister();
2187 if (STI.isTarget64BitILP32())
2188 BasePtr = getX86SubSuperRegister(BasePtr, 64);
2189 SavedRegs.set(BasePtr);
2194 HasNestArgument(const MachineFunction *MF) {
2195 const Function &F = MF->getFunction();
2196 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
2198 if (I->hasNestAttr())
2204 /// GetScratchRegister - Get a temp register for performing work in the
2205 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
2206 /// and the properties of the function either one or two registers will be
2207 /// needed. Set primary to true for the first register, false for the second.
2209 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
2210 CallingConv::ID CallingConvention = MF.getFunction().getCallingConv();
2213 if (CallingConvention == CallingConv::HiPE) {
2215 return Primary ? X86::R14 : X86::R13;
2217 return Primary ? X86::EBX : X86::EDI;
2222 return Primary ? X86::R11 : X86::R12;
2224 return Primary ? X86::R11D : X86::R12D;
2227 bool IsNested = HasNestArgument(&MF);
2229 if (CallingConvention == CallingConv::X86_FastCall ||
2230 CallingConvention == CallingConv::Fast) {
2232 report_fatal_error("Segmented stacks does not support fastcall with "
2233 "nested function.");
2234 return Primary ? X86::EAX : X86::ECX;
2237 return Primary ? X86::EDX : X86::EAX;
2238 return Primary ? X86::ECX : X86::EAX;
2241 // The stack limit in the TCB is set to this many bytes above the actual stack
2243 static const uint64_t kSplitStackAvailable = 256;
2245 void X86FrameLowering::adjustForSegmentedStacks(
2246 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
2247 MachineFrameInfo &MFI = MF.getFrameInfo();
2249 unsigned TlsReg, TlsOffset;
2252 // To support shrink-wrapping we would need to insert the new blocks
2253 // at the right place and update the branches to PrologueMBB.
2254 assert(&(*MF.begin()) == &PrologueMBB && "Shrink-wrapping not supported yet");
2256 unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2257 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
2258 "Scratch register is live-in");
2260 if (MF.getFunction().isVarArg())
2261 report_fatal_error("Segmented stacks do not support vararg functions.");
2262 if (!STI.isTargetLinux() && !STI.isTargetDarwin() && !STI.isTargetWin32() &&
2263 !STI.isTargetWin64() && !STI.isTargetFreeBSD() &&
2264 !STI.isTargetDragonFly())
2265 report_fatal_error("Segmented stacks not supported on this platform.");
2267 // Eventually StackSize will be calculated by a link-time pass; which will
2268 // also decide whether checking code needs to be injected into this particular
2270 StackSize = MFI.getStackSize();
2272 // Do not generate a prologue for leaf functions with a stack of size zero.
2273 // For non-leaf functions we have to allow for the possibility that the
2274 // callis to a non-split function, as in PR37807. This function could also
2275 // take the address of a non-split function. When the linker tries to adjust
2276 // its non-existent prologue, it would fail with an error. Mark the object
2277 // file so that such failures are not errors. See this Go language bug-report
2278 // https://go-review.googlesource.com/c/go/+/148819/
2279 if (StackSize == 0 && !MFI.hasTailCall()) {
2280 MF.getMMI().setHasNosplitStack(true);
2284 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
2285 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
2286 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2287 bool IsNested = false;
2289 // We need to know if the function has a nest argument only in 64 bit mode.
2291 IsNested = HasNestArgument(&MF);
2293 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
2294 // allocMBB needs to be last (terminating) instruction.
2296 for (const auto &LI : PrologueMBB.liveins()) {
2297 allocMBB->addLiveIn(LI);
2298 checkMBB->addLiveIn(LI);
2302 allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
2304 MF.push_front(allocMBB);
2305 MF.push_front(checkMBB);
2307 // When the frame size is less than 256 we just compare the stack
2308 // boundary directly to the value of the stack pointer, per gcc.
2309 bool CompareStackPointer = StackSize < kSplitStackAvailable;
2311 // Read the limit off the current stacklet off the stack_guard location.
2313 if (STI.isTargetLinux()) {
2315 TlsOffset = IsLP64 ? 0x70 : 0x40;
2316 } else if (STI.isTargetDarwin()) {
2318 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
2319 } else if (STI.isTargetWin64()) {
2321 TlsOffset = 0x28; // pvArbitrary, reserved for application use
2322 } else if (STI.isTargetFreeBSD()) {
2325 } else if (STI.isTargetDragonFly()) {
2327 TlsOffset = 0x20; // use tls_tcb.tcb_segstack
2329 report_fatal_error("Segmented stacks not supported on this platform.");
2332 if (CompareStackPointer)
2333 ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
2335 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
2336 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2338 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
2339 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2341 if (STI.isTargetLinux()) {
2344 } else if (STI.isTargetDarwin()) {
2346 TlsOffset = 0x48 + 90*4;
2347 } else if (STI.isTargetWin32()) {
2349 TlsOffset = 0x14; // pvArbitrary, reserved for application use
2350 } else if (STI.isTargetDragonFly()) {
2352 TlsOffset = 0x10; // use tls_tcb.tcb_segstack
2353 } else if (STI.isTargetFreeBSD()) {
2354 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
2356 report_fatal_error("Segmented stacks not supported on this platform.");
2359 if (CompareStackPointer)
2360 ScratchReg = X86::ESP;
2362 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
2363 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2365 if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
2366 STI.isTargetDragonFly()) {
2367 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
2368 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2369 } else if (STI.isTargetDarwin()) {
2371 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
2372 unsigned ScratchReg2;
2374 if (CompareStackPointer) {
2375 // The primary scratch register is available for holding the TLS offset.
2376 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2377 SaveScratch2 = false;
2379 // Need to use a second register to hold the TLS offset
2380 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
2382 // Unfortunately, with fastcc the second scratch register may hold an
2384 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
2387 // If Scratch2 is live-in then it needs to be saved.
2388 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
2389 "Scratch register is live-in and not saved");
2392 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
2393 .addReg(ScratchReg2, RegState::Kill);
2395 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
2397 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
2399 .addReg(ScratchReg2).addImm(1).addReg(0)
2404 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
2408 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
2409 // It jumps to normal execution of the function body.
2410 BuildMI(checkMBB, DL, TII.get(X86::JA_1)).addMBB(&PrologueMBB);
2412 // On 32 bit we first push the arguments size and then the frame size. On 64
2413 // bit, we pass the stack frame size in r10 and the argument size in r11.
2415 // Functions with nested arguments use R10, so it needs to be saved across
2416 // the call to _morestack
2418 const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
2419 const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
2420 const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
2421 const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
2422 const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
2425 BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
2427 BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
2429 BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
2430 .addImm(X86FI->getArgumentStackSize());
2432 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2433 .addImm(X86FI->getArgumentStackSize());
2434 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2438 // __morestack is in libgcc
2439 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
2440 // Under the large code model, we cannot assume that __morestack lives
2441 // within 2^31 bytes of the call site, so we cannot use pc-relative
2442 // addressing. We cannot perform the call via a temporary register,
2443 // as the rax register may be used to store the static chain, and all
2444 // other suitable registers may be either callee-save or used for
2445 // parameter passing. We cannot use the stack at this point either
2446 // because __morestack manipulates the stack directly.
2448 // To avoid these issues, perform an indirect call via a read-only memory
2449 // location containing the address.
2451 // This solution is not perfect, as it assumes that the .rodata section
2452 // is laid out within 2^31 bytes of each function body, but this seems
2453 // to be sufficient for JIT.
2454 // FIXME: Add retpoline support and remove the error here..
2455 if (STI.useRetpolineIndirectCalls())
2456 report_fatal_error("Emitting morestack calls on 64-bit with the large "
2457 "code model and retpoline not yet implemented.");
2458 BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
2462 .addExternalSymbol("__morestack_addr")
2464 MF.getMMI().setUsesMorestackAddr(true);
2467 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
2468 .addExternalSymbol("__morestack");
2470 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
2471 .addExternalSymbol("__morestack");
2475 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
2477 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
2479 allocMBB->addSuccessor(&PrologueMBB);
2481 checkMBB->addSuccessor(allocMBB, BranchProbability::getZero());
2482 checkMBB->addSuccessor(&PrologueMBB, BranchProbability::getOne());
2484 #ifdef EXPENSIVE_CHECKS
2489 /// Lookup an ERTS parameter in the !hipe.literals named metadata node.
2490 /// HiPE provides Erlang Runtime System-internal parameters, such as PCB offsets
2491 /// to fields it needs, through a named metadata node "hipe.literals" containing
2492 /// name-value pairs.
2493 static unsigned getHiPELiteral(
2494 NamedMDNode *HiPELiteralsMD, const StringRef LiteralName) {
2495 for (int i = 0, e = HiPELiteralsMD->getNumOperands(); i != e; ++i) {
2496 MDNode *Node = HiPELiteralsMD->getOperand(i);
2497 if (Node->getNumOperands() != 2) continue;
2498 MDString *NodeName = dyn_cast<MDString>(Node->getOperand(0));
2499 ValueAsMetadata *NodeVal = dyn_cast<ValueAsMetadata>(Node->getOperand(1));
2500 if (!NodeName || !NodeVal) continue;
2501 ConstantInt *ValConst = dyn_cast_or_null<ConstantInt>(NodeVal->getValue());
2502 if (ValConst && NodeName->getString() == LiteralName) {
2503 return ValConst->getZExtValue();
2507 report_fatal_error("HiPE literal " + LiteralName
2508 + " required but not provided");
2511 /// Erlang programs may need a special prologue to handle the stack size they
2512 /// might need at runtime. That is because Erlang/OTP does not implement a C
2513 /// stack but uses a custom implementation of hybrid stack/heap architecture.
2514 /// (for more information see Eric Stenman's Ph.D. thesis:
2515 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
2518 /// temp0 = sp - MaxStack
2519 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
2523 /// call inc_stack # doubles the stack space
2524 /// temp0 = sp - MaxStack
2525 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
2526 void X86FrameLowering::adjustForHiPEPrologue(
2527 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
2528 MachineFrameInfo &MFI = MF.getFrameInfo();
2531 // To support shrink-wrapping we would need to insert the new blocks
2532 // at the right place and update the branches to PrologueMBB.
2533 assert(&(*MF.begin()) == &PrologueMBB && "Shrink-wrapping not supported yet");
2535 // HiPE-specific values
2536 NamedMDNode *HiPELiteralsMD = MF.getMMI().getModule()
2537 ->getNamedMetadata("hipe.literals");
2538 if (!HiPELiteralsMD)
2540 "Can't generate HiPE prologue without runtime parameters");
2541 const unsigned HipeLeafWords
2542 = getHiPELiteral(HiPELiteralsMD,
2543 Is64Bit ? "AMD64_LEAF_WORDS" : "X86_LEAF_WORDS");
2544 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
2545 const unsigned Guaranteed = HipeLeafWords * SlotSize;
2546 unsigned CallerStkArity = MF.getFunction().arg_size() > CCRegisteredArgs ?
2547 MF.getFunction().arg_size() - CCRegisteredArgs : 0;
2548 unsigned MaxStack = MFI.getStackSize() + CallerStkArity*SlotSize + SlotSize;
2550 assert(STI.isTargetLinux() &&
2551 "HiPE prologue is only supported on Linux operating systems.");
2553 // Compute the largest caller's frame that is needed to fit the callees'
2554 // frames. This 'MaxStack' is computed from:
2556 // a) the fixed frame size, which is the space needed for all spilled temps,
2557 // b) outgoing on-stack parameter areas, and
2558 // c) the minimum stack space this function needs to make available for the
2559 // functions it calls (a tunable ABI property).
2560 if (MFI.hasCalls()) {
2561 unsigned MoreStackForCalls = 0;
2563 for (auto &MBB : MF) {
2564 for (auto &MI : MBB) {
2568 // Get callee operand.
2569 const MachineOperand &MO = MI.getOperand(0);
2571 // Only take account of global function calls (no closures etc.).
2575 const Function *F = dyn_cast<Function>(MO.getGlobal());
2579 // Do not update 'MaxStack' for primitive and built-in functions
2580 // (encoded with names either starting with "erlang."/"bif_" or not
2581 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
2582 // "_", such as the BIF "suspend_0") as they are executed on another
2584 if (F->getName().find("erlang.") != StringRef::npos ||
2585 F->getName().find("bif_") != StringRef::npos ||
2586 F->getName().find_first_of("._") == StringRef::npos)
2589 unsigned CalleeStkArity =
2590 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
2591 if (HipeLeafWords - 1 > CalleeStkArity)
2592 MoreStackForCalls = std::max(MoreStackForCalls,
2593 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
2596 MaxStack += MoreStackForCalls;
2599 // If the stack frame needed is larger than the guaranteed then runtime checks
2600 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
2601 if (MaxStack > Guaranteed) {
2602 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
2603 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
2605 for (const auto &LI : PrologueMBB.liveins()) {
2606 stackCheckMBB->addLiveIn(LI);
2607 incStackMBB->addLiveIn(LI);
2610 MF.push_front(incStackMBB);
2611 MF.push_front(stackCheckMBB);
2613 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
2614 unsigned LEAop, CMPop, CALLop;
2615 SPLimitOffset = getHiPELiteral(HiPELiteralsMD, "P_NSP_LIMIT");
2619 LEAop = X86::LEA64r;
2620 CMPop = X86::CMP64rm;
2621 CALLop = X86::CALL64pcrel32;
2625 LEAop = X86::LEA32r;
2626 CMPop = X86::CMP32rm;
2627 CALLop = X86::CALLpcrel32;
2630 ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2631 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
2632 "HiPE prologue scratch register is live-in");
2634 // Create new MBB for StackCheck:
2635 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
2636 SPReg, false, -MaxStack);
2637 // SPLimitOffset is in a fixed heap location (pointed by BP).
2638 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
2639 .addReg(ScratchReg), PReg, false, SPLimitOffset);
2640 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_1)).addMBB(&PrologueMBB);
2642 // Create new MBB for IncStack:
2643 BuildMI(incStackMBB, DL, TII.get(CALLop)).
2644 addExternalSymbol("inc_stack_0");
2645 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
2646 SPReg, false, -MaxStack);
2647 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
2648 .addReg(ScratchReg), PReg, false, SPLimitOffset);
2649 BuildMI(incStackMBB, DL, TII.get(X86::JLE_1)).addMBB(incStackMBB);
2651 stackCheckMBB->addSuccessor(&PrologueMBB, {99, 100});
2652 stackCheckMBB->addSuccessor(incStackMBB, {1, 100});
2653 incStackMBB->addSuccessor(&PrologueMBB, {99, 100});
2654 incStackMBB->addSuccessor(incStackMBB, {1, 100});
2656 #ifdef EXPENSIVE_CHECKS
2661 bool X86FrameLowering::adjustStackWithPops(MachineBasicBlock &MBB,
2662 MachineBasicBlock::iterator MBBI,
2669 if (Offset % SlotSize)
2672 int NumPops = Offset / SlotSize;
2673 // This is only worth it if we have at most 2 pops.
2674 if (NumPops != 1 && NumPops != 2)
2677 // Handle only the trivial case where the adjustment directly follows
2678 // a call. This is the most common one, anyway.
2679 if (MBBI == MBB.begin())
2681 MachineBasicBlock::iterator Prev = std::prev(MBBI);
2682 if (!Prev->isCall() || !Prev->getOperand(1).isRegMask())
2686 unsigned FoundRegs = 0;
2688 auto &MRI = MBB.getParent()->getRegInfo();
2689 auto RegMask = Prev->getOperand(1);
2692 Is64Bit ? X86::GR64_NOREX_NOSPRegClass : X86::GR32_NOREX_NOSPRegClass;
2693 // Try to find up to NumPops free registers.
2694 for (auto Candidate : RegClass) {
2696 // Poor man's liveness:
2697 // Since we're immediately after a call, any register that is clobbered
2698 // by the call and not defined by it can be considered dead.
2699 if (!RegMask.clobbersPhysReg(Candidate))
2702 // Don't clobber reserved registers
2703 if (MRI.isReserved(Candidate))
2707 for (const MachineOperand &MO : Prev->implicit_operands()) {
2708 if (MO.isReg() && MO.isDef() &&
2709 TRI->isSuperOrSubRegisterEq(MO.getReg(), Candidate)) {
2718 Regs[FoundRegs++] = Candidate;
2719 if (FoundRegs == (unsigned)NumPops)
2726 // If we found only one free register, but need two, reuse the same one twice.
2727 while (FoundRegs < (unsigned)NumPops)
2728 Regs[FoundRegs++] = Regs[0];
2730 for (int i = 0; i < NumPops; ++i)
2731 BuildMI(MBB, MBBI, DL,
2732 TII.get(STI.is64Bit() ? X86::POP64r : X86::POP32r), Regs[i]);
2737 MachineBasicBlock::iterator X86FrameLowering::
2738 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
2739 MachineBasicBlock::iterator I) const {
2740 bool reserveCallFrame = hasReservedCallFrame(MF);
2741 unsigned Opcode = I->getOpcode();
2742 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
2743 DebugLoc DL = I->getDebugLoc();
2744 uint64_t Amount = !reserveCallFrame ? TII.getFrameSize(*I) : 0;
2745 uint64_t InternalAmt = (isDestroy || Amount) ? TII.getFrameAdjustment(*I) : 0;
2747 auto InsertPos = skipDebugInstructionsForward(I, MBB.end());
2749 if (!reserveCallFrame) {
2750 // If the stack pointer can be changed after prologue, turn the
2751 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
2752 // adjcallstackdown instruction into 'add ESP, <amt>'
2754 // We need to keep the stack aligned properly. To do this, we round the
2755 // amount of space needed for the outgoing arguments up to the next
2756 // alignment boundary.
2757 unsigned StackAlign = getStackAlignment();
2758 Amount = alignTo(Amount, StackAlign);
2760 MachineModuleInfo &MMI = MF.getMMI();
2761 const Function &F = MF.getFunction();
2762 bool WindowsCFI = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
2763 bool DwarfCFI = !WindowsCFI &&
2764 (MMI.hasDebugInfo() || F.needsUnwindTableEntry());
2766 // If we have any exception handlers in this function, and we adjust
2767 // the SP before calls, we may need to indicate this to the unwinder
2768 // using GNU_ARGS_SIZE. Note that this may be necessary even when
2769 // Amount == 0, because the preceding function may have set a non-0
2771 // TODO: We don't need to reset this between subsequent functions,
2772 // if it didn't change.
2773 bool HasDwarfEHHandlers = !WindowsCFI && !MF.getLandingPads().empty();
2775 if (HasDwarfEHHandlers && !isDestroy &&
2776 MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences())
2777 BuildCFI(MBB, InsertPos, DL,
2778 MCCFIInstruction::createGnuArgsSize(nullptr, Amount));
2783 // Factor out the amount that gets handled inside the sequence
2784 // (Pushes of argument for frame setup, callee pops for frame destroy)
2785 Amount -= InternalAmt;
2787 // TODO: This is needed only if we require precise CFA.
2788 // If this is a callee-pop calling convention, emit a CFA adjust for
2789 // the amount the callee popped.
2790 if (isDestroy && InternalAmt && DwarfCFI && !hasFP(MF))
2791 BuildCFI(MBB, InsertPos, DL,
2792 MCCFIInstruction::createAdjustCfaOffset(nullptr, -InternalAmt));
2794 // Add Amount to SP to destroy a frame, or subtract to setup.
2795 int64_t StackAdjustment = isDestroy ? Amount : -Amount;
2797 if (StackAdjustment) {
2798 // Merge with any previous or following adjustment instruction. Note: the
2799 // instructions merged with here do not have CFI, so their stack
2800 // adjustments do not feed into CfaAdjustment.
2801 StackAdjustment += mergeSPUpdates(MBB, InsertPos, true);
2802 StackAdjustment += mergeSPUpdates(MBB, InsertPos, false);
2804 if (StackAdjustment) {
2805 if (!(F.optForMinSize() &&
2806 adjustStackWithPops(MBB, InsertPos, DL, StackAdjustment)))
2807 BuildStackAdjustment(MBB, InsertPos, DL, StackAdjustment,
2808 /*InEpilogue=*/false);
2812 if (DwarfCFI && !hasFP(MF)) {
2813 // If we don't have FP, but need to generate unwind information,
2814 // we need to set the correct CFA offset after the stack adjustment.
2815 // How much we adjust the CFA offset depends on whether we're emitting
2816 // CFI only for EH purposes or for debugging. EH only requires the CFA
2817 // offset to be correct at each call site, while for debugging we want
2818 // it to be more precise.
2820 int64_t CfaAdjustment = -StackAdjustment;
2821 // TODO: When not using precise CFA, we also need to adjust for the
2822 // InternalAmt here.
2823 if (CfaAdjustment) {
2824 BuildCFI(MBB, InsertPos, DL,
2825 MCCFIInstruction::createAdjustCfaOffset(nullptr,
2833 if (isDestroy && InternalAmt) {
2834 // If we are performing frame pointer elimination and if the callee pops
2835 // something off the stack pointer, add it back. We do this until we have
2836 // more advanced stack pointer tracking ability.
2837 // We are not tracking the stack pointer adjustment by the callee, so make
2838 // sure we restore the stack pointer immediately after the call, there may
2839 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
2840 MachineBasicBlock::iterator CI = I;
2841 MachineBasicBlock::iterator B = MBB.begin();
2842 while (CI != B && !std::prev(CI)->isCall())
2844 BuildStackAdjustment(MBB, CI, DL, -InternalAmt, /*InEpilogue=*/false);
2850 bool X86FrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const {
2851 assert(MBB.getParent() && "Block is not attached to a function!");
2852 const MachineFunction &MF = *MBB.getParent();
2853 return !TRI->needsStackRealignment(MF) || !MBB.isLiveIn(X86::EFLAGS);
2856 bool X86FrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
2857 assert(MBB.getParent() && "Block is not attached to a function!");
2859 // Win64 has strict requirements in terms of epilogue and we are
2860 // not taking a chance at messing with them.
2861 // I.e., unless this block is already an exit block, we can't use
2862 // it as an epilogue.
2863 if (STI.isTargetWin64() && !MBB.succ_empty() && !MBB.isReturnBlock())
2866 if (canUseLEAForSPInEpilogue(*MBB.getParent()))
2869 // If we cannot use LEA to adjust SP, we may need to use ADD, which
2870 // clobbers the EFLAGS. Check that we do not need to preserve it,
2871 // otherwise, conservatively assume this is not
2872 // safe to insert the epilogue here.
2873 return !flagsNeedToBePreservedBeforeTheTerminators(MBB);
2876 bool X86FrameLowering::enableShrinkWrapping(const MachineFunction &MF) const {
2877 // If we may need to emit frameless compact unwind information, give
2878 // up as this is currently broken: PR25614.
2879 return (MF.getFunction().hasFnAttribute(Attribute::NoUnwind) || hasFP(MF)) &&
2880 // The lowering of segmented stack and HiPE only support entry blocks
2881 // as prologue blocks: PR26107.
2882 // This limitation may be lifted if we fix:
2883 // - adjustForSegmentedStacks
2884 // - adjustForHiPEPrologue
2885 MF.getFunction().getCallingConv() != CallingConv::HiPE &&
2886 !MF.shouldSplitStack();
2889 MachineBasicBlock::iterator X86FrameLowering::restoreWin32EHStackPointers(
2890 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
2891 const DebugLoc &DL, bool RestoreSP) const {
2892 assert(STI.isTargetWindowsMSVC() && "funclets only supported in MSVC env");
2893 assert(STI.isTargetWin32() && "EBP/ESI restoration only required on win32");
2894 assert(STI.is32Bit() && !Uses64BitFramePtr &&
2895 "restoring EBP/ESI on non-32-bit target");
2897 MachineFunction &MF = *MBB.getParent();
2898 unsigned FramePtr = TRI->getFrameRegister(MF);
2899 unsigned BasePtr = TRI->getBaseRegister();
2900 WinEHFuncInfo &FuncInfo = *MF.getWinEHFuncInfo();
2901 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2902 MachineFrameInfo &MFI = MF.getFrameInfo();
2904 // FIXME: Don't set FrameSetup flag in catchret case.
2906 int FI = FuncInfo.EHRegNodeFrameIndex;
2907 int EHRegSize = MFI.getObjectSize(FI);
2910 // MOV32rm -EHRegSize(%ebp), %esp
2911 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), X86::ESP),
2912 X86::EBP, true, -EHRegSize)
2913 .setMIFlag(MachineInstr::FrameSetup);
2917 int EHRegOffset = getFrameIndexReference(MF, FI, UsedReg);
2918 int EndOffset = -EHRegOffset - EHRegSize;
2919 FuncInfo.EHRegNodeEndOffset = EndOffset;
2921 if (UsedReg == FramePtr) {
2922 // ADD $offset, %ebp
2923 unsigned ADDri = getADDriOpcode(false, EndOffset);
2924 BuildMI(MBB, MBBI, DL, TII.get(ADDri), FramePtr)
2927 .setMIFlag(MachineInstr::FrameSetup)
2930 assert(EndOffset >= 0 &&
2931 "end of registration object above normal EBP position!");
2932 } else if (UsedReg == BasePtr) {
2933 // LEA offset(%ebp), %esi
2934 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA32r), BasePtr),
2935 FramePtr, false, EndOffset)
2936 .setMIFlag(MachineInstr::FrameSetup);
2937 // MOV32rm SavedEBPOffset(%esi), %ebp
2938 assert(X86FI->getHasSEHFramePtrSave());
2940 getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg);
2941 assert(UsedReg == BasePtr);
2942 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), FramePtr),
2943 UsedReg, true, Offset)
2944 .setMIFlag(MachineInstr::FrameSetup);
2946 llvm_unreachable("32-bit frames with WinEH must use FramePtr or BasePtr");
2951 int X86FrameLowering::getInitialCFAOffset(const MachineFunction &MF) const {
2952 return TRI->getSlotSize();
2955 unsigned X86FrameLowering::getInitialCFARegister(const MachineFunction &MF)
2957 return TRI->getDwarfRegNum(StackPtr, true);
2961 // Struct used by orderFrameObjects to help sort the stack objects.
2962 struct X86FrameSortingObject {
2963 bool IsValid = false; // true if we care about this Object.
2964 unsigned ObjectIndex = 0; // Index of Object into MFI list.
2965 unsigned ObjectSize = 0; // Size of Object in bytes.
2966 unsigned ObjectAlignment = 1; // Alignment of Object in bytes.
2967 unsigned ObjectNumUses = 0; // Object static number of uses.
2970 // The comparison function we use for std::sort to order our local
2971 // stack symbols. The current algorithm is to use an estimated
2972 // "density". This takes into consideration the size and number of
2973 // uses each object has in order to roughly minimize code size.
2974 // So, for example, an object of size 16B that is referenced 5 times
2975 // will get higher priority than 4 4B objects referenced 1 time each.
2976 // It's not perfect and we may be able to squeeze a few more bytes out of
2977 // it (for example : 0(esp) requires fewer bytes, symbols allocated at the
2978 // fringe end can have special consideration, given their size is less
2979 // important, etc.), but the algorithmic complexity grows too much to be
2980 // worth the extra gains we get. This gets us pretty close.
2981 // The final order leaves us with objects with highest priority going
2982 // at the end of our list.
2983 struct X86FrameSortingComparator {
2984 inline bool operator()(const X86FrameSortingObject &A,
2985 const X86FrameSortingObject &B) {
2986 uint64_t DensityAScaled, DensityBScaled;
2988 // For consistency in our comparison, all invalid objects are placed
2989 // at the end. This also allows us to stop walking when we hit the
2990 // first invalid item after it's all sorted.
2996 // The density is calculated by doing :
2997 // (double)DensityA = A.ObjectNumUses / A.ObjectSize
2998 // (double)DensityB = B.ObjectNumUses / B.ObjectSize
2999 // Since this approach may cause inconsistencies in
3000 // the floating point <, >, == comparisons, depending on the floating
3001 // point model with which the compiler was built, we're going
3002 // to scale both sides by multiplying with
3003 // A.ObjectSize * B.ObjectSize. This ends up factoring away
3004 // the division and, with it, the need for any floating point
3006 DensityAScaled = static_cast<uint64_t>(A.ObjectNumUses) *
3007 static_cast<uint64_t>(B.ObjectSize);
3008 DensityBScaled = static_cast<uint64_t>(B.ObjectNumUses) *
3009 static_cast<uint64_t>(A.ObjectSize);
3011 // If the two densities are equal, prioritize highest alignment
3012 // objects. This allows for similar alignment objects
3013 // to be packed together (given the same density).
3014 // There's room for improvement here, also, since we can pack
3015 // similar alignment (different density) objects next to each
3016 // other to save padding. This will also require further
3017 // complexity/iterations, and the overall gain isn't worth it,
3018 // in general. Something to keep in mind, though.
3019 if (DensityAScaled == DensityBScaled)
3020 return A.ObjectAlignment < B.ObjectAlignment;
3022 return DensityAScaled < DensityBScaled;
3027 // Order the symbols in the local stack.
3028 // We want to place the local stack objects in some sort of sensible order.
3029 // The heuristic we use is to try and pack them according to static number
3030 // of uses and size of object in order to minimize code size.
3031 void X86FrameLowering::orderFrameObjects(
3032 const MachineFunction &MF, SmallVectorImpl<int> &ObjectsToAllocate) const {
3033 const MachineFrameInfo &MFI = MF.getFrameInfo();
3035 // Don't waste time if there's nothing to do.
3036 if (ObjectsToAllocate.empty())
3039 // Create an array of all MFI objects. We won't need all of these
3040 // objects, but we're going to create a full array of them to make
3041 // it easier to index into when we're counting "uses" down below.
3042 // We want to be able to easily/cheaply access an object by simply
3043 // indexing into it, instead of having to search for it every time.
3044 std::vector<X86FrameSortingObject> SortingObjects(MFI.getObjectIndexEnd());
3046 // Walk the objects we care about and mark them as such in our working
3048 for (auto &Obj : ObjectsToAllocate) {
3049 SortingObjects[Obj].IsValid = true;
3050 SortingObjects[Obj].ObjectIndex = Obj;
3051 SortingObjects[Obj].ObjectAlignment = MFI.getObjectAlignment(Obj);
3053 int ObjectSize = MFI.getObjectSize(Obj);
3054 if (ObjectSize == 0)
3055 // Variable size. Just use 4.
3056 SortingObjects[Obj].ObjectSize = 4;
3058 SortingObjects[Obj].ObjectSize = ObjectSize;
3061 // Count the number of uses for each object.
3062 for (auto &MBB : MF) {
3063 for (auto &MI : MBB) {
3064 if (MI.isDebugInstr())
3066 for (const MachineOperand &MO : MI.operands()) {
3067 // Check to see if it's a local stack symbol.
3070 int Index = MO.getIndex();
3071 // Check to see if it falls within our range, and is tagged
3072 // to require ordering.
3073 if (Index >= 0 && Index < MFI.getObjectIndexEnd() &&
3074 SortingObjects[Index].IsValid)
3075 SortingObjects[Index].ObjectNumUses++;
3080 // Sort the objects using X86FrameSortingAlgorithm (see its comment for
3082 std::stable_sort(SortingObjects.begin(), SortingObjects.end(),
3083 X86FrameSortingComparator());
3085 // Now modify the original list to represent the final order that
3086 // we want. The order will depend on whether we're going to access them
3087 // from the stack pointer or the frame pointer. For SP, the list should
3088 // end up with the END containing objects that we want with smaller offsets.
3089 // For FP, it should be flipped.
3091 for (auto &Obj : SortingObjects) {
3092 // All invalid items are sorted at the end, so it's safe to stop.
3095 ObjectsToAllocate[i++] = Obj.ObjectIndex;
3098 // Flip it if we're accessing off of the FP.
3099 if (!TRI->needsStackRealignment(MF) && hasFP(MF))
3100 std::reverse(ObjectsToAllocate.begin(), ObjectsToAllocate.end());
3104 unsigned X86FrameLowering::getWinEHParentFrameOffset(const MachineFunction &MF) const {
3105 // RDX, the parent frame pointer, is homed into 16(%rsp) in the prologue.
3106 unsigned Offset = 16;
3107 // RBP is immediately pushed.
3109 // All callee-saved registers are then pushed.
3110 Offset += MF.getInfo<X86MachineFunctionInfo>()->getCalleeSavedFrameSize();
3111 // Every funclet allocates enough stack space for the largest outgoing call.
3112 Offset += getWinEHFuncletFrameSize(MF);
3116 void X86FrameLowering::processFunctionBeforeFrameFinalized(
3117 MachineFunction &MF, RegScavenger *RS) const {
3118 // Mark the function as not having WinCFI. We will set it back to true in
3119 // emitPrologue if it gets called and emits CFI.
3120 MF.setHasWinCFI(false);
3122 // If this function isn't doing Win64-style C++ EH, we don't need to do
3124 const Function &F = MF.getFunction();
3125 if (!STI.is64Bit() || !MF.hasEHFunclets() ||
3126 classifyEHPersonality(F.getPersonalityFn()) != EHPersonality::MSVC_CXX)
3129 // Win64 C++ EH needs to allocate the UnwindHelp object at some fixed offset
3130 // relative to RSP after the prologue. Find the offset of the last fixed
3131 // object, so that we can allocate a slot immediately following it. If there
3132 // were no fixed objects, use offset -SlotSize, which is immediately after the
3133 // return address. Fixed objects have negative frame indices.
3134 MachineFrameInfo &MFI = MF.getFrameInfo();
3135 WinEHFuncInfo &EHInfo = *MF.getWinEHFuncInfo();
3136 int64_t MinFixedObjOffset = -SlotSize;
3137 for (int I = MFI.getObjectIndexBegin(); I < 0; ++I)
3138 MinFixedObjOffset = std::min(MinFixedObjOffset, MFI.getObjectOffset(I));
3140 for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
3141 for (WinEHHandlerType &H : TBME.HandlerArray) {
3142 int FrameIndex = H.CatchObj.FrameIndex;
3143 if (FrameIndex != INT_MAX) {
3144 // Ensure alignment.
3145 unsigned Align = MFI.getObjectAlignment(FrameIndex);
3146 MinFixedObjOffset -= std::abs(MinFixedObjOffset) % Align;
3147 MinFixedObjOffset -= MFI.getObjectSize(FrameIndex);
3148 MFI.setObjectOffset(FrameIndex, MinFixedObjOffset);
3153 // Ensure alignment.
3154 MinFixedObjOffset -= std::abs(MinFixedObjOffset) % 8;
3155 int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize;
3157 MFI.CreateFixedObject(SlotSize, UnwindHelpOffset, /*Immutable=*/false);
3158 EHInfo.UnwindHelpFrameIdx = UnwindHelpFI;
3160 // Store -2 into UnwindHelp on function entry. We have to scan forwards past
3161 // other frame setup instructions.
3162 MachineBasicBlock &MBB = MF.front();
3163 auto MBBI = MBB.begin();
3164 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
3167 DebugLoc DL = MBB.findDebugLoc(MBBI);
3168 addFrameReference(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mi32)),