1 //===- X86GenRegisterBankInfo.def ----------------------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file defines all the static objects used by X86RegisterBankInfo.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_BUILD_GLOBAL_ISEL
15 #error "You shouldn't build this"
18 #ifdef GET_TARGET_REGBANK_INFO_IMPL
19 RegisterBankInfo::PartialMapping X86GenRegisterBankInfo::PartMappings[]{
20 /* StartIdx, Length, RegBank */
22 {0, 8, X86::GPRRegBank}, // :0
23 {0, 16, X86::GPRRegBank}, // :1
24 {0, 32, X86::GPRRegBank}, // :2
25 {0, 64, X86::GPRRegBank}, // :3
26 // FR32/64 , xmm registers
27 {0, 32, X86::VECRRegBank}, // :4
28 {0, 64, X86::VECRRegBank}, // :5
30 {0, 128, X86::VECRRegBank}, // :6
31 {0, 256, X86::VECRRegBank}, // :7
32 {0, 512, X86::VECRRegBank}, // :8
34 #endif // GET_TARGET_REGBANK_INFO_IMPL
36 #ifdef GET_TARGET_REGBANK_INFO_CLASS
37 enum PartialMappingIdx {
49 #endif // GET_TARGET_REGBANK_INFO_CLASS
51 #ifdef GET_TARGET_REGBANK_INFO_IMPL
52 #define INSTR_3OP(INFO) INFO, INFO, INFO,
53 #define BREAKDOWN(INDEX, NUM) \
54 { &X86GenRegisterBankInfo::PartMappings[INDEX], NUM }
56 RegisterBankInfo::ValueMapping X86GenRegisterBankInfo::ValMappings[]{
57 /* BreakDown, NumBreakDowns */
58 // 3-operands instructions (all binary operations should end up with one of
60 INSTR_3OP(BREAKDOWN(PMI_GPR8, 1)) // 0: GPR_8
61 INSTR_3OP(BREAKDOWN(PMI_GPR16, 1)) // 3: GPR_16
62 INSTR_3OP(BREAKDOWN(PMI_GPR32, 1)) // 6: GPR_32
63 INSTR_3OP(BREAKDOWN(PMI_GPR64, 1)) // 9: GPR_64
64 INSTR_3OP(BREAKDOWN(PMI_FP32, 1)) // 12: Fp32
65 INSTR_3OP(BREAKDOWN(PMI_FP64, 1)) // 15: Fp64
66 INSTR_3OP(BREAKDOWN(PMI_VEC128, 1)) // 18: Vec128
67 INSTR_3OP(BREAKDOWN(PMI_VEC256, 1)) // 21: Vec256
68 INSTR_3OP(BREAKDOWN(PMI_VEC512, 1)) // 24: Vec512
72 #endif // GET_TARGET_REGBANK_INFO_IMPL
74 #ifdef GET_TARGET_REGBANK_INFO_CLASS
75 enum ValueMappingIdx {
77 VMI_3OpsGpr8Idx = PMI_GPR8 * 3,
78 VMI_3OpsGpr16Idx = PMI_GPR16 * 3,
79 VMI_3OpsGpr32Idx = PMI_GPR32 * 3,
80 VMI_3OpsGpr64Idx = PMI_GPR64 * 3,
81 VMI_3OpsFp32Idx = PMI_FP32 * 3,
82 VMI_3OpsFp64Idx = PMI_FP64 * 3,
83 VMI_3OpsVec128Idx = PMI_VEC128 * 3,
84 VMI_3OpsVec256Idx = PMI_VEC256 * 3,
85 VMI_3OpsVec512Idx = PMI_VEC512 * 3,
87 #undef GET_TARGET_REGBANK_INFO_CLASS
88 #endif // GET_TARGET_REGBANK_INFO_CLASS
90 #ifdef GET_TARGET_REGBANK_INFO_IMPL
91 #undef GET_TARGET_REGBANK_INFO_IMPL
92 const RegisterBankInfo::ValueMapping *
93 X86GenRegisterBankInfo::getValueMapping(PartialMappingIdx Idx,
94 unsigned NumOperands) {
96 // We can use VMI_3Ops Mapping for all the cases.
97 if (NumOperands <= 3 && (Idx >= PMI_GPR8 && Idx <= PMI_VEC512))
98 return &ValMappings[(unsigned)Idx * 3];
100 llvm_unreachable("Unsupported PartialMappingIdx.");
103 #endif // GET_TARGET_REGBANK_INFO_IMPL