1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86RegisterInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
40 #define DEBUG_TYPE "x86-isel"
42 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
44 //===----------------------------------------------------------------------===//
45 // Pattern Matcher Implementation
46 //===----------------------------------------------------------------------===//
49 /// This corresponds to X86AddressMode, but uses SDValue's instead of register
50 /// numbers for the leaves of the matched tree.
51 struct X86ISelAddressMode {
57 // This is really a union, discriminated by BaseType!
65 const GlobalValue *GV;
67 const BlockAddress *BlockAddr;
71 unsigned Align; // CP alignment.
72 unsigned char SymbolFlags; // X86II::MO_*
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
76 Segment(), GV(nullptr), CP(nullptr), BlockAddr(nullptr), ES(nullptr),
77 MCSym(nullptr), JT(-1), Align(0), SymbolFlags(X86II::MO_NO_FLAG) {}
79 bool hasSymbolicDisplacement() const {
80 return GV != nullptr || CP != nullptr || ES != nullptr ||
81 MCSym != nullptr || JT != -1 || BlockAddr != nullptr;
84 bool hasBaseOrIndexReg() const {
85 return BaseType == FrameIndexBase ||
86 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr;
89 /// Return true if this addressing mode is already RIP-relative.
90 bool isRIPRelative() const {
91 if (BaseType != RegBase) return false;
92 if (RegisterSDNode *RegNode =
93 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
94 return RegNode->getReg() == X86::RIP;
98 void setBaseReg(SDValue Reg) {
103 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
105 dbgs() << "X86ISelAddressMode " << this << '\n';
106 dbgs() << "Base_Reg ";
107 if (Base_Reg.getNode())
108 Base_Reg.getNode()->dump();
111 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
112 << " Scale" << Scale << '\n'
114 if (IndexReg.getNode())
115 IndexReg.getNode()->dump();
118 dbgs() << " Disp " << Disp << '\n'
140 dbgs() << " JT" << JT << " Align" << Align << '\n';
147 //===--------------------------------------------------------------------===//
148 /// ISel - X86-specific code to select X86 machine instructions for
149 /// SelectionDAG operations.
151 class X86DAGToDAGISel final : public SelectionDAGISel {
152 /// Keep a pointer to the X86Subtarget around so that we can
153 /// make the right decision when generating code for different targets.
154 const X86Subtarget *Subtarget;
156 /// If true, selector should try to optimize for code size instead of
160 /// If true, selector should try to optimize for minimum code size.
164 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
165 : SelectionDAGISel(tm, OptLevel), OptForSize(false),
166 OptForMinSize(false) {}
168 const char *getPassName() const override {
169 return "X86 DAG->DAG Instruction Selection";
172 bool runOnMachineFunction(MachineFunction &MF) override {
173 // Reset the subtarget each time through.
174 Subtarget = &MF.getSubtarget<X86Subtarget>();
175 SelectionDAGISel::runOnMachineFunction(MF);
179 void EmitFunctionEntryCode() override;
181 bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
183 void PreprocessISelDAG() override;
185 inline bool immSext8(SDNode *N) const {
186 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
189 // True if the 64-bit immediate fits in a 32-bit sign-extended field.
190 inline bool i64immSExt32(SDNode *N) const {
191 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
192 return (int64_t)v == (int32_t)v;
195 // Include the pieces autogenerated from the target description.
196 #include "X86GenDAGISel.inc"
199 void Select(SDNode *N) override;
200 bool tryGather(SDNode *N, unsigned Opc);
202 bool foldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
203 bool matchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
204 bool matchWrapper(SDValue N, X86ISelAddressMode &AM);
205 bool matchAddress(SDValue N, X86ISelAddressMode &AM);
206 bool matchAdd(SDValue N, X86ISelAddressMode &AM, unsigned Depth);
207 bool matchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
209 bool matchAddressBase(SDValue N, X86ISelAddressMode &AM);
210 bool selectAddr(SDNode *Parent, SDValue N, SDValue &Base,
211 SDValue &Scale, SDValue &Index, SDValue &Disp,
213 bool selectVectorAddr(SDNode *Parent, SDValue N, SDValue &Base,
214 SDValue &Scale, SDValue &Index, SDValue &Disp,
216 bool selectMOV64Imm32(SDValue N, SDValue &Imm);
217 bool selectLEAAddr(SDValue N, SDValue &Base,
218 SDValue &Scale, SDValue &Index, SDValue &Disp,
220 bool selectLEA64_32Addr(SDValue N, SDValue &Base,
221 SDValue &Scale, SDValue &Index, SDValue &Disp,
223 bool selectTLSADDRAddr(SDValue N, SDValue &Base,
224 SDValue &Scale, SDValue &Index, SDValue &Disp,
226 bool selectScalarSSELoad(SDNode *Root, SDValue N,
227 SDValue &Base, SDValue &Scale,
228 SDValue &Index, SDValue &Disp,
230 SDValue &NodeWithChain);
232 bool tryFoldLoad(SDNode *P, SDValue N,
233 SDValue &Base, SDValue &Scale,
234 SDValue &Index, SDValue &Disp,
237 /// Implement addressing mode selection for inline asm expressions.
238 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
239 unsigned ConstraintID,
240 std::vector<SDValue> &OutOps) override;
242 void emitSpecialCodeForMain();
244 inline void getAddressOperands(X86ISelAddressMode &AM, const SDLoc &DL,
245 SDValue &Base, SDValue &Scale,
246 SDValue &Index, SDValue &Disp,
248 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
249 ? CurDAG->getTargetFrameIndex(
251 TLI->getPointerTy(CurDAG->getDataLayout()))
253 Scale = getI8Imm(AM.Scale, DL);
255 // These are 32-bit even in 64-bit mode since RIP-relative offset
258 Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(),
262 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
263 AM.Align, AM.Disp, AM.SymbolFlags);
265 assert(!AM.Disp && "Non-zero displacement is ignored with ES.");
266 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
267 } else if (AM.MCSym) {
268 assert(!AM.Disp && "Non-zero displacement is ignored with MCSym.");
269 assert(AM.SymbolFlags == 0 && "oo");
270 Disp = CurDAG->getMCSymbol(AM.MCSym, MVT::i32);
271 } else if (AM.JT != -1) {
272 assert(!AM.Disp && "Non-zero displacement is ignored with JT.");
273 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
274 } else if (AM.BlockAddr)
275 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
278 Disp = CurDAG->getTargetConstant(AM.Disp, DL, MVT::i32);
280 if (AM.Segment.getNode())
281 Segment = AM.Segment;
283 Segment = CurDAG->getRegister(0, MVT::i32);
286 // Utility function to determine whether we should avoid selecting
287 // immediate forms of instructions for better code size or not.
288 // At a high level, we'd like to avoid such instructions when
289 // we have similar constants used within the same basic block
290 // that can be kept in a register.
292 bool shouldAvoidImmediateInstFormsForSize(SDNode *N) const {
293 uint32_t UseCount = 0;
295 // Do not want to hoist if we're not optimizing for size.
296 // TODO: We'd like to remove this restriction.
297 // See the comment in X86InstrInfo.td for more info.
301 // Walk all the users of the immediate.
302 for (SDNode::use_iterator UI = N->use_begin(),
303 UE = N->use_end(); (UI != UE) && (UseCount < 2); ++UI) {
307 // This user is already selected. Count it as a legitimate use and
309 if (User->isMachineOpcode()) {
314 // We want to count stores of immediates as real uses.
315 if (User->getOpcode() == ISD::STORE &&
316 User->getOperand(1).getNode() == N) {
321 // We don't currently match users that have > 2 operands (except
322 // for stores, which are handled above)
323 // Those instruction won't match in ISEL, for now, and would
324 // be counted incorrectly.
325 // This may change in the future as we add additional instruction
327 if (User->getNumOperands() != 2)
330 // Immediates that are used for offsets as part of stack
331 // manipulation should be left alone. These are typically
332 // used to indicate SP offsets for argument passing and
333 // will get pulled into stores/pushes (implicitly).
334 if (User->getOpcode() == X86ISD::ADD ||
335 User->getOpcode() == ISD::ADD ||
336 User->getOpcode() == X86ISD::SUB ||
337 User->getOpcode() == ISD::SUB) {
339 // Find the other operand of the add/sub.
340 SDValue OtherOp = User->getOperand(0);
341 if (OtherOp.getNode() == N)
342 OtherOp = User->getOperand(1);
344 // Don't count if the other operand is SP.
345 RegisterSDNode *RegNode;
346 if (OtherOp->getOpcode() == ISD::CopyFromReg &&
347 (RegNode = dyn_cast_or_null<RegisterSDNode>(
348 OtherOp->getOperand(1).getNode())))
349 if ((RegNode->getReg() == X86::ESP) ||
350 (RegNode->getReg() == X86::RSP))
354 // ... otherwise, count this and move on.
358 // If we have more than 1 use, then recommend for hoisting.
359 return (UseCount > 1);
362 /// Return a target constant with the specified value of type i8.
363 inline SDValue getI8Imm(unsigned Imm, const SDLoc &DL) {
364 return CurDAG->getTargetConstant(Imm, DL, MVT::i8);
367 /// Return a target constant with the specified value, of type i32.
368 inline SDValue getI32Imm(unsigned Imm, const SDLoc &DL) {
369 return CurDAG->getTargetConstant(Imm, DL, MVT::i32);
372 /// Return an SDNode that returns the value of the global base register.
373 /// Output instructions required to initialize the global base register,
375 SDNode *getGlobalBaseReg();
377 /// Return a reference to the TargetMachine, casted to the target-specific
379 const X86TargetMachine &getTargetMachine() const {
380 return static_cast<const X86TargetMachine &>(TM);
383 /// Return a reference to the TargetInstrInfo, casted to the target-specific
385 const X86InstrInfo *getInstrInfo() const {
386 return Subtarget->getInstrInfo();
389 /// \brief Address-mode matching performs shift-of-and to and-of-shift
390 /// reassociation in order to expose more scaled addressing
392 bool ComplexPatternFuncMutatesDAG() const override {
400 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
401 if (OptLevel == CodeGenOpt::None) return false;
406 if (N.getOpcode() != ISD::LOAD)
409 // If N is a load, do additional profitability checks.
411 switch (U->getOpcode()) {
424 SDValue Op1 = U->getOperand(1);
426 // If the other operand is a 8-bit immediate we should fold the immediate
427 // instead. This reduces code size.
429 // movl 4(%esp), %eax
433 // addl 4(%esp), %eax
434 // The former is 2 bytes shorter. In case where the increment is 1, then
435 // the saving can be 4 bytes (by using incl %eax).
436 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
437 if (Imm->getAPIntValue().isSignedIntN(8))
440 // If the other operand is a TLS address, we should fold it instead.
443 // leal i@NTPOFF(%eax), %eax
445 // movl $i@NTPOFF, %eax
447 // if the block also has an access to a second TLS address this will save
449 // FIXME: This is probably also true for non-TLS addresses.
450 if (Op1.getOpcode() == X86ISD::Wrapper) {
451 SDValue Val = Op1.getOperand(0);
452 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
462 /// Replace the original chain operand of the call with
463 /// load's chain operand and move load below the call's chain operand.
464 static void moveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
465 SDValue Call, SDValue OrigChain) {
466 SmallVector<SDValue, 8> Ops;
467 SDValue Chain = OrigChain.getOperand(0);
468 if (Chain.getNode() == Load.getNode())
469 Ops.push_back(Load.getOperand(0));
471 assert(Chain.getOpcode() == ISD::TokenFactor &&
472 "Unexpected chain operand");
473 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
474 if (Chain.getOperand(i).getNode() == Load.getNode())
475 Ops.push_back(Load.getOperand(0));
477 Ops.push_back(Chain.getOperand(i));
479 CurDAG->getNode(ISD::TokenFactor, SDLoc(Load), MVT::Other, Ops);
481 Ops.push_back(NewChain);
483 Ops.append(OrigChain->op_begin() + 1, OrigChain->op_end());
484 CurDAG->UpdateNodeOperands(OrigChain.getNode(), Ops);
485 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
486 Load.getOperand(1), Load.getOperand(2));
489 Ops.push_back(SDValue(Load.getNode(), 1));
490 Ops.append(Call->op_begin() + 1, Call->op_end());
491 CurDAG->UpdateNodeOperands(Call.getNode(), Ops);
494 /// Return true if call address is a load and it can be
495 /// moved below CALLSEQ_START and the chains leading up to the call.
496 /// Return the CALLSEQ_START by reference as a second output.
497 /// In the case of a tail call, there isn't a callseq node between the call
498 /// chain and the load.
499 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
500 // The transformation is somewhat dangerous if the call's chain was glued to
501 // the call. After MoveBelowOrigChain the load is moved between the call and
502 // the chain, this can create a cycle if the load is not folded. So it is
503 // *really* important that we are sure the load will be folded.
504 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
506 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
509 LD->getAddressingMode() != ISD::UNINDEXED ||
510 LD->getExtensionType() != ISD::NON_EXTLOAD)
513 // Now let's find the callseq_start.
514 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
515 if (!Chain.hasOneUse())
517 Chain = Chain.getOperand(0);
520 if (!Chain.getNumOperands())
522 // Since we are not checking for AA here, conservatively abort if the chain
523 // writes to memory. It's not safe to move the callee (a load) across a store.
524 if (isa<MemSDNode>(Chain.getNode()) &&
525 cast<MemSDNode>(Chain.getNode())->writeMem())
527 if (Chain.getOperand(0).getNode() == Callee.getNode())
529 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
530 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
531 Callee.getValue(1).hasOneUse())
536 void X86DAGToDAGISel::PreprocessISelDAG() {
537 // OptFor[Min]Size are used in pattern predicates that isel is matching.
538 OptForSize = MF->getFunction()->optForSize();
539 OptForMinSize = MF->getFunction()->optForMinSize();
540 assert((!OptForMinSize || OptForSize) && "OptForMinSize implies OptForSize");
542 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
543 E = CurDAG->allnodes_end(); I != E; ) {
544 SDNode *N = &*I++; // Preincrement iterator to avoid invalidation issues.
546 if (OptLevel != CodeGenOpt::None &&
547 // Only does this when target favors doesn't favor register indirect
549 ((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) ||
550 (N->getOpcode() == X86ISD::TC_RETURN &&
551 // Only does this if load can be folded into TC_RETURN.
552 (Subtarget->is64Bit() ||
553 !getTargetMachine().isPositionIndependent())))) {
554 /// Also try moving call address load from outside callseq_start to just
555 /// before the call to allow it to be folded.
573 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
574 SDValue Chain = N->getOperand(0);
575 SDValue Load = N->getOperand(1);
576 if (!isCalleeLoad(Load, Chain, HasCallSeq))
578 moveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
583 // Lower fpround and fpextend nodes that target the FP stack to be store and
584 // load to the stack. This is a gross hack. We would like to simply mark
585 // these as being illegal, but when we do that, legalize produces these when
586 // it expands calls, then expands these in the same legalize pass. We would
587 // like dag combine to be able to hack on these between the call expansion
588 // and the node legalization. As such this pass basically does "really
589 // late" legalization of these inline with the X86 isel pass.
590 // FIXME: This should only happen when not compiled with -O0.
591 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
594 MVT SrcVT = N->getOperand(0).getSimpleValueType();
595 MVT DstVT = N->getSimpleValueType(0);
597 // If any of the sources are vectors, no fp stack involved.
598 if (SrcVT.isVector() || DstVT.isVector())
601 // If the source and destination are SSE registers, then this is a legal
602 // conversion that should not be lowered.
603 const X86TargetLowering *X86Lowering =
604 static_cast<const X86TargetLowering *>(TLI);
605 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
606 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT);
607 if (SrcIsSSE && DstIsSSE)
610 if (!SrcIsSSE && !DstIsSSE) {
611 // If this is an FPStack extension, it is a noop.
612 if (N->getOpcode() == ISD::FP_EXTEND)
614 // If this is a value-preserving FPStack truncation, it is a noop.
615 if (N->getConstantOperandVal(1))
619 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
620 // FPStack has extload and truncstore. SSE can fold direct loads into other
621 // operations. Based on this, decide what we want to do.
623 if (N->getOpcode() == ISD::FP_ROUND)
624 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
626 MemVT = SrcIsSSE ? SrcVT : DstVT;
628 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
631 // FIXME: optimize the case where the src/dest is a load or store?
633 CurDAG->getTruncStore(CurDAG->getEntryNode(), dl, N->getOperand(0),
634 MemTmp, MachinePointerInfo(), MemVT);
635 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
636 MachinePointerInfo(), MemVT);
638 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
639 // extload we created. This will cause general havok on the dag because
640 // anything below the conversion could be folded into other existing nodes.
641 // To avoid invalidating 'I', back it up to the convert node.
643 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
645 // Now that we did that, the node is dead. Increment the iterator to the
646 // next node to process, then delete N.
648 CurDAG->DeleteNode(N);
653 /// Emit any code that needs to be executed only in the main function.
654 void X86DAGToDAGISel::emitSpecialCodeForMain() {
655 if (Subtarget->isTargetCygMing()) {
656 TargetLowering::ArgListTy Args;
657 auto &DL = CurDAG->getDataLayout();
659 TargetLowering::CallLoweringInfo CLI(*CurDAG);
660 CLI.setChain(CurDAG->getRoot())
661 .setCallee(CallingConv::C, Type::getVoidTy(*CurDAG->getContext()),
662 CurDAG->getExternalSymbol("__main", TLI->getPointerTy(DL)),
664 const TargetLowering &TLI = CurDAG->getTargetLoweringInfo();
665 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
666 CurDAG->setRoot(Result.second);
670 void X86DAGToDAGISel::EmitFunctionEntryCode() {
671 // If this is main, emit special code for main.
672 if (const Function *Fn = MF->getFunction())
673 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
674 emitSpecialCodeForMain();
677 static bool isDispSafeForFrameIndex(int64_t Val) {
678 // On 64-bit platforms, we can run into an issue where a frame index
679 // includes a displacement that, when added to the explicit displacement,
680 // will overflow the displacement field. Assuming that the frame index
681 // displacement fits into a 31-bit integer (which is only slightly more
682 // aggressive than the current fundamental assumption that it fits into
683 // a 32-bit integer), a 31-bit disp should always be safe.
684 return isInt<31>(Val);
687 bool X86DAGToDAGISel::foldOffsetIntoAddress(uint64_t Offset,
688 X86ISelAddressMode &AM) {
689 // Cannot combine ExternalSymbol displacements with integer offsets.
690 if (Offset != 0 && (AM.ES || AM.MCSym))
692 int64_t Val = AM.Disp + Offset;
693 CodeModel::Model M = TM.getCodeModel();
694 if (Subtarget->is64Bit()) {
695 if (!X86::isOffsetSuitableForCodeModel(Val, M,
696 AM.hasSymbolicDisplacement()))
698 // In addition to the checks required for a register base, check that
699 // we do not try to use an unsafe Disp with a frame index.
700 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase &&
701 !isDispSafeForFrameIndex(Val))
709 bool X86DAGToDAGISel::matchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
710 SDValue Address = N->getOperand(1);
712 // load gs:0 -> GS segment register.
713 // load fs:0 -> FS segment register.
715 // This optimization is valid because the GNU TLS model defines that
716 // gs:0 (or fs:0 on X86-64) contains its own address.
717 // For more information see http://people.redhat.com/drepper/tls.pdf
718 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
719 if (C->getSExtValue() == 0 && AM.Segment.getNode() == nullptr &&
720 Subtarget->isTargetGlibc())
721 switch (N->getPointerInfo().getAddrSpace()) {
723 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
726 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
728 // Address space 258 is not handled here, because it is not used to
729 // address TLS areas.
735 /// Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes into an addressing
736 /// mode. These wrap things that will resolve down into a symbol reference.
737 /// If no match is possible, this returns true, otherwise it returns false.
738 bool X86DAGToDAGISel::matchWrapper(SDValue N, X86ISelAddressMode &AM) {
739 // If the addressing mode already has a symbol as the displacement, we can
740 // never match another symbol.
741 if (AM.hasSymbolicDisplacement())
744 SDValue N0 = N.getOperand(0);
745 CodeModel::Model M = TM.getCodeModel();
747 // Handle X86-64 rip-relative addresses. We check this before checking direct
748 // folding because RIP is preferable to non-RIP accesses.
749 if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP &&
750 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
751 // they cannot be folded into immediate fields.
752 // FIXME: This can be improved for kernel and other models?
753 (M == CodeModel::Small || M == CodeModel::Kernel)) {
754 // Base and index reg must be 0 in order to use %rip as base.
755 if (AM.hasBaseOrIndexReg())
757 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
758 X86ISelAddressMode Backup = AM;
759 AM.GV = G->getGlobal();
760 AM.SymbolFlags = G->getTargetFlags();
761 if (foldOffsetIntoAddress(G->getOffset(), AM)) {
765 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
766 X86ISelAddressMode Backup = AM;
767 AM.CP = CP->getConstVal();
768 AM.Align = CP->getAlignment();
769 AM.SymbolFlags = CP->getTargetFlags();
770 if (foldOffsetIntoAddress(CP->getOffset(), AM)) {
774 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
775 AM.ES = S->getSymbol();
776 AM.SymbolFlags = S->getTargetFlags();
777 } else if (auto *S = dyn_cast<MCSymbolSDNode>(N0)) {
778 AM.MCSym = S->getMCSymbol();
779 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
780 AM.JT = J->getIndex();
781 AM.SymbolFlags = J->getTargetFlags();
782 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
783 X86ISelAddressMode Backup = AM;
784 AM.BlockAddr = BA->getBlockAddress();
785 AM.SymbolFlags = BA->getTargetFlags();
786 if (foldOffsetIntoAddress(BA->getOffset(), AM)) {
791 llvm_unreachable("Unhandled symbol reference node.");
793 if (N.getOpcode() == X86ISD::WrapperRIP)
794 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
798 // Handle the case when globals fit in our immediate field: This is true for
799 // X86-32 always and X86-64 when in -mcmodel=small mode. In 64-bit
800 // mode, this only applies to a non-RIP-relative computation.
801 if (!Subtarget->is64Bit() ||
802 M == CodeModel::Small || M == CodeModel::Kernel) {
803 assert(N.getOpcode() != X86ISD::WrapperRIP &&
804 "RIP-relative addressing already handled");
805 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
806 AM.GV = G->getGlobal();
807 AM.Disp += G->getOffset();
808 AM.SymbolFlags = G->getTargetFlags();
809 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
810 AM.CP = CP->getConstVal();
811 AM.Align = CP->getAlignment();
812 AM.Disp += CP->getOffset();
813 AM.SymbolFlags = CP->getTargetFlags();
814 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
815 AM.ES = S->getSymbol();
816 AM.SymbolFlags = S->getTargetFlags();
817 } else if (auto *S = dyn_cast<MCSymbolSDNode>(N0)) {
818 AM.MCSym = S->getMCSymbol();
819 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
820 AM.JT = J->getIndex();
821 AM.SymbolFlags = J->getTargetFlags();
822 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
823 AM.BlockAddr = BA->getBlockAddress();
824 AM.Disp += BA->getOffset();
825 AM.SymbolFlags = BA->getTargetFlags();
827 llvm_unreachable("Unhandled symbol reference node.");
834 /// Add the specified node to the specified addressing mode, returning true if
835 /// it cannot be done. This just pattern matches for the addressing mode.
836 bool X86DAGToDAGISel::matchAddress(SDValue N, X86ISelAddressMode &AM) {
837 if (matchAddressRecursively(N, AM, 0))
840 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
841 // a smaller encoding and avoids a scaled-index.
843 AM.BaseType == X86ISelAddressMode::RegBase &&
844 AM.Base_Reg.getNode() == nullptr) {
845 AM.Base_Reg = AM.IndexReg;
849 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
850 // because it has a smaller encoding.
851 // TODO: Which other code models can use this?
852 if (TM.getCodeModel() == CodeModel::Small &&
853 Subtarget->is64Bit() &&
855 AM.BaseType == X86ISelAddressMode::RegBase &&
856 AM.Base_Reg.getNode() == nullptr &&
857 AM.IndexReg.getNode() == nullptr &&
858 AM.SymbolFlags == X86II::MO_NO_FLAG &&
859 AM.hasSymbolicDisplacement())
860 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
865 bool X86DAGToDAGISel::matchAdd(SDValue N, X86ISelAddressMode &AM,
867 // Add an artificial use to this node so that we can keep track of
868 // it if it gets CSE'd with a different node.
869 HandleSDNode Handle(N);
871 X86ISelAddressMode Backup = AM;
872 if (!matchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
873 !matchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
877 // Try again after commuting the operands.
878 if (!matchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1) &&
879 !matchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
883 // If we couldn't fold both operands into the address at the same time,
884 // see if we can just put each operand into a register and fold at least
886 if (AM.BaseType == X86ISelAddressMode::RegBase &&
887 !AM.Base_Reg.getNode() &&
888 !AM.IndexReg.getNode()) {
889 N = Handle.getValue();
890 AM.Base_Reg = N.getOperand(0);
891 AM.IndexReg = N.getOperand(1);
895 N = Handle.getValue();
899 // Insert a node into the DAG at least before the Pos node's position. This
900 // will reposition the node as needed, and will assign it a node ID that is <=
901 // the Pos node's ID. Note that this does *not* preserve the uniqueness of node
902 // IDs! The selection DAG must no longer depend on their uniqueness when this
904 static void insertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
905 if (N.getNode()->getNodeId() == -1 ||
906 N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) {
907 DAG.RepositionNode(Pos.getNode()->getIterator(), N.getNode());
908 N.getNode()->setNodeId(Pos.getNode()->getNodeId());
912 // Transform "(X >> (8-C1)) & (0xff << C1)" to "((X >> 8) & 0xff) << C1" if
913 // safe. This allows us to convert the shift and and into an h-register
914 // extract and a scaled index. Returns false if the simplification is
916 static bool foldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
918 SDValue Shift, SDValue X,
919 X86ISelAddressMode &AM) {
920 if (Shift.getOpcode() != ISD::SRL ||
921 !isa<ConstantSDNode>(Shift.getOperand(1)) ||
925 int ScaleLog = 8 - Shift.getConstantOperandVal(1);
926 if (ScaleLog <= 0 || ScaleLog >= 4 ||
927 Mask != (0xffu << ScaleLog))
930 MVT VT = N.getSimpleValueType();
932 SDValue Eight = DAG.getConstant(8, DL, MVT::i8);
933 SDValue NewMask = DAG.getConstant(0xff, DL, VT);
934 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
935 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
936 SDValue ShlCount = DAG.getConstant(ScaleLog, DL, MVT::i8);
937 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
939 // Insert the new nodes into the topological ordering. We must do this in
940 // a valid topological ordering as nothing is going to go back and re-sort
941 // these nodes. We continually insert before 'N' in sequence as this is
942 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
943 // hierarchy left to express.
944 insertDAGNode(DAG, N, Eight);
945 insertDAGNode(DAG, N, Srl);
946 insertDAGNode(DAG, N, NewMask);
947 insertDAGNode(DAG, N, And);
948 insertDAGNode(DAG, N, ShlCount);
949 insertDAGNode(DAG, N, Shl);
950 DAG.ReplaceAllUsesWith(N, Shl);
952 AM.Scale = (1 << ScaleLog);
956 // Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this
957 // allows us to fold the shift into this addressing mode. Returns false if the
958 // transform succeeded.
959 static bool foldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
961 SDValue Shift, SDValue X,
962 X86ISelAddressMode &AM) {
963 if (Shift.getOpcode() != ISD::SHL ||
964 !isa<ConstantSDNode>(Shift.getOperand(1)))
967 // Not likely to be profitable if either the AND or SHIFT node has more
968 // than one use (unless all uses are for address computation). Besides,
969 // isel mechanism requires their node ids to be reused.
970 if (!N.hasOneUse() || !Shift.hasOneUse())
973 // Verify that the shift amount is something we can fold.
974 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
975 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
978 MVT VT = N.getSimpleValueType();
980 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, DL, VT);
981 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
982 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
984 // Insert the new nodes into the topological ordering. We must do this in
985 // a valid topological ordering as nothing is going to go back and re-sort
986 // these nodes. We continually insert before 'N' in sequence as this is
987 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
988 // hierarchy left to express.
989 insertDAGNode(DAG, N, NewMask);
990 insertDAGNode(DAG, N, NewAnd);
991 insertDAGNode(DAG, N, NewShift);
992 DAG.ReplaceAllUsesWith(N, NewShift);
994 AM.Scale = 1 << ShiftAmt;
995 AM.IndexReg = NewAnd;
999 // Implement some heroics to detect shifts of masked values where the mask can
1000 // be replaced by extending the shift and undoing that in the addressing mode
1001 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
1002 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
1003 // the addressing mode. This results in code such as:
1005 // int f(short *y, int *lookup_table) {
1007 // return *y + lookup_table[*y >> 11];
1011 // movzwl (%rdi), %eax
1014 // addl (%rsi,%rcx,4), %eax
1017 // movzwl (%rdi), %eax
1021 // addl (%rsi,%rcx), %eax
1023 // Note that this function assumes the mask is provided as a mask *after* the
1024 // value is shifted. The input chain may or may not match that, but computing
1025 // such a mask is trivial.
1026 static bool foldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
1028 SDValue Shift, SDValue X,
1029 X86ISelAddressMode &AM) {
1030 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
1031 !isa<ConstantSDNode>(Shift.getOperand(1)))
1034 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
1035 unsigned MaskLZ = countLeadingZeros(Mask);
1036 unsigned MaskTZ = countTrailingZeros(Mask);
1038 // The amount of shift we're trying to fit into the addressing mode is taken
1039 // from the trailing zeros of the mask.
1040 unsigned AMShiftAmt = MaskTZ;
1042 // There is nothing we can do here unless the mask is removing some bits.
1043 // Also, the addressing mode can only represent shifts of 1, 2, or 3 bits.
1044 if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true;
1046 // We also need to ensure that mask is a continuous run of bits.
1047 if (countTrailingOnes(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
1049 // Scale the leading zero count down based on the actual size of the value.
1050 // Also scale it down based on the size of the shift.
1051 MaskLZ -= (64 - X.getSimpleValueType().getSizeInBits()) + ShiftAmt;
1053 // The final check is to ensure that any masked out high bits of X are
1054 // already known to be zero. Otherwise, the mask has a semantic impact
1055 // other than masking out a couple of low bits. Unfortunately, because of
1056 // the mask, zero extensions will be removed from operands in some cases.
1057 // This code works extra hard to look through extensions because we can
1058 // replace them with zero extensions cheaply if necessary.
1059 bool ReplacingAnyExtend = false;
1060 if (X.getOpcode() == ISD::ANY_EXTEND) {
1061 unsigned ExtendBits = X.getSimpleValueType().getSizeInBits() -
1062 X.getOperand(0).getSimpleValueType().getSizeInBits();
1063 // Assume that we'll replace the any-extend with a zero-extend, and
1064 // narrow the search to the extended value.
1065 X = X.getOperand(0);
1066 MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits;
1067 ReplacingAnyExtend = true;
1069 APInt MaskedHighBits =
1070 APInt::getHighBitsSet(X.getSimpleValueType().getSizeInBits(), MaskLZ);
1071 APInt KnownZero, KnownOne;
1072 DAG.computeKnownBits(X, KnownZero, KnownOne);
1073 if (MaskedHighBits != KnownZero) return true;
1075 // We've identified a pattern that can be transformed into a single shift
1076 // and an addressing mode. Make it so.
1077 MVT VT = N.getSimpleValueType();
1078 if (ReplacingAnyExtend) {
1079 assert(X.getValueType() != VT);
1080 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
1081 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(X), VT, X);
1082 insertDAGNode(DAG, N, NewX);
1086 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, DL, MVT::i8);
1087 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
1088 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, DL, MVT::i8);
1089 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
1091 // Insert the new nodes into the topological ordering. We must do this in
1092 // a valid topological ordering as nothing is going to go back and re-sort
1093 // these nodes. We continually insert before 'N' in sequence as this is
1094 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
1095 // hierarchy left to express.
1096 insertDAGNode(DAG, N, NewSRLAmt);
1097 insertDAGNode(DAG, N, NewSRL);
1098 insertDAGNode(DAG, N, NewSHLAmt);
1099 insertDAGNode(DAG, N, NewSHL);
1100 DAG.ReplaceAllUsesWith(N, NewSHL);
1102 AM.Scale = 1 << AMShiftAmt;
1103 AM.IndexReg = NewSRL;
1107 bool X86DAGToDAGISel::matchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
1111 dbgs() << "MatchAddress: ";
1116 return matchAddressBase(N, AM);
1118 // If this is already a %rip relative address, we can only merge immediates
1119 // into it. Instead of handling this in every case, we handle it here.
1120 // RIP relative addressing: %rip + 32-bit displacement!
1121 if (AM.isRIPRelative()) {
1122 // FIXME: JumpTable and ExternalSymbol address currently don't like
1123 // displacements. It isn't very important, but this should be fixed for
1125 if (!(AM.ES || AM.MCSym) && AM.JT != -1)
1128 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
1129 if (!foldOffsetIntoAddress(Cst->getSExtValue(), AM))
1134 switch (N.getOpcode()) {
1136 case ISD::LOCAL_RECOVER: {
1137 if (!AM.hasSymbolicDisplacement() && AM.Disp == 0)
1138 if (const auto *ESNode = dyn_cast<MCSymbolSDNode>(N.getOperand(0))) {
1139 // Use the symbol and don't prefix it.
1140 AM.MCSym = ESNode->getMCSymbol();
1145 case ISD::Constant: {
1146 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
1147 if (!foldOffsetIntoAddress(Val, AM))
1152 case X86ISD::Wrapper:
1153 case X86ISD::WrapperRIP:
1154 if (!matchWrapper(N, AM))
1159 if (!matchLoadInAddress(cast<LoadSDNode>(N), AM))
1163 case ISD::FrameIndex:
1164 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1165 AM.Base_Reg.getNode() == nullptr &&
1166 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) {
1167 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
1168 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
1174 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1)
1178 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
1179 unsigned Val = CN->getZExtValue();
1180 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
1181 // that the base operand remains free for further matching. If
1182 // the base doesn't end up getting used, a post-processing step
1183 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
1184 if (Val == 1 || Val == 2 || Val == 3) {
1185 AM.Scale = 1 << Val;
1186 SDValue ShVal = N.getNode()->getOperand(0);
1188 // Okay, we know that we have a scale by now. However, if the scaled
1189 // value is an add of something and a constant, we can fold the
1190 // constant into the disp field here.
1191 if (CurDAG->isBaseWithConstantOffset(ShVal)) {
1192 AM.IndexReg = ShVal.getNode()->getOperand(0);
1193 ConstantSDNode *AddVal =
1194 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
1195 uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val;
1196 if (!foldOffsetIntoAddress(Disp, AM))
1200 AM.IndexReg = ShVal;
1207 // Scale must not be used already.
1208 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1210 SDValue And = N.getOperand(0);
1211 if (And.getOpcode() != ISD::AND) break;
1212 SDValue X = And.getOperand(0);
1214 // We only handle up to 64-bit values here as those are what matter for
1215 // addressing mode optimizations.
1216 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1218 // The mask used for the transform is expected to be post-shift, but we
1219 // found the shift first so just apply the shift to the mask before passing
1221 if (!isa<ConstantSDNode>(N.getOperand(1)) ||
1222 !isa<ConstantSDNode>(And.getOperand(1)))
1224 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1);
1226 // Try to fold the mask and shift into the scale, and return false if we
1228 if (!foldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
1233 case ISD::SMUL_LOHI:
1234 case ISD::UMUL_LOHI:
1235 // A mul_lohi where we need the low part can be folded as a plain multiply.
1236 if (N.getResNo() != 0) break;
1239 case X86ISD::MUL_IMM:
1240 // X*[3,5,9] -> X+X*[2,4,8]
1241 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1242 AM.Base_Reg.getNode() == nullptr &&
1243 AM.IndexReg.getNode() == nullptr) {
1245 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
1246 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
1247 CN->getZExtValue() == 9) {
1248 AM.Scale = unsigned(CN->getZExtValue())-1;
1250 SDValue MulVal = N.getNode()->getOperand(0);
1253 // Okay, we know that we have a scale by now. However, if the scaled
1254 // value is an add of something and a constant, we can fold the
1255 // constant into the disp field here.
1256 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
1257 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
1258 Reg = MulVal.getNode()->getOperand(0);
1259 ConstantSDNode *AddVal =
1260 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
1261 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
1262 if (foldOffsetIntoAddress(Disp, AM))
1263 Reg = N.getNode()->getOperand(0);
1265 Reg = N.getNode()->getOperand(0);
1268 AM.IndexReg = AM.Base_Reg = Reg;
1275 // Given A-B, if A can be completely folded into the address and
1276 // the index field with the index field unused, use -B as the index.
1277 // This is a win if a has multiple parts that can be folded into
1278 // the address. Also, this saves a mov if the base register has
1279 // other uses, since it avoids a two-address sub instruction, however
1280 // it costs an additional mov if the index register has other uses.
1282 // Add an artificial use to this node so that we can keep track of
1283 // it if it gets CSE'd with a different node.
1284 HandleSDNode Handle(N);
1286 // Test if the LHS of the sub can be folded.
1287 X86ISelAddressMode Backup = AM;
1288 if (matchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1292 // Test if the index field is free for use.
1293 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1299 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
1300 // If the RHS involves a register with multiple uses, this
1301 // transformation incurs an extra mov, due to the neg instruction
1302 // clobbering its operand.
1303 if (!RHS.getNode()->hasOneUse() ||
1304 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1305 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1306 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1307 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1308 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1310 // If the base is a register with multiple uses, this
1311 // transformation may save a mov.
1312 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1313 AM.Base_Reg.getNode() &&
1314 !AM.Base_Reg.getNode()->hasOneUse()) ||
1315 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1317 // If the folded LHS was interesting, this transformation saves
1318 // address arithmetic.
1319 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1320 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1321 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1323 // If it doesn't look like it may be an overall win, don't do it.
1329 // Ok, the transformation is legal and appears profitable. Go for it.
1330 SDValue Zero = CurDAG->getConstant(0, dl, N.getValueType());
1331 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1335 // Insert the new nodes into the topological ordering.
1336 insertDAGNode(*CurDAG, N, Zero);
1337 insertDAGNode(*CurDAG, N, Neg);
1342 if (!matchAdd(N, AM, Depth))
1347 // We want to look through a transform in InstCombine and DAGCombiner that
1348 // turns 'add' into 'or', so we can treat this 'or' exactly like an 'add'.
1349 // Example: (or (and x, 1), (shl y, 3)) --> (add (and x, 1), (shl y, 3))
1350 // An 'lea' can then be used to match the shift (multiply) and add:
1352 // lea (%rsi, %rdi, 8), %rax
1353 if (CurDAG->haveNoCommonBitsSet(N.getOperand(0), N.getOperand(1)) &&
1354 !matchAdd(N, AM, Depth))
1359 // Perform some heroic transforms on an and of a constant-count shift
1360 // with a constant to enable use of the scaled offset field.
1362 // Scale must not be used already.
1363 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1365 SDValue Shift = N.getOperand(0);
1366 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
1367 SDValue X = Shift.getOperand(0);
1369 // We only handle up to 64-bit values here as those are what matter for
1370 // addressing mode optimizations.
1371 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1373 if (!isa<ConstantSDNode>(N.getOperand(1)))
1375 uint64_t Mask = N.getConstantOperandVal(1);
1377 // Try to fold the mask and shift into an extract and scale.
1378 if (!foldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
1381 // Try to fold the mask and shift directly into the scale.
1382 if (!foldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
1385 // Try to swap the mask and shift to place shifts which can be done as
1386 // a scale on the outside of the mask.
1387 if (!foldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
1393 return matchAddressBase(N, AM);
1396 /// Helper for MatchAddress. Add the specified node to the
1397 /// specified addressing mode without any further recursion.
1398 bool X86DAGToDAGISel::matchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1399 // Is the base register already occupied?
1400 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1401 // If so, check to see if the scale index register is set.
1402 if (!AM.IndexReg.getNode()) {
1408 // Otherwise, we cannot select it.
1412 // Default, generate it as a register.
1413 AM.BaseType = X86ISelAddressMode::RegBase;
1418 bool X86DAGToDAGISel::selectVectorAddr(SDNode *Parent, SDValue N, SDValue &Base,
1419 SDValue &Scale, SDValue &Index,
1420 SDValue &Disp, SDValue &Segment) {
1422 MaskedGatherScatterSDNode *Mgs = dyn_cast<MaskedGatherScatterSDNode>(Parent);
1425 X86ISelAddressMode AM;
1426 unsigned AddrSpace = Mgs->getPointerInfo().getAddrSpace();
1427 // AddrSpace 256 -> GS, 257 -> FS, 258 -> SS.
1428 if (AddrSpace == 256)
1429 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1430 if (AddrSpace == 257)
1431 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1432 if (AddrSpace == 258)
1433 AM.Segment = CurDAG->getRegister(X86::SS, MVT::i16);
1436 Base = Mgs->getBasePtr();
1437 Index = Mgs->getIndex();
1438 unsigned ScalarSize = Mgs->getValue().getValueType().getScalarSizeInBits();
1439 Scale = getI8Imm(ScalarSize/8, DL);
1441 // If Base is 0, the whole address is in index and the Scale is 1
1442 if (isa<ConstantSDNode>(Base)) {
1443 assert(cast<ConstantSDNode>(Base)->isNullValue() &&
1444 "Unexpected base in gather/scatter");
1445 Scale = getI8Imm(1, DL);
1446 Base = CurDAG->getRegister(0, MVT::i32);
1448 if (AM.Segment.getNode())
1449 Segment = AM.Segment;
1451 Segment = CurDAG->getRegister(0, MVT::i32);
1452 Disp = CurDAG->getTargetConstant(0, DL, MVT::i32);
1456 /// Returns true if it is able to pattern match an addressing mode.
1457 /// It returns the operands which make up the maximal addressing mode it can
1458 /// match by reference.
1460 /// Parent is the parent node of the addr operand that is being matched. It
1461 /// is always a load, store, atomic node, or null. It is only null when
1462 /// checking memory operands for inline asm nodes.
1463 bool X86DAGToDAGISel::selectAddr(SDNode *Parent, SDValue N, SDValue &Base,
1464 SDValue &Scale, SDValue &Index,
1465 SDValue &Disp, SDValue &Segment) {
1466 X86ISelAddressMode AM;
1469 // This list of opcodes are all the nodes that have an "addr:$ptr" operand
1470 // that are not a MemSDNode, and thus don't have proper addrspace info.
1471 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
1472 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
1473 Parent->getOpcode() != X86ISD::TLSCALL && // Fixme
1474 Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp
1475 Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp
1476 unsigned AddrSpace =
1477 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
1478 // AddrSpace 256 -> GS, 257 -> FS, 258 -> SS.
1479 if (AddrSpace == 256)
1480 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1481 if (AddrSpace == 257)
1482 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1483 if (AddrSpace == 258)
1484 AM.Segment = CurDAG->getRegister(X86::SS, MVT::i16);
1487 if (matchAddress(N, AM))
1490 MVT VT = N.getSimpleValueType();
1491 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1492 if (!AM.Base_Reg.getNode())
1493 AM.Base_Reg = CurDAG->getRegister(0, VT);
1496 if (!AM.IndexReg.getNode())
1497 AM.IndexReg = CurDAG->getRegister(0, VT);
1499 getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment);
1503 /// Match a scalar SSE load. In particular, we want to match a load whose top
1504 /// elements are either undef or zeros. The load flavor is derived from the
1505 /// type of N, which is either v4f32 or v2f64.
1508 /// PatternChainNode: this is the matched node that has a chain input and
1510 bool X86DAGToDAGISel::selectScalarSSELoad(SDNode *Root,
1511 SDValue N, SDValue &Base,
1512 SDValue &Scale, SDValue &Index,
1513 SDValue &Disp, SDValue &Segment,
1514 SDValue &PatternNodeWithChain) {
1515 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1516 PatternNodeWithChain = N.getOperand(0);
1517 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1518 PatternNodeWithChain.hasOneUse() &&
1519 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1520 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1521 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1522 if (!selectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1528 // Also handle the case where we explicitly require zeros in the top
1529 // elements. This is a vector shuffle from the zero vector.
1530 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1531 // Check to see if the top elements are all zeros (or bitcast of zeros).
1532 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1533 N.getOperand(0).getNode()->hasOneUse() &&
1534 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1535 N.getOperand(0).getOperand(0).hasOneUse() &&
1536 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1537 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1538 // Okay, this is a zero extending load. Fold it.
1539 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1540 if (!selectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1542 PatternNodeWithChain = SDValue(LD, 0);
1549 bool X86DAGToDAGISel::selectMOV64Imm32(SDValue N, SDValue &Imm) {
1550 if (const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1551 uint64_t ImmVal = CN->getZExtValue();
1552 if ((uint32_t)ImmVal != (uint64_t)ImmVal)
1555 Imm = CurDAG->getTargetConstant(ImmVal, SDLoc(N), MVT::i64);
1559 // In static codegen with small code model, we can get the address of a label
1560 // into a register with 'movl'. TableGen has already made sure we're looking
1561 // at a label of some kind.
1562 assert(N->getOpcode() == X86ISD::Wrapper &&
1563 "Unexpected node type for MOV32ri64");
1564 N = N.getOperand(0);
1566 if (N->getOpcode() != ISD::TargetConstantPool &&
1567 N->getOpcode() != ISD::TargetJumpTable &&
1568 N->getOpcode() != ISD::TargetGlobalAddress &&
1569 N->getOpcode() != ISD::TargetExternalSymbol &&
1570 N->getOpcode() != ISD::MCSymbol &&
1571 N->getOpcode() != ISD::TargetBlockAddress)
1575 return TM.getCodeModel() == CodeModel::Small;
1578 bool X86DAGToDAGISel::selectLEA64_32Addr(SDValue N, SDValue &Base,
1579 SDValue &Scale, SDValue &Index,
1580 SDValue &Disp, SDValue &Segment) {
1581 // Save the debug loc before calling selectLEAAddr, in case it invalidates N.
1584 if (!selectLEAAddr(N, Base, Scale, Index, Disp, Segment))
1587 RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Base);
1588 if (RN && RN->getReg() == 0)
1589 Base = CurDAG->getRegister(0, MVT::i64);
1590 else if (Base.getValueType() == MVT::i32 && !dyn_cast<FrameIndexSDNode>(Base)) {
1591 // Base could already be %rip, particularly in the x32 ABI.
1592 Base = SDValue(CurDAG->getMachineNode(
1593 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1594 CurDAG->getTargetConstant(0, DL, MVT::i64),
1596 CurDAG->getTargetConstant(X86::sub_32bit, DL, MVT::i32)),
1600 RN = dyn_cast<RegisterSDNode>(Index);
1601 if (RN && RN->getReg() == 0)
1602 Index = CurDAG->getRegister(0, MVT::i64);
1604 assert(Index.getValueType() == MVT::i32 &&
1605 "Expect to be extending 32-bit registers for use in LEA");
1606 Index = SDValue(CurDAG->getMachineNode(
1607 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1608 CurDAG->getTargetConstant(0, DL, MVT::i64),
1610 CurDAG->getTargetConstant(X86::sub_32bit, DL,
1618 /// Calls SelectAddr and determines if the maximal addressing
1619 /// mode it matches can be cost effectively emitted as an LEA instruction.
1620 bool X86DAGToDAGISel::selectLEAAddr(SDValue N,
1621 SDValue &Base, SDValue &Scale,
1622 SDValue &Index, SDValue &Disp,
1624 X86ISelAddressMode AM;
1626 // Save the DL and VT before calling matchAddress, it can invalidate N.
1628 MVT VT = N.getSimpleValueType();
1630 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1632 SDValue Copy = AM.Segment;
1633 SDValue T = CurDAG->getRegister(0, MVT::i32);
1635 if (matchAddress(N, AM))
1637 assert (T == AM.Segment);
1640 unsigned Complexity = 0;
1641 if (AM.BaseType == X86ISelAddressMode::RegBase)
1642 if (AM.Base_Reg.getNode())
1645 AM.Base_Reg = CurDAG->getRegister(0, VT);
1646 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1649 if (AM.IndexReg.getNode())
1652 AM.IndexReg = CurDAG->getRegister(0, VT);
1654 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1659 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1660 // to a LEA. This is determined with some experimentation but is by no means
1661 // optimal (especially for code size consideration). LEA is nice because of
1662 // its three-address nature. Tweak the cost function again when we can run
1663 // convertToThreeAddress() at register allocation time.
1664 if (AM.hasSymbolicDisplacement()) {
1665 // For X86-64, always use LEA to materialize RIP-relative addresses.
1666 if (Subtarget->is64Bit())
1672 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1675 // If it isn't worth using an LEA, reject it.
1676 if (Complexity <= 2)
1679 getAddressOperands(AM, DL, Base, Scale, Index, Disp, Segment);
1683 /// This is only run on TargetGlobalTLSAddress nodes.
1684 bool X86DAGToDAGISel::selectTLSADDRAddr(SDValue N, SDValue &Base,
1685 SDValue &Scale, SDValue &Index,
1686 SDValue &Disp, SDValue &Segment) {
1687 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1688 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1690 X86ISelAddressMode AM;
1691 AM.GV = GA->getGlobal();
1692 AM.Disp += GA->getOffset();
1693 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1694 AM.SymbolFlags = GA->getTargetFlags();
1696 if (N.getValueType() == MVT::i32) {
1698 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1700 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1703 getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment);
1708 bool X86DAGToDAGISel::tryFoldLoad(SDNode *P, SDValue N,
1709 SDValue &Base, SDValue &Scale,
1710 SDValue &Index, SDValue &Disp,
1712 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1713 !IsProfitableToFold(N, P, P) ||
1714 !IsLegalToFold(N, P, P, OptLevel))
1717 return selectAddr(N.getNode(),
1718 N.getOperand(1), Base, Scale, Index, Disp, Segment);
1721 /// Return an SDNode that returns the value of the global base register.
1722 /// Output instructions required to initialize the global base register,
1724 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1725 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1726 auto &DL = MF->getDataLayout();
1727 return CurDAG->getRegister(GlobalBaseReg, TLI->getPointerTy(DL)).getNode();
1730 /// Test whether the given X86ISD::CMP node has any uses which require the SF
1731 /// or OF bits to be accurate.
1732 static bool hasNoSignedComparisonUses(SDNode *N) {
1733 // Examine each user of the node.
1734 for (SDNode::use_iterator UI = N->use_begin(),
1735 UE = N->use_end(); UI != UE; ++UI) {
1736 // Only examine CopyToReg uses.
1737 if (UI->getOpcode() != ISD::CopyToReg)
1739 // Only examine CopyToReg uses that copy to EFLAGS.
1740 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1743 // Examine each user of the CopyToReg use.
1744 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1745 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1746 // Only examine the Flag result.
1747 if (FlagUI.getUse().getResNo() != 1) continue;
1748 // Anything unusual: assume conservatively.
1749 if (!FlagUI->isMachineOpcode()) return false;
1750 // Examine the opcode of the user.
1751 switch (FlagUI->getMachineOpcode()) {
1752 // These comparisons don't treat the most significant bit specially.
1753 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1754 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1755 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1756 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1757 case X86::JA_1: case X86::JAE_1: case X86::JB_1: case X86::JBE_1:
1758 case X86::JE_1: case X86::JNE_1: case X86::JP_1: case X86::JNP_1:
1759 case X86::CMOVA16rr: case X86::CMOVA16rm:
1760 case X86::CMOVA32rr: case X86::CMOVA32rm:
1761 case X86::CMOVA64rr: case X86::CMOVA64rm:
1762 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1763 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1764 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1765 case X86::CMOVB16rr: case X86::CMOVB16rm:
1766 case X86::CMOVB32rr: case X86::CMOVB32rm:
1767 case X86::CMOVB64rr: case X86::CMOVB64rm:
1768 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1769 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1770 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1771 case X86::CMOVE16rr: case X86::CMOVE16rm:
1772 case X86::CMOVE32rr: case X86::CMOVE32rm:
1773 case X86::CMOVE64rr: case X86::CMOVE64rm:
1774 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1775 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1776 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1777 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1778 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1779 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1780 case X86::CMOVP16rr: case X86::CMOVP16rm:
1781 case X86::CMOVP32rr: case X86::CMOVP32rm:
1782 case X86::CMOVP64rr: case X86::CMOVP64rm:
1784 // Anything else: assume conservatively.
1785 default: return false;
1792 /// Check whether or not the chain ending in StoreNode is suitable for doing
1793 /// the {load; increment or decrement; store} to modify transformation.
1794 static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc,
1795 SDValue StoredVal, SelectionDAG *CurDAG,
1796 LoadSDNode* &LoadNode, SDValue &InputChain) {
1798 // is the value stored the result of a DEC or INC?
1799 if (!(Opc == X86ISD::DEC || Opc == X86ISD::INC)) return false;
1801 // is the stored value result 0 of the load?
1802 if (StoredVal.getResNo() != 0) return false;
1804 // are there other uses of the loaded value than the inc or dec?
1805 if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) return false;
1807 // is the store non-extending and non-indexed?
1808 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
1811 SDValue Load = StoredVal->getOperand(0);
1812 // Is the stored value a non-extending and non-indexed load?
1813 if (!ISD::isNormalLoad(Load.getNode())) return false;
1815 // Return LoadNode by reference.
1816 LoadNode = cast<LoadSDNode>(Load);
1817 // is the size of the value one that we can handle? (i.e. 64, 32, 16, or 8)
1818 EVT LdVT = LoadNode->getMemoryVT();
1819 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
1823 // Is store the only read of the loaded value?
1824 if (!Load.hasOneUse())
1827 // Is the address of the store the same as the load?
1828 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
1829 LoadNode->getOffset() != StoreNode->getOffset())
1832 // Check if the chain is produced by the load or is a TokenFactor with
1833 // the load output chain as an operand. Return InputChain by reference.
1834 SDValue Chain = StoreNode->getChain();
1836 bool ChainCheck = false;
1837 if (Chain == Load.getValue(1)) {
1839 InputChain = LoadNode->getChain();
1840 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1841 SmallVector<SDValue, 4> ChainOps;
1842 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) {
1843 SDValue Op = Chain.getOperand(i);
1844 if (Op == Load.getValue(1)) {
1849 // Make sure using Op as part of the chain would not cause a cycle here.
1850 // In theory, we could check whether the chain node is a predecessor of
1851 // the load. But that can be very expensive. Instead visit the uses and
1852 // make sure they all have smaller node id than the load.
1853 int LoadId = LoadNode->getNodeId();
1854 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
1855 UE = UI->use_end(); UI != UE; ++UI) {
1856 if (UI.getUse().getResNo() != 0)
1858 if (UI->getNodeId() > LoadId)
1862 ChainOps.push_back(Op);
1866 // Make a new TokenFactor with all the other input chains except
1868 InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
1869 MVT::Other, ChainOps);
1877 /// Get the appropriate X86 opcode for an in-memory increment or decrement.
1878 /// Opc should be X86ISD::DEC or X86ISD::INC.
1879 static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
1880 if (Opc == X86ISD::DEC) {
1881 if (LdVT == MVT::i64) return X86::DEC64m;
1882 if (LdVT == MVT::i32) return X86::DEC32m;
1883 if (LdVT == MVT::i16) return X86::DEC16m;
1884 if (LdVT == MVT::i8) return X86::DEC8m;
1886 assert(Opc == X86ISD::INC && "unrecognized opcode");
1887 if (LdVT == MVT::i64) return X86::INC64m;
1888 if (LdVT == MVT::i32) return X86::INC32m;
1889 if (LdVT == MVT::i16) return X86::INC16m;
1890 if (LdVT == MVT::i8) return X86::INC8m;
1892 llvm_unreachable("unrecognized size for LdVT");
1895 /// Customized ISel for GATHER operations.
1896 bool X86DAGToDAGISel::tryGather(SDNode *Node, unsigned Opc) {
1897 // Operands of Gather: VSrc, Base, VIdx, VMask, Scale
1898 SDValue Chain = Node->getOperand(0);
1899 SDValue VSrc = Node->getOperand(2);
1900 SDValue Base = Node->getOperand(3);
1901 SDValue VIdx = Node->getOperand(4);
1902 SDValue VMask = Node->getOperand(5);
1903 ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6));
1907 SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(),
1912 // Memory Operands: Base, Scale, Index, Disp, Segment
1913 SDValue Disp = CurDAG->getTargetConstant(0, DL, MVT::i32);
1914 SDValue Segment = CurDAG->getRegister(0, MVT::i32);
1915 const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue(), DL), VIdx,
1916 Disp, Segment, VMask, Chain};
1917 SDNode *ResNode = CurDAG->getMachineNode(Opc, DL, VTs, Ops);
1918 // Node has 2 outputs: VDst and MVT::Other.
1919 // ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.
1920 // We replace VDst of Node with VDst of ResNode, and Other of Node with Other
1922 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
1923 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 2));
1924 CurDAG->RemoveDeadNode(Node);
1928 void X86DAGToDAGISel::Select(SDNode *Node) {
1929 MVT NVT = Node->getSimpleValueType(0);
1931 unsigned Opcode = Node->getOpcode();
1934 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
1936 if (Node->isMachineOpcode()) {
1937 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
1938 Node->setNodeId(-1);
1939 return; // Already selected.
1945 if (Subtarget->isTargetNaCl())
1946 // NaCl has its own pass where jmp %r32 are converted to jmp %r64. We
1947 // leave the instruction alone.
1949 if (Subtarget->isTarget64BitILP32()) {
1950 // Converts a 32-bit register to a 64-bit, zero-extended version of
1951 // it. This is needed because x86-64 can do many things, but jmp %r32
1952 // ain't one of them.
1953 const SDValue &Target = Node->getOperand(1);
1954 assert(Target.getSimpleValueType() == llvm::MVT::i32);
1955 SDValue ZextTarget = CurDAG->getZExtOrTrunc(Target, dl, EVT(MVT::i64));
1956 SDValue Brind = CurDAG->getNode(ISD::BRIND, dl, MVT::Other,
1957 Node->getOperand(0), ZextTarget);
1958 ReplaceNode(Node, Brind.getNode());
1959 SelectCode(ZextTarget.getNode());
1960 SelectCode(Brind.getNode());
1965 case ISD::INTRINSIC_W_CHAIN: {
1966 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
1969 case Intrinsic::x86_avx2_gather_d_pd:
1970 case Intrinsic::x86_avx2_gather_d_pd_256:
1971 case Intrinsic::x86_avx2_gather_q_pd:
1972 case Intrinsic::x86_avx2_gather_q_pd_256:
1973 case Intrinsic::x86_avx2_gather_d_ps:
1974 case Intrinsic::x86_avx2_gather_d_ps_256:
1975 case Intrinsic::x86_avx2_gather_q_ps:
1976 case Intrinsic::x86_avx2_gather_q_ps_256:
1977 case Intrinsic::x86_avx2_gather_d_q:
1978 case Intrinsic::x86_avx2_gather_d_q_256:
1979 case Intrinsic::x86_avx2_gather_q_q:
1980 case Intrinsic::x86_avx2_gather_q_q_256:
1981 case Intrinsic::x86_avx2_gather_d_d:
1982 case Intrinsic::x86_avx2_gather_d_d_256:
1983 case Intrinsic::x86_avx2_gather_q_d:
1984 case Intrinsic::x86_avx2_gather_q_d_256: {
1985 if (!Subtarget->hasAVX2())
1989 default: llvm_unreachable("Impossible intrinsic");
1990 case Intrinsic::x86_avx2_gather_d_pd: Opc = X86::VGATHERDPDrm; break;
1991 case Intrinsic::x86_avx2_gather_d_pd_256: Opc = X86::VGATHERDPDYrm; break;
1992 case Intrinsic::x86_avx2_gather_q_pd: Opc = X86::VGATHERQPDrm; break;
1993 case Intrinsic::x86_avx2_gather_q_pd_256: Opc = X86::VGATHERQPDYrm; break;
1994 case Intrinsic::x86_avx2_gather_d_ps: Opc = X86::VGATHERDPSrm; break;
1995 case Intrinsic::x86_avx2_gather_d_ps_256: Opc = X86::VGATHERDPSYrm; break;
1996 case Intrinsic::x86_avx2_gather_q_ps: Opc = X86::VGATHERQPSrm; break;
1997 case Intrinsic::x86_avx2_gather_q_ps_256: Opc = X86::VGATHERQPSYrm; break;
1998 case Intrinsic::x86_avx2_gather_d_q: Opc = X86::VPGATHERDQrm; break;
1999 case Intrinsic::x86_avx2_gather_d_q_256: Opc = X86::VPGATHERDQYrm; break;
2000 case Intrinsic::x86_avx2_gather_q_q: Opc = X86::VPGATHERQQrm; break;
2001 case Intrinsic::x86_avx2_gather_q_q_256: Opc = X86::VPGATHERQQYrm; break;
2002 case Intrinsic::x86_avx2_gather_d_d: Opc = X86::VPGATHERDDrm; break;
2003 case Intrinsic::x86_avx2_gather_d_d_256: Opc = X86::VPGATHERDDYrm; break;
2004 case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break;
2005 case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break;
2007 if (tryGather(Node, Opc))
2014 case X86ISD::GlobalBaseReg:
2015 ReplaceNode(Node, getGlobalBaseReg());
2018 case X86ISD::SHRUNKBLEND: {
2019 // SHRUNKBLEND selects like a regular VSELECT.
2020 SDValue VSelect = CurDAG->getNode(
2021 ISD::VSELECT, SDLoc(Node), Node->getValueType(0), Node->getOperand(0),
2022 Node->getOperand(1), Node->getOperand(2));
2023 ReplaceUses(SDValue(Node, 0), VSelect);
2024 SelectCode(VSelect.getNode());
2025 // We already called ReplaceUses.
2032 // For operations of the form (x << C1) op C2, check if we can use a smaller
2033 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
2034 SDValue N0 = Node->getOperand(0);
2035 SDValue N1 = Node->getOperand(1);
2037 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
2040 // i8 is unshrinkable, i16 should be promoted to i32.
2041 if (NVT != MVT::i32 && NVT != MVT::i64)
2044 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
2045 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
2046 if (!Cst || !ShlCst)
2049 int64_t Val = Cst->getSExtValue();
2050 uint64_t ShlVal = ShlCst->getZExtValue();
2052 // Make sure that we don't change the operation by removing bits.
2053 // This only matters for OR and XOR, AND is unaffected.
2054 uint64_t RemovedBitsMask = (1ULL << ShlVal) - 1;
2055 if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
2058 unsigned ShlOp, AddOp, Op;
2061 // Check the minimum bitwidth for the new constant.
2062 // TODO: AND32ri is the same as AND64ri32 with zext imm.
2063 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
2064 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
2065 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
2067 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
2070 // Bail if there is no smaller encoding.
2074 switch (NVT.SimpleTy) {
2075 default: llvm_unreachable("Unsupported VT!");
2077 assert(CstVT == MVT::i8);
2078 ShlOp = X86::SHL32ri;
2079 AddOp = X86::ADD32rr;
2082 default: llvm_unreachable("Impossible opcode");
2083 case ISD::AND: Op = X86::AND32ri8; break;
2084 case ISD::OR: Op = X86::OR32ri8; break;
2085 case ISD::XOR: Op = X86::XOR32ri8; break;
2089 assert(CstVT == MVT::i8 || CstVT == MVT::i32);
2090 ShlOp = X86::SHL64ri;
2091 AddOp = X86::ADD64rr;
2094 default: llvm_unreachable("Impossible opcode");
2095 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
2096 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
2097 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
2102 // Emit the smaller op and the shift.
2103 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, dl, CstVT);
2104 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
2106 CurDAG->SelectNodeTo(Node, AddOp, NVT, SDValue(New, 0),
2109 CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
2110 getI8Imm(ShlVal, dl));
2114 case X86ISD::SMUL8: {
2115 SDValue N0 = Node->getOperand(0);
2116 SDValue N1 = Node->getOperand(1);
2118 Opc = (Opcode == X86ISD::SMUL8 ? X86::IMUL8r : X86::MUL8r);
2120 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, X86::AL,
2121 N0, SDValue()).getValue(1);
2123 SDVTList VTs = CurDAG->getVTList(NVT, MVT::i32);
2124 SDValue Ops[] = {N1, InFlag};
2125 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2127 ReplaceNode(Node, CNode);
2131 case X86ISD::UMUL: {
2132 SDValue N0 = Node->getOperand(0);
2133 SDValue N1 = Node->getOperand(1);
2136 switch (NVT.SimpleTy) {
2137 default: llvm_unreachable("Unsupported VT!");
2138 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
2139 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
2140 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
2141 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
2144 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
2145 N0, SDValue()).getValue(1);
2147 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32);
2148 SDValue Ops[] = {N1, InFlag};
2149 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2151 ReplaceNode(Node, CNode);
2155 case ISD::SMUL_LOHI:
2156 case ISD::UMUL_LOHI: {
2157 SDValue N0 = Node->getOperand(0);
2158 SDValue N1 = Node->getOperand(1);
2160 bool isSigned = Opcode == ISD::SMUL_LOHI;
2161 bool hasBMI2 = Subtarget->hasBMI2();
2163 switch (NVT.SimpleTy) {
2164 default: llvm_unreachable("Unsupported VT!");
2165 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
2166 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
2167 case MVT::i32: Opc = hasBMI2 ? X86::MULX32rr : X86::MUL32r;
2168 MOpc = hasBMI2 ? X86::MULX32rm : X86::MUL32m; break;
2169 case MVT::i64: Opc = hasBMI2 ? X86::MULX64rr : X86::MUL64r;
2170 MOpc = hasBMI2 ? X86::MULX64rm : X86::MUL64m; break;
2173 switch (NVT.SimpleTy) {
2174 default: llvm_unreachable("Unsupported VT!");
2175 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
2176 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
2177 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
2178 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
2182 unsigned SrcReg, LoReg, HiReg;
2184 default: llvm_unreachable("Unknown MUL opcode!");
2187 SrcReg = LoReg = X86::AL; HiReg = X86::AH;
2191 SrcReg = LoReg = X86::AX; HiReg = X86::DX;
2195 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX;
2199 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
2202 SrcReg = X86::EDX; LoReg = HiReg = 0;
2205 SrcReg = X86::RDX; LoReg = HiReg = 0;
2209 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2210 bool foldedLoad = tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2211 // Multiply is commmutative.
2213 foldedLoad = tryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2218 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SrcReg,
2219 N0, SDValue()).getValue(1);
2220 SDValue ResHi, ResLo;
2224 MachineSDNode *CNode = nullptr;
2225 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2227 if (MOpc == X86::MULX32rm || MOpc == X86::MULX64rm) {
2228 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Other, MVT::Glue);
2229 CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2230 ResHi = SDValue(CNode, 0);
2231 ResLo = SDValue(CNode, 1);
2232 Chain = SDValue(CNode, 2);
2233 InFlag = SDValue(CNode, 3);
2235 SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
2236 CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2237 Chain = SDValue(CNode, 0);
2238 InFlag = SDValue(CNode, 1);
2241 // Update the chain.
2242 ReplaceUses(N1.getValue(1), Chain);
2243 // Record the mem-refs
2244 LoadSDNode *LoadNode = cast<LoadSDNode>(N1);
2246 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2247 MemOp[0] = LoadNode->getMemOperand();
2248 CNode->setMemRefs(MemOp, MemOp + 1);
2251 SDValue Ops[] = { N1, InFlag };
2252 if (Opc == X86::MULX32rr || Opc == X86::MULX64rr) {
2253 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Glue);
2254 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2255 ResHi = SDValue(CNode, 0);
2256 ResLo = SDValue(CNode, 1);
2257 InFlag = SDValue(CNode, 2);
2259 SDVTList VTs = CurDAG->getVTList(MVT::Glue);
2260 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2261 InFlag = SDValue(CNode, 0);
2265 // Prevent use of AH in a REX instruction by referencing AX instead.
2266 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2267 !SDValue(Node, 1).use_empty()) {
2268 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2269 X86::AX, MVT::i16, InFlag);
2270 InFlag = Result.getValue(2);
2271 // Get the low part if needed. Don't use getCopyFromReg for aliasing
2273 if (!SDValue(Node, 0).use_empty())
2274 ReplaceUses(SDValue(Node, 1),
2275 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2277 // Shift AX down 8 bits.
2278 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2280 CurDAG->getTargetConstant(8, dl, MVT::i8)),
2282 // Then truncate it down to i8.
2283 ReplaceUses(SDValue(Node, 1),
2284 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2286 // Copy the low half of the result, if it is needed.
2287 if (!SDValue(Node, 0).use_empty()) {
2288 if (!ResLo.getNode()) {
2289 assert(LoReg && "Register for low half is not defined!");
2290 ResLo = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, LoReg, NVT,
2292 InFlag = ResLo.getValue(2);
2294 ReplaceUses(SDValue(Node, 0), ResLo);
2295 DEBUG(dbgs() << "=> "; ResLo.getNode()->dump(CurDAG); dbgs() << '\n');
2297 // Copy the high half of the result, if it is needed.
2298 if (!SDValue(Node, 1).use_empty()) {
2299 if (!ResHi.getNode()) {
2300 assert(HiReg && "Register for high half is not defined!");
2301 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT,
2303 InFlag = ResHi.getValue(2);
2305 ReplaceUses(SDValue(Node, 1), ResHi);
2306 DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); dbgs() << '\n');
2314 case X86ISD::SDIVREM8_SEXT_HREG:
2315 case X86ISD::UDIVREM8_ZEXT_HREG: {
2316 SDValue N0 = Node->getOperand(0);
2317 SDValue N1 = Node->getOperand(1);
2319 bool isSigned = (Opcode == ISD::SDIVREM ||
2320 Opcode == X86ISD::SDIVREM8_SEXT_HREG);
2322 switch (NVT.SimpleTy) {
2323 default: llvm_unreachable("Unsupported VT!");
2324 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
2325 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
2326 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
2327 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
2330 switch (NVT.SimpleTy) {
2331 default: llvm_unreachable("Unsupported VT!");
2332 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
2333 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
2334 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
2335 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
2339 unsigned LoReg, HiReg, ClrReg;
2340 unsigned SExtOpcode;
2341 switch (NVT.SimpleTy) {
2342 default: llvm_unreachable("Unsupported VT!");
2344 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
2345 SExtOpcode = X86::CBW;
2348 LoReg = X86::AX; HiReg = X86::DX;
2350 SExtOpcode = X86::CWD;
2353 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
2354 SExtOpcode = X86::CDQ;
2357 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
2358 SExtOpcode = X86::CQO;
2362 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2363 bool foldedLoad = tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2364 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
2367 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
2368 // Special case for div8, just use a move with zero extension to AX to
2369 // clear the upper 8 bits (AH).
2370 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
2371 if (tryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
2372 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
2374 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
2375 MVT::Other, Ops), 0);
2376 Chain = Move.getValue(1);
2377 ReplaceUses(N0.getValue(1), Chain);
2380 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
2381 Chain = CurDAG->getEntryNode();
2383 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
2384 InFlag = Chain.getValue(1);
2387 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2388 LoReg, N0, SDValue()).getValue(1);
2389 if (isSigned && !signBitIsZero) {
2390 // Sign extend the low part into the high part.
2392 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0);
2394 // Zero out the high part, effectively zero extending the input.
2395 SDValue ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, NVT), 0);
2396 switch (NVT.SimpleTy) {
2399 SDValue(CurDAG->getMachineNode(
2400 TargetOpcode::EXTRACT_SUBREG, dl, MVT::i16, ClrNode,
2401 CurDAG->getTargetConstant(X86::sub_16bit, dl,
2409 SDValue(CurDAG->getMachineNode(
2410 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2411 CurDAG->getTargetConstant(0, dl, MVT::i64), ClrNode,
2412 CurDAG->getTargetConstant(X86::sub_32bit, dl,
2417 llvm_unreachable("Unexpected division source");
2420 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
2421 ClrNode, InFlag).getValue(1);
2426 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2429 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops);
2430 InFlag = SDValue(CNode, 1);
2431 // Update the chain.
2432 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2435 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0);
2438 // Prevent use of AH in a REX instruction by explicitly copying it to
2439 // an ABCD_L register.
2441 // The current assumption of the register allocator is that isel
2442 // won't generate explicit references to the GR8_ABCD_H registers. If
2443 // the allocator and/or the backend get enhanced to be more robust in
2444 // that regard, this can be, and should be, removed.
2445 if (HiReg == X86::AH && !SDValue(Node, 1).use_empty()) {
2446 SDValue AHCopy = CurDAG->getRegister(X86::AH, MVT::i8);
2447 unsigned AHExtOpcode =
2448 isSigned ? X86::MOVSX32_NOREXrr8 : X86::MOVZX32_NOREXrr8;
2450 SDNode *RNode = CurDAG->getMachineNode(AHExtOpcode, dl, MVT::i32,
2451 MVT::Glue, AHCopy, InFlag);
2452 SDValue Result(RNode, 0);
2453 InFlag = SDValue(RNode, 1);
2455 if (Opcode == X86ISD::UDIVREM8_ZEXT_HREG ||
2456 Opcode == X86ISD::SDIVREM8_SEXT_HREG) {
2457 if (Node->getValueType(1) == MVT::i64) {
2458 // It's not possible to directly movsx AH to a 64bit register, because
2459 // the latter needs the REX prefix, but the former can't have it.
2460 assert(Opcode != X86ISD::SDIVREM8_SEXT_HREG &&
2461 "Unexpected i64 sext of h-register");
2463 SDValue(CurDAG->getMachineNode(
2464 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2465 CurDAG->getTargetConstant(0, dl, MVT::i64), Result,
2466 CurDAG->getTargetConstant(X86::sub_32bit, dl,
2472 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result);
2474 ReplaceUses(SDValue(Node, 1), Result);
2475 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2477 // Copy the division (low) result, if it is needed.
2478 if (!SDValue(Node, 0).use_empty()) {
2479 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2480 LoReg, NVT, InFlag);
2481 InFlag = Result.getValue(2);
2482 ReplaceUses(SDValue(Node, 0), Result);
2483 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2485 // Copy the remainder (high) result, if it is needed.
2486 if (!SDValue(Node, 1).use_empty()) {
2487 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2488 HiReg, NVT, InFlag);
2489 InFlag = Result.getValue(2);
2490 ReplaceUses(SDValue(Node, 1), Result);
2491 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2498 // Sometimes a SUB is used to perform comparison.
2499 if (Opcode == X86ISD::SUB && Node->hasAnyUseOfValue(0))
2500 // This node is not a CMP.
2502 SDValue N0 = Node->getOperand(0);
2503 SDValue N1 = Node->getOperand(1);
2505 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
2506 hasNoSignedComparisonUses(Node))
2507 N0 = N0.getOperand(0);
2509 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2510 // use a smaller encoding.
2511 // Look past the truncate if CMP is the only use of it.
2512 if ((N0.getNode()->getOpcode() == ISD::AND ||
2513 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
2514 N0.getNode()->hasOneUse() &&
2515 N0.getValueType() != MVT::i8 &&
2516 X86::isZeroNode(N1)) {
2517 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2520 // For example, convert "testl %eax, $8" to "testb %al, $8"
2521 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2522 (!(C->getZExtValue() & 0x80) ||
2523 hasNoSignedComparisonUses(Node))) {
2524 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl, MVT::i8);
2525 SDValue Reg = N0.getNode()->getOperand(0);
2527 // On x86-32, only the ABCD registers have 8-bit subregisters.
2528 if (!Subtarget->is64Bit()) {
2529 const TargetRegisterClass *TRC;
2530 switch (N0.getSimpleValueType().SimpleTy) {
2531 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2532 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2533 default: llvm_unreachable("Unsupported TEST operand type!");
2535 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
2536 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2537 Reg.getValueType(), Reg, RC), 0);
2540 // Extract the l-register.
2541 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
2545 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
2547 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2548 // one, do not call ReplaceAllUsesWith.
2549 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2550 SDValue(NewNode, 0));
2554 // For example, "testl %eax, $2048" to "testb %ah, $8".
2555 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2556 (!(C->getZExtValue() & 0x8000) ||
2557 hasNoSignedComparisonUses(Node))) {
2558 // Shift the immediate right by 8 bits.
2559 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2561 SDValue Reg = N0.getNode()->getOperand(0);
2563 // Put the value in an ABCD register.
2564 const TargetRegisterClass *TRC;
2565 switch (N0.getSimpleValueType().SimpleTy) {
2566 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2567 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2568 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2569 default: llvm_unreachable("Unsupported TEST operand type!");
2571 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
2572 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2573 Reg.getValueType(), Reg, RC), 0);
2575 // Extract the h-register.
2576 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
2579 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only
2580 // target GR8_NOREX registers, so make sure the register class is
2582 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl,
2583 MVT::i32, Subreg, ShiftedImm);
2584 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2585 // one, do not call ReplaceAllUsesWith.
2586 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2587 SDValue(NewNode, 0));
2591 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2592 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2593 N0.getValueType() != MVT::i16 &&
2594 (!(C->getZExtValue() & 0x8000) ||
2595 hasNoSignedComparisonUses(Node))) {
2596 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl,
2598 SDValue Reg = N0.getNode()->getOperand(0);
2600 // Extract the 16-bit subregister.
2601 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
2605 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32,
2607 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2608 // one, do not call ReplaceAllUsesWith.
2609 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2610 SDValue(NewNode, 0));
2614 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2615 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2616 N0.getValueType() == MVT::i64 &&
2617 (!(C->getZExtValue() & 0x80000000) ||
2618 hasNoSignedComparisonUses(Node))) {
2619 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl,
2621 SDValue Reg = N0.getNode()->getOperand(0);
2623 // Extract the 32-bit subregister.
2624 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
2628 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32,
2630 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2631 // one, do not call ReplaceAllUsesWith.
2632 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2633 SDValue(NewNode, 0));
2640 // Change a chain of {load; incr or dec; store} of the same value into
2641 // a simple increment or decrement through memory of that value, if the
2642 // uses of the modified value and its address are suitable.
2643 // The DEC64m tablegen pattern is currently not able to match the case where
2644 // the EFLAGS on the original DEC are used. (This also applies to
2645 // {INC,DEC}X{64,32,16,8}.)
2646 // We'll need to improve tablegen to allow flags to be transferred from a
2647 // node in the pattern to the result node. probably with a new keyword
2648 // for example, we have this
2649 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2650 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2651 // (implicit EFLAGS)]>;
2652 // but maybe need something like this
2653 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2654 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2655 // (transferrable EFLAGS)]>;
2657 StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
2658 SDValue StoredVal = StoreNode->getOperand(1);
2659 unsigned Opc = StoredVal->getOpcode();
2661 LoadSDNode *LoadNode = nullptr;
2663 if (!isLoadIncOrDecStore(StoreNode, Opc, StoredVal, CurDAG,
2664 LoadNode, InputChain))
2667 SDValue Base, Scale, Index, Disp, Segment;
2668 if (!selectAddr(LoadNode, LoadNode->getBasePtr(),
2669 Base, Scale, Index, Disp, Segment))
2672 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
2673 MemOp[0] = StoreNode->getMemOperand();
2674 MemOp[1] = LoadNode->getMemOperand();
2675 const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
2676 EVT LdVT = LoadNode->getMemoryVT();
2677 unsigned newOpc = getFusedLdStOpcode(LdVT, Opc);
2678 MachineSDNode *Result = CurDAG->getMachineNode(newOpc,
2680 MVT::i32, MVT::Other, Ops);
2681 Result->setMemRefs(MemOp, MemOp + 2);
2683 ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
2684 ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
2685 CurDAG->RemoveDeadNode(Node);
2693 bool X86DAGToDAGISel::
2694 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
2695 std::vector<SDValue> &OutOps) {
2696 SDValue Op0, Op1, Op2, Op3, Op4;
2697 switch (ConstraintID) {
2699 llvm_unreachable("Unexpected asm memory constraint");
2700 case InlineAsm::Constraint_i:
2701 // FIXME: It seems strange that 'i' is needed here since it's supposed to
2702 // be an immediate and not a memory constraint.
2704 case InlineAsm::Constraint_o: // offsetable ??
2705 case InlineAsm::Constraint_v: // not offsetable ??
2706 case InlineAsm::Constraint_m: // memory
2707 case InlineAsm::Constraint_X:
2708 if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
2713 OutOps.push_back(Op0);
2714 OutOps.push_back(Op1);
2715 OutOps.push_back(Op2);
2716 OutOps.push_back(Op3);
2717 OutOps.push_back(Op4);
2721 /// This pass converts a legalized DAG into a X86-specific DAG,
2722 /// ready for instruction scheduling.
2723 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2724 CodeGenOpt::Level OptLevel) {
2725 return new X86DAGToDAGISel(TM, OptLevel);