1 //===-- X86Instr3DNow.td - The 3DNow! Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the 3DNow! instruction set, which extends MMX to support
11 // floating point and also adds a few more random instructions for good measure.
13 //===----------------------------------------------------------------------===//
15 class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pat>
16 : I<o, F, outs, ins, asm, pat>, TB, Requires<[Has3DNow]> {
19 class I3DNow_binop<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat>
20 : I3DNow<o, F, (outs VR64:$dst), ins,
21 !strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), pat>,
23 // FIXME: The disassembler doesn't support Has3DNow0F0FOpcode yet.
24 let isAsmParserOnly = 1;
25 let Constraints = "$src1 = $dst";
28 class I3DNow_conv<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat>
29 : I3DNow<o, F, (outs VR64:$dst), ins,
30 !strconcat(Mnemonic, "\t{$src, $dst|$dst, $src}"), pat>,
32 // FIXME: The disassembler doesn't support Has3DNow0F0FOpcode yet.
33 let isAsmParserOnly = 1;
36 multiclass I3DNow_binop_rm<bits<8> opc, string Mn> {
37 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, []>;
38 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn, []>;
41 multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn, bit Commutable = 0,
43 let isCommutable = Commutable in
44 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
45 [(set VR64:$dst, (!cast<Intrinsic>(
46 !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, VR64:$src2))]>;
47 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn,
48 [(set VR64:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1,
50 (bitconvert (load_mmx addr:$src2))))]>;
53 multiclass I3DNow_conv_rm<bits<8> opc, string Mn> {
54 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src1), Mn, []>;
55 def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src1), Mn, []>;
58 multiclass I3DNow_conv_rm_int<bits<8> opc, string Mn, string Ver = ""> {
59 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn,
60 [(set VR64:$dst, (!cast<Intrinsic>(
61 !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src))]>;
62 def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src), Mn,
63 [(set VR64:$dst, (!cast<Intrinsic>(
64 !strconcat("int_x86_3dnow", Ver, "_", Mn))
65 (bitconvert (load_mmx addr:$src))))]>;
68 defm PAVGUSB : I3DNow_binop_rm_int<0xBF, "pavgusb", 1>;
69 defm PF2ID : I3DNow_conv_rm_int<0x1D, "pf2id">;
70 defm PFACC : I3DNow_binop_rm_int<0xAE, "pfacc">;
71 defm PFADD : I3DNow_binop_rm_int<0x9E, "pfadd", 1>;
72 defm PFCMPEQ : I3DNow_binop_rm_int<0xB0, "pfcmpeq", 1>;
73 defm PFCMPGE : I3DNow_binop_rm_int<0x90, "pfcmpge">;
74 defm PFCMPGT : I3DNow_binop_rm_int<0xA0, "pfcmpgt">;
75 defm PFMAX : I3DNow_binop_rm_int<0xA4, "pfmax">;
76 defm PFMIN : I3DNow_binop_rm_int<0x94, "pfmin">;
77 defm PFMUL : I3DNow_binop_rm_int<0xB4, "pfmul", 1>;
78 defm PFRCP : I3DNow_conv_rm_int<0x96, "pfrcp">;
79 defm PFRCPIT1 : I3DNow_binop_rm_int<0xA6, "pfrcpit1">;
80 defm PFRCPIT2 : I3DNow_binop_rm_int<0xB6, "pfrcpit2">;
81 defm PFRSQIT1 : I3DNow_binop_rm_int<0xA7, "pfrsqit1">;
82 defm PFRSQRT : I3DNow_conv_rm_int<0x97, "pfrsqrt">;
83 defm PFSUB : I3DNow_binop_rm_int<0x9A, "pfsub", 1>;
84 defm PFSUBR : I3DNow_binop_rm_int<0xAA, "pfsubr", 1>;
85 defm PI2FD : I3DNow_conv_rm_int<0x0D, "pi2fd">;
86 defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw", 1>;
89 def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms",
90 [(int_x86_mmx_femms)]>;
92 def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i8mem:$addr),
94 [(prefetch addr:$addr, (i32 0), imm, (i32 1))]>;
96 def PREFETCHW : I<0x0D, MRM1m, (outs), (ins i8mem:$addr), "prefetchw\t$addr",
97 [(prefetch addr:$addr, (i32 1), (i32 3), (i32 1))]>, TB,
98 Requires<[HasPrefetchW]>;
100 // "3DNowA" instructions
101 defm PF2IW : I3DNow_conv_rm_int<0x1C, "pf2iw", "a">;
102 defm PI2FW : I3DNow_conv_rm_int<0x0C, "pi2fw", "a">;
103 defm PFNACC : I3DNow_binop_rm_int<0x8A, "pfnacc", 0, "a">;
104 defm PFPNACC : I3DNow_binop_rm_int<0x8E, "pfpnacc", 0, "a">;
105 defm PSWAPD : I3DNow_conv_rm_int<0xBB, "pswapd", "a">;