1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
34 ValueType KVT = !cast<ValueType>("v" # NumElts # "i1");
36 // Suffix used in the instruction mnemonic.
37 string Suffix = suffix;
39 // VTName is a string name for vector VT. For vector types it will be
40 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
41 // It is a little bit complex for scalar types, where NumElts = 1.
42 // In this case we build v4f32 or v2f64
43 string VTName = "v" # !if (!eq (NumElts, 1),
44 !if (!eq (EltVT.Size, 32), 4,
45 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
48 ValueType VT = !cast<ValueType>(VTName);
50 string EltTypeName = !cast<string>(EltVT);
51 // Size of the element type in bits, e.g. 32 for v16i32.
52 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
53 int EltSize = EltVT.Size;
55 // "i" for integer types and "f" for floating-point types
56 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
58 // Size of RC in bits, e.g. 512 for VR512.
61 // The corresponding memory operand, e.g. i512mem for VR512.
62 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
63 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
64 // FP scalar memory operand for intrinsics - ssmem/sdmem.
65 Operand IntScalarMemOp = !if (!eq (EltTypeName, "f32"), !cast<Operand>("ssmem"),
66 !if (!eq (EltTypeName, "f64"), !cast<Operand>("sdmem"), ?));
69 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
70 // due to load promotion during legalization
71 PatFrag LdFrag = !cast<PatFrag>("load" #
72 !if (!eq (TypeVariantName, "i"),
73 !if (!eq (Size, 128), "v2i64",
74 !if (!eq (Size, 256), "v4i64",
75 !if (!eq (Size, 512), "v8i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
82 !if (!eq (Size, 512), "v8i64",
85 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
87 ComplexPattern ScalarIntMemCPat = !if (!eq (EltTypeName, "f32"),
88 !cast<ComplexPattern>("sse_load_f32"),
89 !if (!eq (EltTypeName, "f64"),
90 !cast<ComplexPattern>("sse_load_f64"),
93 // The corresponding float type, e.g. v16f32 for v16i32
94 // Note: For EltSize < 32, FloatVT is illegal and TableGen
95 // fails to compile, so we choose FloatVT = VT
96 ValueType FloatVT = !cast<ValueType>(
97 !if (!eq (!srl(EltSize,5),0),
99 !if (!eq(TypeVariantName, "i"),
100 "v" # NumElts # "f" # EltSize,
103 ValueType IntVT = !cast<ValueType>(
104 !if (!eq (!srl(EltSize,5),0),
106 !if (!eq(TypeVariantName, "f"),
107 "v" # NumElts # "i" # EltSize,
109 // The string to specify embedded broadcast in assembly.
110 string BroadcastStr = "{1to" # NumElts # "}";
112 // 8-bit compressed displacement tuple/subvector format. This is only
113 // defined for NumElts <= 8.
114 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
115 !cast<CD8VForm>("CD8VT" # NumElts), ?);
117 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
118 !if (!eq (Size, 256), sub_ymm, ?));
120 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
121 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
124 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
126 // A vector tye of the same width with element type i64. This is used to
127 // create patterns for logic ops.
128 ValueType i64VT = !cast<ValueType>("v" # !srl(Size, 6) # "i64");
130 // A vector type of the same width with element type i32. This is used to
131 // create the canonical constant zero node ImmAllZerosV.
132 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
133 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
135 string ZSuffix = !if (!eq (Size, 128), "Z128",
136 !if (!eq (Size, 256), "Z256", "Z"));
139 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
140 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
141 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
142 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
143 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
144 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
146 // "x" in v32i8x_info means RC = VR256X
147 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
148 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
149 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
150 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
151 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
152 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
154 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
155 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
156 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
157 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
158 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
159 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
161 // We map scalar types to the smallest (128-bit) vector type
162 // with the appropriate element type. This allows to use the same masking logic.
163 def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">;
164 def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">;
165 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
166 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
168 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
169 X86VectorVTInfo i128> {
170 X86VectorVTInfo info512 = i512;
171 X86VectorVTInfo info256 = i256;
172 X86VectorVTInfo info128 = i128;
175 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
177 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
179 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
181 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
183 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
185 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
188 // This multiclass generates the masking variants from the non-masking
189 // variant. It only provides the assembly pieces for the masking variants.
190 // It assumes custom ISel patterns for masking which can be provided as
191 // template arguments.
192 multiclass AVX512_maskable_custom<bits<8> O, Format F,
194 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
196 string AttSrcAsm, string IntelSrcAsm,
198 list<dag> MaskingPattern,
199 list<dag> ZeroMaskingPattern,
200 string MaskingConstraint = "",
201 InstrItinClass itin = NoItinerary,
202 bit IsCommutable = 0,
203 bit IsKCommutable = 0> {
204 let isCommutable = IsCommutable in
205 def NAME: AVX512<O, F, Outs, Ins,
206 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
207 "$dst, "#IntelSrcAsm#"}",
210 // Prefer over VMOV*rrk Pat<>
211 let isCommutable = IsKCommutable in
212 def NAME#k: AVX512<O, F, Outs, MaskingIns,
213 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
214 "$dst {${mask}}, "#IntelSrcAsm#"}",
215 MaskingPattern, itin>,
217 // In case of the 3src subclass this is overridden with a let.
218 string Constraints = MaskingConstraint;
221 // Zero mask does not add any restrictions to commute operands transformation.
222 // So, it is Ok to use IsCommutable instead of IsKCommutable.
223 let isCommutable = IsCommutable in // Prefer over VMOV*rrkz Pat<>
224 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
225 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
226 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
233 // Common base class of AVX512_maskable and AVX512_maskable_3src.
234 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
236 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
238 string AttSrcAsm, string IntelSrcAsm,
239 dag RHS, dag MaskingRHS,
240 SDNode Select = vselect,
241 string MaskingConstraint = "",
242 InstrItinClass itin = NoItinerary,
243 bit IsCommutable = 0,
244 bit IsKCommutable = 0> :
245 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
246 AttSrcAsm, IntelSrcAsm,
247 [(set _.RC:$dst, RHS)],
248 [(set _.RC:$dst, MaskingRHS)],
250 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
251 MaskingConstraint, NoItinerary, IsCommutable,
254 // Similar to AVX512_maskable_common, but with scalar types.
255 multiclass AVX512_maskable_fp_common<bits<8> O, Format F, X86VectorVTInfo _,
257 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
259 string AttSrcAsm, string IntelSrcAsm,
260 SDNode Select = vselect,
261 string MaskingConstraint = "",
262 InstrItinClass itin = NoItinerary,
263 bit IsCommutable = 0,
264 bit IsKCommutable = 0> :
265 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
266 AttSrcAsm, IntelSrcAsm,
268 MaskingConstraint, NoItinerary, IsCommutable,
271 // This multiclass generates the unconditional/non-masking, the masking and
272 // the zero-masking variant of the vector instruction. In the masking case, the
273 // perserved vector elements come from a new dummy input operand tied to $dst.
274 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
275 dag Outs, dag Ins, string OpcodeStr,
276 string AttSrcAsm, string IntelSrcAsm,
278 InstrItinClass itin = NoItinerary,
279 bit IsCommutable = 0, bit IsKCommutable = 0,
280 SDNode Select = vselect> :
281 AVX512_maskable_common<O, F, _, Outs, Ins,
282 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
283 !con((ins _.KRCWM:$mask), Ins),
284 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
285 (Select _.KRCWM:$mask, RHS, _.RC:$src0), Select,
286 "$src0 = $dst", itin, IsCommutable, IsKCommutable>;
288 // This multiclass generates the unconditional/non-masking, the masking and
289 // the zero-masking variant of the scalar instruction.
290 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
291 dag Outs, dag Ins, string OpcodeStr,
292 string AttSrcAsm, string IntelSrcAsm,
294 InstrItinClass itin = NoItinerary,
295 bit IsCommutable = 0> :
296 AVX512_maskable_common<O, F, _, Outs, Ins,
297 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
298 !con((ins _.KRCWM:$mask), Ins),
299 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
300 (X86selects _.KRCWM:$mask, RHS, _.RC:$src0),
301 X86selects, "$src0 = $dst", itin, IsCommutable>;
303 // Similar to AVX512_maskable but in this case one of the source operands
304 // ($src1) is already tied to $dst so we just use that for the preserved
305 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
307 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
308 dag Outs, dag NonTiedIns, string OpcodeStr,
309 string AttSrcAsm, string IntelSrcAsm,
310 dag RHS, bit IsCommutable = 0,
311 bit IsKCommutable = 0> :
312 AVX512_maskable_common<O, F, _, Outs,
313 !con((ins _.RC:$src1), NonTiedIns),
314 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
315 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
316 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
317 (vselect _.KRCWM:$mask, RHS, _.RC:$src1),
318 vselect, "", NoItinerary, IsCommutable, IsKCommutable>;
320 multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
321 dag Outs, dag NonTiedIns, string OpcodeStr,
322 string AttSrcAsm, string IntelSrcAsm,
323 dag RHS, bit IsCommutable = 0,
324 bit IsKCommutable = 0> :
325 AVX512_maskable_common<O, F, _, Outs,
326 !con((ins _.RC:$src1), NonTiedIns),
327 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
328 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
329 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
330 (X86selects _.KRCWM:$mask, RHS, _.RC:$src1),
331 X86selects, "", NoItinerary, IsCommutable,
334 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
337 string AttSrcAsm, string IntelSrcAsm,
339 AVX512_maskable_custom<O, F, Outs, Ins,
340 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
341 !con((ins _.KRCWM:$mask), Ins),
342 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
346 // Instruction with mask that puts result in mask register,
347 // like "compare" and "vptest"
348 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
350 dag Ins, dag MaskingIns,
352 string AttSrcAsm, string IntelSrcAsm,
354 list<dag> MaskingPattern,
355 bit IsCommutable = 0> {
356 let isCommutable = IsCommutable in
357 def NAME: AVX512<O, F, Outs, Ins,
358 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
359 "$dst, "#IntelSrcAsm#"}",
360 Pattern, NoItinerary>;
362 def NAME#k: AVX512<O, F, Outs, MaskingIns,
363 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
364 "$dst {${mask}}, "#IntelSrcAsm#"}",
365 MaskingPattern, NoItinerary>, EVEX_K;
368 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
370 dag Ins, dag MaskingIns,
372 string AttSrcAsm, string IntelSrcAsm,
373 dag RHS, dag MaskingRHS,
374 bit IsCommutable = 0> :
375 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
376 AttSrcAsm, IntelSrcAsm,
377 [(set _.KRC:$dst, RHS)],
378 [(set _.KRC:$dst, MaskingRHS)], IsCommutable>;
380 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
381 dag Outs, dag Ins, string OpcodeStr,
382 string AttSrcAsm, string IntelSrcAsm,
383 dag RHS, bit IsCommutable = 0> :
384 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
385 !con((ins _.KRCWM:$mask), Ins),
386 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
387 (and _.KRCWM:$mask, RHS), IsCommutable>;
389 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
390 dag Outs, dag Ins, string OpcodeStr,
391 string AttSrcAsm, string IntelSrcAsm> :
392 AVX512_maskable_custom_cmp<O, F, Outs,
393 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
394 AttSrcAsm, IntelSrcAsm, [],[]>;
396 // This multiclass generates the unconditional/non-masking, the masking and
397 // the zero-masking variant of the vector instruction. In the masking case, the
398 // perserved vector elements come from a new dummy input operand tied to $dst.
399 multiclass AVX512_maskable_logic<bits<8> O, Format F, X86VectorVTInfo _,
400 dag Outs, dag Ins, string OpcodeStr,
401 string AttSrcAsm, string IntelSrcAsm,
402 dag RHS, dag MaskedRHS,
403 InstrItinClass itin = NoItinerary,
404 bit IsCommutable = 0, SDNode Select = vselect> :
405 AVX512_maskable_custom<O, F, Outs, Ins,
406 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
407 !con((ins _.KRCWM:$mask), Ins),
408 OpcodeStr, AttSrcAsm, IntelSrcAsm,
409 [(set _.RC:$dst, RHS)],
411 (Select _.KRCWM:$mask, MaskedRHS, _.RC:$src0))],
413 (Select _.KRCWM:$mask, MaskedRHS,
415 "$src0 = $dst", itin, IsCommutable>;
417 // Bitcasts between 512-bit vector types. Return the original type since
418 // no instruction is needed for the conversion.
419 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
420 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
421 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
422 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
423 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
424 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
425 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
426 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
427 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
428 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
429 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
430 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
431 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
432 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
433 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
434 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
435 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
436 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
437 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
438 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
439 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
440 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
441 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
442 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
443 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
444 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
445 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
446 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
447 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
448 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
449 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
451 // Alias instruction that maps zero vector to pxor / xorp* for AVX-512.
452 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
453 // swizzled by ExecutionDepsFix to pxor.
454 // We set canFoldAsLoad because this can be converted to a constant-pool
455 // load of an all-zeros value if folding it would be beneficial.
456 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
457 isPseudo = 1, Predicates = [HasAVX512], SchedRW = [WriteZero] in {
458 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
459 [(set VR512:$dst, (v16i32 immAllZerosV))]>;
460 def AVX512_512_SETALLONES : I<0, Pseudo, (outs VR512:$dst), (ins), "",
461 [(set VR512:$dst, (v16i32 immAllOnesV))]>;
464 // Alias instructions that allow VPTERNLOG to be used with a mask to create
465 // a mix of all ones and all zeros elements. This is done this way to force
466 // the same register to be used as input for all three sources.
467 let isPseudo = 1, Predicates = [HasAVX512] in {
468 def AVX512_512_SEXT_MASK_32 : I<0, Pseudo, (outs VR512:$dst),
469 (ins VK16WM:$mask), "",
470 [(set VR512:$dst, (vselect (v16i1 VK16WM:$mask),
471 (v16i32 immAllOnesV),
472 (v16i32 immAllZerosV)))]>;
473 def AVX512_512_SEXT_MASK_64 : I<0, Pseudo, (outs VR512:$dst),
474 (ins VK8WM:$mask), "",
475 [(set VR512:$dst, (vselect (v8i1 VK8WM:$mask),
476 (bc_v8i64 (v16i32 immAllOnesV)),
477 (bc_v8i64 (v16i32 immAllZerosV))))]>;
480 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
481 isPseudo = 1, Predicates = [HasAVX512], SchedRW = [WriteZero] in {
482 def AVX512_128_SET0 : I<0, Pseudo, (outs VR128X:$dst), (ins), "",
483 [(set VR128X:$dst, (v4i32 immAllZerosV))]>;
484 def AVX512_256_SET0 : I<0, Pseudo, (outs VR256X:$dst), (ins), "",
485 [(set VR256X:$dst, (v8i32 immAllZerosV))]>;
488 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
489 // This is expanded by ExpandPostRAPseudos.
490 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
491 isPseudo = 1, SchedRW = [WriteZero], Predicates = [HasAVX512] in {
492 def AVX512_FsFLD0SS : I<0, Pseudo, (outs FR32X:$dst), (ins), "",
493 [(set FR32X:$dst, fp32imm0)]>;
494 def AVX512_FsFLD0SD : I<0, Pseudo, (outs FR64X:$dst), (ins), "",
495 [(set FR64X:$dst, fpimm0)]>;
498 //===----------------------------------------------------------------------===//
499 // AVX-512 - VECTOR INSERT
501 multiclass vinsert_for_size<int Opcode, X86VectorVTInfo From, X86VectorVTInfo To,
502 PatFrag vinsert_insert> {
503 let ExeDomain = To.ExeDomain in {
504 defm rr : AVX512_maskable<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
505 (ins To.RC:$src1, From.RC:$src2, u8imm:$src3),
506 "vinsert" # From.EltTypeName # "x" # From.NumElts,
507 "$src3, $src2, $src1", "$src1, $src2, $src3",
508 (vinsert_insert:$src3 (To.VT To.RC:$src1),
509 (From.VT From.RC:$src2),
510 (iPTR imm))>, AVX512AIi8Base, EVEX_4V;
512 defm rm : AVX512_maskable<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
513 (ins To.RC:$src1, From.MemOp:$src2, u8imm:$src3),
514 "vinsert" # From.EltTypeName # "x" # From.NumElts,
515 "$src3, $src2, $src1", "$src1, $src2, $src3",
516 (vinsert_insert:$src3 (To.VT To.RC:$src1),
517 (From.VT (bitconvert (From.LdFrag addr:$src2))),
518 (iPTR imm))>, AVX512AIi8Base, EVEX_4V,
519 EVEX_CD8<From.EltSize, From.CD8TupleForm>;
523 multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
524 X86VectorVTInfo To, PatFrag vinsert_insert,
525 SDNodeXForm INSERT_get_vinsert_imm , list<Predicate> p> {
526 let Predicates = p in {
527 def : Pat<(vinsert_insert:$ins
528 (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
529 (To.VT (!cast<Instruction>(InstrStr#"rr")
530 To.RC:$src1, From.RC:$src2,
531 (INSERT_get_vinsert_imm To.RC:$ins)))>;
533 def : Pat<(vinsert_insert:$ins
535 (From.VT (bitconvert (From.LdFrag addr:$src2))),
537 (To.VT (!cast<Instruction>(InstrStr#"rm")
538 To.RC:$src1, addr:$src2,
539 (INSERT_get_vinsert_imm To.RC:$ins)))>;
543 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
544 ValueType EltVT64, int Opcode256> {
546 let Predicates = [HasVLX] in
547 defm NAME # "32x4Z256" : vinsert_for_size<Opcode128,
548 X86VectorVTInfo< 4, EltVT32, VR128X>,
549 X86VectorVTInfo< 8, EltVT32, VR256X>,
550 vinsert128_insert>, EVEX_V256;
552 defm NAME # "32x4Z" : vinsert_for_size<Opcode128,
553 X86VectorVTInfo< 4, EltVT32, VR128X>,
554 X86VectorVTInfo<16, EltVT32, VR512>,
555 vinsert128_insert>, EVEX_V512;
557 defm NAME # "64x4Z" : vinsert_for_size<Opcode256,
558 X86VectorVTInfo< 4, EltVT64, VR256X>,
559 X86VectorVTInfo< 8, EltVT64, VR512>,
560 vinsert256_insert>, VEX_W, EVEX_V512;
562 let Predicates = [HasVLX, HasDQI] in
563 defm NAME # "64x2Z256" : vinsert_for_size<Opcode128,
564 X86VectorVTInfo< 2, EltVT64, VR128X>,
565 X86VectorVTInfo< 4, EltVT64, VR256X>,
566 vinsert128_insert>, VEX_W, EVEX_V256;
568 let Predicates = [HasDQI] in {
569 defm NAME # "64x2Z" : vinsert_for_size<Opcode128,
570 X86VectorVTInfo< 2, EltVT64, VR128X>,
571 X86VectorVTInfo< 8, EltVT64, VR512>,
572 vinsert128_insert>, VEX_W, EVEX_V512;
574 defm NAME # "32x8Z" : vinsert_for_size<Opcode256,
575 X86VectorVTInfo< 8, EltVT32, VR256X>,
576 X86VectorVTInfo<16, EltVT32, VR512>,
577 vinsert256_insert>, EVEX_V512;
581 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
582 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
584 // Codegen pattern with the alternative types,
585 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
586 defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info,
587 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
588 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info,
589 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
591 defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v2f64x_info, v8f64_info,
592 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
593 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v2i64x_info, v8i64_info,
594 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
596 defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v8f32x_info, v16f32_info,
597 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
598 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v8i32x_info, v16i32_info,
599 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
601 // Codegen pattern with the alternative types insert VEC128 into VEC256
602 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info,
603 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
604 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info,
605 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
606 // Codegen pattern with the alternative types insert VEC128 into VEC512
607 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v8i16x_info, v32i16_info,
608 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
609 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v16i8x_info, v64i8_info,
610 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
611 // Codegen pattern with the alternative types insert VEC256 into VEC512
612 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v16i16x_info, v32i16_info,
613 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
614 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v32i8x_info, v64i8_info,
615 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
617 // vinsertps - insert f32 to XMM
618 let ExeDomain = SSEPackedSingle in {
619 def VINSERTPSZrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
620 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
621 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
622 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
624 def VINSERTPSZrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
625 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
626 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
627 [(set VR128X:$dst, (X86insertps VR128X:$src1,
628 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
629 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
632 //===----------------------------------------------------------------------===//
633 // AVX-512 VECTOR EXTRACT
636 multiclass vextract_for_size<int Opcode,
637 X86VectorVTInfo From, X86VectorVTInfo To,
638 PatFrag vextract_extract,
639 SDNodeXForm EXTRACT_get_vextract_imm> {
641 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
642 // use AVX512_maskable_in_asm (AVX512_maskable can't be used due to
643 // vextract_extract), we interesting only in patterns without mask,
644 // intrinsics pattern match generated bellow.
645 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
646 (ins From.RC:$src1, u8imm:$idx),
647 "vextract" # To.EltTypeName # "x" # To.NumElts,
648 "$idx, $src1", "$src1, $idx",
649 [(set To.RC:$dst, (vextract_extract:$idx (From.VT From.RC:$src1),
651 AVX512AIi8Base, EVEX;
652 def mr : AVX512AIi8<Opcode, MRMDestMem, (outs),
653 (ins To.MemOp:$dst, From.RC:$src1, u8imm:$idx),
654 "vextract" # To.EltTypeName # "x" # To.NumElts #
655 "\t{$idx, $src1, $dst|$dst, $src1, $idx}",
656 [(store (To.VT (vextract_extract:$idx
657 (From.VT From.RC:$src1), (iPTR imm))),
660 let mayStore = 1, hasSideEffects = 0 in
661 def mrk : AVX512AIi8<Opcode, MRMDestMem, (outs),
662 (ins To.MemOp:$dst, To.KRCWM:$mask,
663 From.RC:$src1, u8imm:$idx),
664 "vextract" # To.EltTypeName # "x" # To.NumElts #
665 "\t{$idx, $src1, $dst {${mask}}|"
666 "$dst {${mask}}, $src1, $idx}",
670 def : Pat<(To.VT (vselect To.KRCWM:$mask,
671 (vextract_extract:$ext (From.VT From.RC:$src1),
674 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
675 From.ZSuffix # "rrk")
676 To.RC:$src0, To.KRCWM:$mask, From.RC:$src1,
677 (EXTRACT_get_vextract_imm To.RC:$ext))>;
679 def : Pat<(To.VT (vselect To.KRCWM:$mask,
680 (vextract_extract:$ext (From.VT From.RC:$src1),
683 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
684 From.ZSuffix # "rrkz")
685 To.KRCWM:$mask, From.RC:$src1,
686 (EXTRACT_get_vextract_imm To.RC:$ext))>;
689 // Codegen pattern for the alternative types
690 multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
691 X86VectorVTInfo To, PatFrag vextract_extract,
692 SDNodeXForm EXTRACT_get_vextract_imm, list<Predicate> p> {
693 let Predicates = p in {
694 def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
695 (To.VT (!cast<Instruction>(InstrStr#"rr")
697 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
698 def : Pat<(store (To.VT (vextract_extract:$ext (From.VT From.RC:$src1),
699 (iPTR imm))), addr:$dst),
700 (!cast<Instruction>(InstrStr#"mr") addr:$dst, From.RC:$src1,
701 (EXTRACT_get_vextract_imm To.RC:$ext))>;
705 multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
706 ValueType EltVT64, int Opcode256> {
707 defm NAME # "32x4Z" : vextract_for_size<Opcode128,
708 X86VectorVTInfo<16, EltVT32, VR512>,
709 X86VectorVTInfo< 4, EltVT32, VR128X>,
711 EXTRACT_get_vextract128_imm>,
712 EVEX_V512, EVEX_CD8<32, CD8VT4>;
713 defm NAME # "64x4Z" : vextract_for_size<Opcode256,
714 X86VectorVTInfo< 8, EltVT64, VR512>,
715 X86VectorVTInfo< 4, EltVT64, VR256X>,
717 EXTRACT_get_vextract256_imm>,
718 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>;
719 let Predicates = [HasVLX] in
720 defm NAME # "32x4Z256" : vextract_for_size<Opcode128,
721 X86VectorVTInfo< 8, EltVT32, VR256X>,
722 X86VectorVTInfo< 4, EltVT32, VR128X>,
724 EXTRACT_get_vextract128_imm>,
725 EVEX_V256, EVEX_CD8<32, CD8VT4>;
726 let Predicates = [HasVLX, HasDQI] in
727 defm NAME # "64x2Z256" : vextract_for_size<Opcode128,
728 X86VectorVTInfo< 4, EltVT64, VR256X>,
729 X86VectorVTInfo< 2, EltVT64, VR128X>,
731 EXTRACT_get_vextract128_imm>,
732 VEX_W, EVEX_V256, EVEX_CD8<64, CD8VT2>;
733 let Predicates = [HasDQI] in {
734 defm NAME # "64x2Z" : vextract_for_size<Opcode128,
735 X86VectorVTInfo< 8, EltVT64, VR512>,
736 X86VectorVTInfo< 2, EltVT64, VR128X>,
738 EXTRACT_get_vextract128_imm>,
739 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>;
740 defm NAME # "32x8Z" : vextract_for_size<Opcode256,
741 X86VectorVTInfo<16, EltVT32, VR512>,
742 X86VectorVTInfo< 8, EltVT32, VR256X>,
744 EXTRACT_get_vextract256_imm>,
745 EVEX_V512, EVEX_CD8<32, CD8VT8>;
749 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
750 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
752 // extract_subvector codegen patterns with the alternative types.
753 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
754 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z", v8f64_info, v2f64x_info,
755 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
756 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v8i64_info, v2i64x_info,
757 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
759 defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v16f32_info, v8f32x_info,
760 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
761 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v16i32_info, v8i32x_info,
762 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
764 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z256", v4f64x_info, v2f64x_info,
765 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
766 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v4i64x_info, v2i64x_info,
767 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
769 // Codegen pattern with the alternative types extract VEC128 from VEC256
770 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v16i16x_info, v8i16x_info,
771 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>;
772 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v32i8x_info, v16i8x_info,
773 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>;
775 // Codegen pattern with the alternative types extract VEC128 from VEC512
776 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v32i16_info, v8i16x_info,
777 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
778 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v64i8_info, v16i8x_info,
779 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
780 // Codegen pattern with the alternative types extract VEC256 from VEC512
781 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v32i16_info, v16i16x_info,
782 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
783 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info,
784 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
786 // A 128-bit subvector extract from the first 256-bit vector position
787 // is a subregister copy that needs no instruction.
788 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
789 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
790 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
791 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
792 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
793 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
794 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
795 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
796 def : Pat<(v8i16 (extract_subvector (v32i16 VR512:$src), (iPTR 0))),
797 (v8i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_xmm))>;
798 def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 0))),
799 (v16i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_xmm))>;
801 // A 256-bit subvector extract from the first 256-bit vector position
802 // is a subregister copy that needs no instruction.
803 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
804 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
805 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
806 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
807 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
808 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
809 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
810 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
811 def : Pat<(v16i16 (extract_subvector (v32i16 VR512:$src), (iPTR 0))),
812 (v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm))>;
813 def : Pat<(v32i8 (extract_subvector (v64i8 VR512:$src), (iPTR 0))),
814 (v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm))>;
816 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
817 // A 128-bit subvector insert to the first 512-bit vector position
818 // is a subregister copy that needs no instruction.
819 def : Pat<(v8i64 (insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0))),
820 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm)>;
821 def : Pat<(v8f64 (insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0))),
822 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm)>;
823 def : Pat<(v16i32 (insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0))),
824 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm)>;
825 def : Pat<(v16f32 (insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0))),
826 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm)>;
827 def : Pat<(v32i16 (insert_subvector undef, (v8i16 VR128X:$src), (iPTR 0))),
828 (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR128X:$src, sub_xmm)>;
829 def : Pat<(v64i8 (insert_subvector undef, (v16i8 VR128X:$src), (iPTR 0))),
830 (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR128X:$src, sub_xmm)>;
832 // A 256-bit subvector insert to the first 512-bit vector position
833 // is a subregister copy that needs no instruction.
834 def : Pat<(v8i64 (insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0))),
835 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
836 def : Pat<(v8f64 (insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0))),
837 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
838 def : Pat<(v16i32 (insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0))),
839 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
840 def : Pat<(v16f32 (insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0))),
841 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
842 def : Pat<(v32i16 (insert_subvector undef, (v16i16 VR256X:$src), (iPTR 0))),
843 (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
844 def : Pat<(v64i8 (insert_subvector undef, (v32i8 VR256X:$src), (iPTR 0))),
845 (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
848 // vextractps - extract 32 bits from XMM
849 def VEXTRACTPSZrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
850 (ins VR128X:$src1, u8imm:$src2),
851 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
852 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
855 def VEXTRACTPSZmr : AVX512AIi8<0x17, MRMDestMem, (outs),
856 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
857 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
858 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
859 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
861 //===---------------------------------------------------------------------===//
864 // broadcast with a scalar argument.
865 multiclass avx512_broadcast_scalar<bits<8> opc, string OpcodeStr,
866 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo> {
867 def : Pat<(DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)),
868 (!cast<Instruction>(NAME#DestInfo.ZSuffix#r)
869 (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC))>;
870 def : Pat<(DestInfo.VT (vselect DestInfo.KRCWM:$mask,
871 (X86VBroadcast SrcInfo.FRC:$src),
873 (!cast<Instruction>(NAME#DestInfo.ZSuffix#rk)
874 DestInfo.RC:$src0, DestInfo.KRCWM:$mask,
875 (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC))>;
876 def : Pat<(DestInfo.VT (vselect DestInfo.KRCWM:$mask,
877 (X86VBroadcast SrcInfo.FRC:$src),
878 DestInfo.ImmAllZerosV)),
879 (!cast<Instruction>(NAME#DestInfo.ZSuffix#rkz)
880 DestInfo.KRCWM:$mask, (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC))>;
883 multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr,
884 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo> {
885 let ExeDomain = DestInfo.ExeDomain in {
886 defm r : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
887 (ins SrcInfo.RC:$src), OpcodeStr, "$src", "$src",
888 (DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src)))>,
890 defm m : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
891 (ins SrcInfo.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
892 (DestInfo.VT (X86VBroadcast
893 (SrcInfo.ScalarLdFrag addr:$src)))>,
894 T8PD, EVEX, EVEX_CD8<SrcInfo.EltSize, CD8VT1>;
897 def : Pat<(DestInfo.VT (X86VBroadcast
898 (SrcInfo.VT (scalar_to_vector
899 (SrcInfo.ScalarLdFrag addr:$src))))),
900 (!cast<Instruction>(NAME#DestInfo.ZSuffix#m) addr:$src)>;
901 def : Pat<(DestInfo.VT (vselect DestInfo.KRCWM:$mask,
903 (SrcInfo.VT (scalar_to_vector
904 (SrcInfo.ScalarLdFrag addr:$src)))),
906 (!cast<Instruction>(NAME#DestInfo.ZSuffix#mk)
907 DestInfo.RC:$src0, DestInfo.KRCWM:$mask, addr:$src)>;
908 def : Pat<(DestInfo.VT (vselect DestInfo.KRCWM:$mask,
910 (SrcInfo.VT (scalar_to_vector
911 (SrcInfo.ScalarLdFrag addr:$src)))),
912 DestInfo.ImmAllZerosV)),
913 (!cast<Instruction>(NAME#DestInfo.ZSuffix#mkz)
914 DestInfo.KRCWM:$mask, addr:$src)>;
917 multiclass avx512_fp_broadcast_sd<bits<8> opc, string OpcodeStr,
918 AVX512VLVectorVTInfo _> {
919 let Predicates = [HasAVX512] in
920 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
921 avx512_broadcast_scalar<opc, OpcodeStr, _.info512, _.info128>,
924 let Predicates = [HasVLX] in {
925 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
926 avx512_broadcast_scalar<opc, OpcodeStr, _.info256, _.info128>,
931 multiclass avx512_fp_broadcast_ss<bits<8> opc, string OpcodeStr,
932 AVX512VLVectorVTInfo _> {
933 let Predicates = [HasAVX512] in
934 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
935 avx512_broadcast_scalar<opc, OpcodeStr, _.info512, _.info128>,
938 let Predicates = [HasVLX] in {
939 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
940 avx512_broadcast_scalar<opc, OpcodeStr, _.info256, _.info128>,
942 defm Z128 : avx512_broadcast_rm<opc, OpcodeStr, _.info128, _.info128>,
943 avx512_broadcast_scalar<opc, OpcodeStr, _.info128, _.info128>,
947 defm VBROADCASTSS : avx512_fp_broadcast_ss<0x18, "vbroadcastss",
949 defm VBROADCASTSD : avx512_fp_broadcast_sd<0x19, "vbroadcastsd",
950 avx512vl_f64_info>, VEX_W;
952 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
953 (VBROADCASTSSZm addr:$src)>;
954 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
955 (VBROADCASTSDZm addr:$src)>;
957 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
958 SDPatternOperator OpNode,
959 RegisterClass SrcRC> {
960 let ExeDomain = _.ExeDomain in
961 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
963 "vpbroadcast"##_.Suffix, "$src", "$src",
964 (_.VT (OpNode SrcRC:$src))>, T8PD, EVEX;
967 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
968 SDPatternOperator OpNode,
969 RegisterClass SrcRC, Predicate prd> {
970 let Predicates = [prd] in
971 defm Z : avx512_int_broadcast_reg<opc, _.info512, OpNode, SrcRC>, EVEX_V512;
972 let Predicates = [prd, HasVLX] in {
973 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, OpNode, SrcRC>, EVEX_V256;
974 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, OpNode, SrcRC>, EVEX_V128;
978 let isCodeGenOnly = 1 in {
979 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info,
980 X86VBroadcast, GR8, HasBWI>;
981 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info,
982 X86VBroadcast, GR16, HasBWI>;
984 let isAsmParserOnly = 1 in {
985 defm VPBROADCASTBr_Alt : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info,
986 null_frag, GR32, HasBWI>;
987 defm VPBROADCASTWr_Alt : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info,
988 null_frag, GR32, HasBWI>;
990 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info,
991 X86VBroadcast, GR32, HasAVX512>;
992 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info,
993 X86VBroadcast, GR64, HasAVX512>, VEX_W;
995 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
996 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
997 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
998 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
1000 // Provide aliases for broadcast from the same register class that
1001 // automatically does the extract.
1002 multiclass avx512_int_broadcast_rm_lowering<X86VectorVTInfo DestInfo,
1003 X86VectorVTInfo SrcInfo> {
1004 def : Pat<(DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))),
1005 (!cast<Instruction>(NAME#DestInfo.ZSuffix#"r")
1006 (EXTRACT_SUBREG (SrcInfo.VT SrcInfo.RC:$src), sub_xmm))>;
1009 multiclass avx512_int_broadcast_rm_vl<bits<8> opc, string OpcodeStr,
1010 AVX512VLVectorVTInfo _, Predicate prd> {
1011 let Predicates = [prd] in {
1012 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
1013 avx512_int_broadcast_rm_lowering<_.info512, _.info256>,
1015 // Defined separately to avoid redefinition.
1016 defm Z_Alt : avx512_int_broadcast_rm_lowering<_.info512, _.info512>;
1018 let Predicates = [prd, HasVLX] in {
1019 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
1020 avx512_int_broadcast_rm_lowering<_.info256, _.info256>,
1022 defm Z128 : avx512_broadcast_rm<opc, OpcodeStr, _.info128, _.info128>,
1027 defm VPBROADCASTB : avx512_int_broadcast_rm_vl<0x78, "vpbroadcastb",
1028 avx512vl_i8_info, HasBWI>;
1029 defm VPBROADCASTW : avx512_int_broadcast_rm_vl<0x79, "vpbroadcastw",
1030 avx512vl_i16_info, HasBWI>;
1031 defm VPBROADCASTD : avx512_int_broadcast_rm_vl<0x58, "vpbroadcastd",
1032 avx512vl_i32_info, HasAVX512>;
1033 defm VPBROADCASTQ : avx512_int_broadcast_rm_vl<0x59, "vpbroadcastq",
1034 avx512vl_i64_info, HasAVX512>, VEX_W;
1036 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
1037 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
1038 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
1039 (ins _Src.MemOp:$src), OpcodeStr, "$src", "$src",
1040 (_Dst.VT (X86SubVBroadcast
1041 (_Src.VT (bitconvert (_Src.LdFrag addr:$src)))))>,
1045 let Predicates = [HasAVX512] in {
1046 // 32-bit targets will fail to load a i64 directly but can use ZEXT_LOAD.
1047 def : Pat<(v8i64 (X86VBroadcast (v8i64 (X86vzload addr:$src)))),
1048 (VPBROADCASTQZm addr:$src)>;
1051 let Predicates = [HasVLX, HasBWI] in {
1052 // 32-bit targets will fail to load a i64 directly but can use ZEXT_LOAD.
1053 def : Pat<(v2i64 (X86VBroadcast (v2i64 (X86vzload addr:$src)))),
1054 (VPBROADCASTQZ128m addr:$src)>;
1055 def : Pat<(v4i64 (X86VBroadcast (v4i64 (X86vzload addr:$src)))),
1056 (VPBROADCASTQZ256m addr:$src)>;
1057 // loadi16 is tricky to fold, because !isTypeDesirableForOp, justifiably.
1058 // This means we'll encounter truncated i32 loads; match that here.
1059 def : Pat<(v8i16 (X86VBroadcast (i16 (trunc (i32 (load addr:$src)))))),
1060 (VPBROADCASTWZ128m addr:$src)>;
1061 def : Pat<(v16i16 (X86VBroadcast (i16 (trunc (i32 (load addr:$src)))))),
1062 (VPBROADCASTWZ256m addr:$src)>;
1063 def : Pat<(v8i16 (X86VBroadcast
1064 (i16 (trunc (i32 (zextloadi16 addr:$src)))))),
1065 (VPBROADCASTWZ128m addr:$src)>;
1066 def : Pat<(v16i16 (X86VBroadcast
1067 (i16 (trunc (i32 (zextloadi16 addr:$src)))))),
1068 (VPBROADCASTWZ256m addr:$src)>;
1071 //===----------------------------------------------------------------------===//
1072 // AVX-512 BROADCAST SUBVECTORS
1075 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1076 v16i32_info, v4i32x_info>,
1077 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1078 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1079 v16f32_info, v4f32x_info>,
1080 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1081 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
1082 v8i64_info, v4i64x_info>, VEX_W,
1083 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1084 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
1085 v8f64_info, v4f64x_info>, VEX_W,
1086 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1088 let Predicates = [HasAVX512] in {
1089 def : Pat<(v32i16 (X86SubVBroadcast (bc_v16i16 (loadv4i64 addr:$src)))),
1090 (VBROADCASTI64X4rm addr:$src)>;
1091 def : Pat<(v64i8 (X86SubVBroadcast (bc_v32i8 (loadv4i64 addr:$src)))),
1092 (VBROADCASTI64X4rm addr:$src)>;
1094 // Provide fallback in case the load node that is used in the patterns above
1095 // is used by additional users, which prevents the pattern selection.
1096 def : Pat<(v8f64 (X86SubVBroadcast (v4f64 VR256X:$src))),
1097 (VINSERTF64x4Zrr (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1098 (v4f64 VR256X:$src), 1)>;
1099 def : Pat<(v8i64 (X86SubVBroadcast (v4i64 VR256X:$src))),
1100 (VINSERTI64x4Zrr (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1101 (v4i64 VR256X:$src), 1)>;
1102 def : Pat<(v32i16 (X86SubVBroadcast (v16i16 VR256X:$src))),
1103 (VINSERTI64x4Zrr (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1104 (v16i16 VR256X:$src), 1)>;
1105 def : Pat<(v64i8 (X86SubVBroadcast (v32i8 VR256X:$src))),
1106 (VINSERTI64x4Zrr (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1107 (v32i8 VR256X:$src), 1)>;
1109 def : Pat<(v32i16 (X86SubVBroadcast (bc_v8i16 (loadv2i64 addr:$src)))),
1110 (VBROADCASTI32X4rm addr:$src)>;
1111 def : Pat<(v64i8 (X86SubVBroadcast (bc_v16i8 (loadv2i64 addr:$src)))),
1112 (VBROADCASTI32X4rm addr:$src)>;
1115 let Predicates = [HasVLX] in {
1116 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1117 v8i32x_info, v4i32x_info>,
1118 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1119 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1120 v8f32x_info, v4f32x_info>,
1121 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1123 def : Pat<(v16i16 (X86SubVBroadcast (bc_v8i16 (loadv2i64 addr:$src)))),
1124 (VBROADCASTI32X4Z256rm addr:$src)>;
1125 def : Pat<(v32i8 (X86SubVBroadcast (bc_v16i8 (loadv2i64 addr:$src)))),
1126 (VBROADCASTI32X4Z256rm addr:$src)>;
1128 // Provide fallback in case the load node that is used in the patterns above
1129 // is used by additional users, which prevents the pattern selection.
1130 def : Pat<(v8f32 (X86SubVBroadcast (v4f32 VR128X:$src))),
1131 (VINSERTF32x4Z256rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
1132 (v4f32 VR128X:$src), 1)>;
1133 def : Pat<(v8i32 (X86SubVBroadcast (v4i32 VR128X:$src))),
1134 (VINSERTI32x4Z256rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
1135 (v4i32 VR128X:$src), 1)>;
1136 def : Pat<(v16i16 (X86SubVBroadcast (v8i16 VR128X:$src))),
1137 (VINSERTI32x4Z256rr (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
1138 (v8i16 VR128X:$src), 1)>;
1139 def : Pat<(v32i8 (X86SubVBroadcast (v16i8 VR128X:$src))),
1140 (VINSERTI32x4Z256rr (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
1141 (v16i8 VR128X:$src), 1)>;
1144 let Predicates = [HasVLX, HasDQI] in {
1145 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1146 v4i64x_info, v2i64x_info>, VEX_W,
1147 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1148 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1149 v4f64x_info, v2f64x_info>, VEX_W,
1150 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1152 // Provide fallback in case the load node that is used in the patterns above
1153 // is used by additional users, which prevents the pattern selection.
1154 def : Pat<(v4f64 (X86SubVBroadcast (v2f64 VR128X:$src))),
1155 (VINSERTF64x2Z256rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
1156 (v2f64 VR128X:$src), 1)>;
1157 def : Pat<(v4i64 (X86SubVBroadcast (v2i64 VR128X:$src))),
1158 (VINSERTI64x2Z256rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
1159 (v2i64 VR128X:$src), 1)>;
1162 let Predicates = [HasVLX, NoDQI] in {
1163 def : Pat<(v4f64 (X86SubVBroadcast (loadv2f64 addr:$src))),
1164 (VBROADCASTF32X4Z256rm addr:$src)>;
1165 def : Pat<(v4i64 (X86SubVBroadcast (loadv2i64 addr:$src))),
1166 (VBROADCASTI32X4Z256rm addr:$src)>;
1168 // Provide fallback in case the load node that is used in the patterns above
1169 // is used by additional users, which prevents the pattern selection.
1170 def : Pat<(v4f64 (X86SubVBroadcast (v2f64 VR128X:$src))),
1171 (VINSERTF32x4Z256rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
1172 (v2f64 VR128X:$src), 1)>;
1173 def : Pat<(v4i64 (X86SubVBroadcast (v2i64 VR128X:$src))),
1174 (VINSERTI32x4Z256rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
1175 (v2i64 VR128X:$src), 1)>;
1178 let Predicates = [HasAVX512, NoDQI] in {
1179 def : Pat<(v8f64 (X86SubVBroadcast (loadv2f64 addr:$src))),
1180 (VBROADCASTF32X4rm addr:$src)>;
1181 def : Pat<(v8i64 (X86SubVBroadcast (loadv2i64 addr:$src))),
1182 (VBROADCASTI32X4rm addr:$src)>;
1184 def : Pat<(v16f32 (X86SubVBroadcast (loadv8f32 addr:$src))),
1185 (VBROADCASTF64X4rm addr:$src)>;
1186 def : Pat<(v16i32 (X86SubVBroadcast (bc_v8i32 (loadv4i64 addr:$src)))),
1187 (VBROADCASTI64X4rm addr:$src)>;
1189 // Provide fallback in case the load node that is used in the patterns above
1190 // is used by additional users, which prevents the pattern selection.
1191 def : Pat<(v16f32 (X86SubVBroadcast (v8f32 VR256X:$src))),
1192 (VINSERTF64x4Zrr (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1193 (v8f32 VR256X:$src), 1)>;
1194 def : Pat<(v16i32 (X86SubVBroadcast (v8i32 VR256X:$src))),
1195 (VINSERTI64x4Zrr (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1196 (v8i32 VR256X:$src), 1)>;
1199 let Predicates = [HasDQI] in {
1200 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1201 v8i64_info, v2i64x_info>, VEX_W,
1202 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1203 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
1204 v16i32_info, v8i32x_info>,
1205 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1206 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1207 v8f64_info, v2f64x_info>, VEX_W,
1208 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1209 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
1210 v16f32_info, v8f32x_info>,
1211 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1213 // Provide fallback in case the load node that is used in the patterns above
1214 // is used by additional users, which prevents the pattern selection.
1215 def : Pat<(v16f32 (X86SubVBroadcast (v8f32 VR256X:$src))),
1216 (VINSERTF32x8Zrr (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1217 (v8f32 VR256X:$src), 1)>;
1218 def : Pat<(v16i32 (X86SubVBroadcast (v8i32 VR256X:$src))),
1219 (VINSERTI32x8Zrr (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1220 (v8i32 VR256X:$src), 1)>;
1223 multiclass avx512_common_broadcast_32x2<bits<8> opc, string OpcodeStr,
1224 AVX512VLVectorVTInfo _Dst, AVX512VLVectorVTInfo _Src> {
1225 let Predicates = [HasDQI] in
1226 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _Dst.info512, _Src.info128>,
1228 let Predicates = [HasDQI, HasVLX] in
1229 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _Dst.info256, _Src.info128>,
1233 multiclass avx512_common_broadcast_i32x2<bits<8> opc, string OpcodeStr,
1234 AVX512VLVectorVTInfo _Dst, AVX512VLVectorVTInfo _Src> :
1235 avx512_common_broadcast_32x2<opc, OpcodeStr, _Dst, _Src> {
1237 let Predicates = [HasDQI, HasVLX] in
1238 defm Z128 : avx512_broadcast_rm<opc, OpcodeStr, _Dst.info128, _Src.info128>,
1242 defm VBROADCASTI32X2 : avx512_common_broadcast_i32x2<0x59, "vbroadcasti32x2",
1243 avx512vl_i32_info, avx512vl_i64_info>;
1244 defm VBROADCASTF32X2 : avx512_common_broadcast_32x2<0x19, "vbroadcastf32x2",
1245 avx512vl_f32_info, avx512vl_f64_info>;
1247 let Predicates = [HasVLX] in {
1248 def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256X:$src))),
1249 (VBROADCASTSSZ256r (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
1250 def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256X:$src))),
1251 (VBROADCASTSDZ256r (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
1254 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
1255 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
1256 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
1257 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
1259 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
1260 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
1261 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
1262 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
1264 //===----------------------------------------------------------------------===//
1265 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
1267 multiclass avx512_mask_broadcastm<bits<8> opc, string OpcodeStr,
1268 X86VectorVTInfo _, RegisterClass KRC> {
1269 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.RC:$dst), (ins KRC:$src),
1270 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1271 [(set _.RC:$dst, (_.VT (X86VBroadcastm KRC:$src)))]>, EVEX;
1274 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
1275 AVX512VLVectorVTInfo VTInfo, RegisterClass KRC> {
1276 let Predicates = [HasCDI] in
1277 defm Z : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info512, KRC>, EVEX_V512;
1278 let Predicates = [HasCDI, HasVLX] in {
1279 defm Z256 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info256, KRC>, EVEX_V256;
1280 defm Z128 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info128, KRC>, EVEX_V128;
1284 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
1285 avx512vl_i32_info, VK16>;
1286 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1287 avx512vl_i64_info, VK8>, VEX_W;
1289 //===----------------------------------------------------------------------===//
1290 // -- VPERMI2 - 3 source operands form --
1291 multiclass avx512_perm_i<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1292 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in {
1293 // The index operand in the pattern should really be an integer type. However,
1294 // if we do that and it happens to come from a bitcast, then it becomes
1295 // difficult to find the bitcast needed to convert the index to the
1296 // destination type for the passthru since it will be folded with the bitcast
1297 // of the index operand.
1298 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1299 (ins _.RC:$src2, _.RC:$src3),
1300 OpcodeStr, "$src3, $src2", "$src2, $src3",
1301 (_.VT (X86VPermi2X _.RC:$src1, _.RC:$src2, _.RC:$src3)), 1>, EVEX_4V,
1304 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1305 (ins _.RC:$src2, _.MemOp:$src3),
1306 OpcodeStr, "$src3, $src2", "$src2, $src3",
1307 (_.VT (X86VPermi2X _.RC:$src1, _.RC:$src2,
1308 (_.VT (bitconvert (_.LdFrag addr:$src3))))), 1>,
1309 EVEX_4V, AVX5128IBase;
1312 multiclass avx512_perm_i_mb<bits<8> opc, string OpcodeStr,
1313 X86VectorVTInfo _> {
1314 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in
1315 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1316 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1317 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1318 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1319 (_.VT (X86VPermi2X _.RC:$src1,
1320 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))),
1321 1>, AVX5128IBase, EVEX_4V, EVEX_B;
1324 multiclass avx512_perm_i_sizes<bits<8> opc, string OpcodeStr,
1325 AVX512VLVectorVTInfo VTInfo> {
1326 defm NAME: avx512_perm_i<opc, OpcodeStr, VTInfo.info512>,
1327 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1328 let Predicates = [HasVLX] in {
1329 defm NAME#128: avx512_perm_i<opc, OpcodeStr, VTInfo.info128>,
1330 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1331 defm NAME#256: avx512_perm_i<opc, OpcodeStr, VTInfo.info256>,
1332 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1336 multiclass avx512_perm_i_sizes_bw<bits<8> opc, string OpcodeStr,
1337 AVX512VLVectorVTInfo VTInfo,
1339 let Predicates = [Prd] in
1340 defm NAME: avx512_perm_i<opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1341 let Predicates = [Prd, HasVLX] in {
1342 defm NAME#128: avx512_perm_i<opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1343 defm NAME#256: avx512_perm_i<opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1347 defm VPERMI2D : avx512_perm_i_sizes<0x76, "vpermi2d",
1348 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1349 defm VPERMI2Q : avx512_perm_i_sizes<0x76, "vpermi2q",
1350 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1351 defm VPERMI2W : avx512_perm_i_sizes_bw<0x75, "vpermi2w",
1352 avx512vl_i16_info, HasBWI>,
1353 VEX_W, EVEX_CD8<16, CD8VF>;
1354 defm VPERMI2B : avx512_perm_i_sizes_bw<0x75, "vpermi2b",
1355 avx512vl_i8_info, HasVBMI>,
1357 defm VPERMI2PS : avx512_perm_i_sizes<0x77, "vpermi2ps",
1358 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1359 defm VPERMI2PD : avx512_perm_i_sizes<0x77, "vpermi2pd",
1360 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1363 multiclass avx512_perm_t<bits<8> opc, string OpcodeStr,
1364 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1365 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in {
1366 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1367 (ins IdxVT.RC:$src2, _.RC:$src3),
1368 OpcodeStr, "$src3, $src2", "$src2, $src3",
1369 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2, _.RC:$src3)), 1>,
1370 EVEX_4V, AVX5128IBase;
1372 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1373 (ins IdxVT.RC:$src2, _.MemOp:$src3),
1374 OpcodeStr, "$src3, $src2", "$src2, $src3",
1375 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2,
1376 (bitconvert (_.LdFrag addr:$src3)))), 1>,
1377 EVEX_4V, AVX5128IBase;
1380 multiclass avx512_perm_t_mb<bits<8> opc, string OpcodeStr,
1381 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1382 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in
1383 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1384 (ins IdxVT.RC:$src2, _.ScalarMemOp:$src3),
1385 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1386 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1387 (_.VT (X86VPermt2 _.RC:$src1,
1388 IdxVT.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))),
1389 1>, AVX5128IBase, EVEX_4V, EVEX_B;
1392 multiclass avx512_perm_t_sizes<bits<8> opc, string OpcodeStr,
1393 AVX512VLVectorVTInfo VTInfo,
1394 AVX512VLVectorVTInfo ShuffleMask> {
1395 defm NAME: avx512_perm_t<opc, OpcodeStr, VTInfo.info512,
1396 ShuffleMask.info512>,
1397 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info512,
1398 ShuffleMask.info512>, EVEX_V512;
1399 let Predicates = [HasVLX] in {
1400 defm NAME#128: avx512_perm_t<opc, OpcodeStr, VTInfo.info128,
1401 ShuffleMask.info128>,
1402 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info128,
1403 ShuffleMask.info128>, EVEX_V128;
1404 defm NAME#256: avx512_perm_t<opc, OpcodeStr, VTInfo.info256,
1405 ShuffleMask.info256>,
1406 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info256,
1407 ShuffleMask.info256>, EVEX_V256;
1411 multiclass avx512_perm_t_sizes_bw<bits<8> opc, string OpcodeStr,
1412 AVX512VLVectorVTInfo VTInfo,
1413 AVX512VLVectorVTInfo Idx,
1415 let Predicates = [Prd] in
1416 defm NAME: avx512_perm_t<opc, OpcodeStr, VTInfo.info512,
1417 Idx.info512>, EVEX_V512;
1418 let Predicates = [Prd, HasVLX] in {
1419 defm NAME#128: avx512_perm_t<opc, OpcodeStr, VTInfo.info128,
1420 Idx.info128>, EVEX_V128;
1421 defm NAME#256: avx512_perm_t<opc, OpcodeStr, VTInfo.info256,
1422 Idx.info256>, EVEX_V256;
1426 defm VPERMT2D : avx512_perm_t_sizes<0x7E, "vpermt2d",
1427 avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1428 defm VPERMT2Q : avx512_perm_t_sizes<0x7E, "vpermt2q",
1429 avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1430 defm VPERMT2W : avx512_perm_t_sizes_bw<0x7D, "vpermt2w",
1431 avx512vl_i16_info, avx512vl_i16_info, HasBWI>,
1432 VEX_W, EVEX_CD8<16, CD8VF>;
1433 defm VPERMT2B : avx512_perm_t_sizes_bw<0x7D, "vpermt2b",
1434 avx512vl_i8_info, avx512vl_i8_info, HasVBMI>,
1436 defm VPERMT2PS : avx512_perm_t_sizes<0x7F, "vpermt2ps",
1437 avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1438 defm VPERMT2PD : avx512_perm_t_sizes<0x7F, "vpermt2pd",
1439 avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1441 //===----------------------------------------------------------------------===//
1442 // AVX-512 - BLEND using mask
1444 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1445 let ExeDomain = _.ExeDomain, hasSideEffects = 0 in {
1446 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1447 (ins _.RC:$src1, _.RC:$src2),
1448 !strconcat(OpcodeStr,
1449 "\t{$src2, $src1, ${dst}|${dst}, $src1, $src2}"),
1451 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1452 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1453 !strconcat(OpcodeStr,
1454 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1455 []>, EVEX_4V, EVEX_K;
1456 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1457 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1458 !strconcat(OpcodeStr,
1459 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1460 []>, EVEX_4V, EVEX_KZ;
1461 let mayLoad = 1 in {
1462 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1463 (ins _.RC:$src1, _.MemOp:$src2),
1464 !strconcat(OpcodeStr,
1465 "\t{$src2, $src1, ${dst}|${dst}, $src1, $src2}"),
1466 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1467 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1468 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1469 !strconcat(OpcodeStr,
1470 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1471 []>, EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1472 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1473 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1474 !strconcat(OpcodeStr,
1475 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1476 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1480 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1482 let mayLoad = 1, hasSideEffects = 0 in {
1483 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1484 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1485 !strconcat(OpcodeStr,
1486 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1487 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1488 []>, EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1490 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1491 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1492 !strconcat(OpcodeStr,
1493 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1494 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1495 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1499 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1500 AVX512VLVectorVTInfo VTInfo> {
1501 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1502 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1504 let Predicates = [HasVLX] in {
1505 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1506 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1507 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1508 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1512 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1513 AVX512VLVectorVTInfo VTInfo> {
1514 let Predicates = [HasBWI] in
1515 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1517 let Predicates = [HasBWI, HasVLX] in {
1518 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1519 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1524 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1525 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1526 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1527 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1528 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1529 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1532 //===----------------------------------------------------------------------===//
1533 // Compare Instructions
1534 //===----------------------------------------------------------------------===//
1536 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1538 multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>{
1540 defm rr_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1542 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1543 "vcmp${cc}"#_.Suffix,
1544 "$src2, $src1", "$src1, $src2",
1545 (OpNode (_.VT _.RC:$src1),
1549 defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1551 (ins _.RC:$src1, _.IntScalarMemOp:$src2, AVXCC:$cc),
1552 "vcmp${cc}"#_.Suffix,
1553 "$src2, $src1", "$src1, $src2",
1554 (OpNode (_.VT _.RC:$src1), _.ScalarIntMemCPat:$src2,
1555 imm:$cc)>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1557 defm rrb_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1559 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1560 "vcmp${cc}"#_.Suffix,
1561 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
1562 (OpNodeRnd (_.VT _.RC:$src1),
1565 (i32 FROUND_NO_EXC))>, EVEX_4V, EVEX_B;
1566 // Accept explicit immediate argument form instead of comparison code.
1567 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1568 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1570 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1572 "$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V;
1574 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1576 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1578 "$cc, $src2, $src1", "$src1, $src2, $cc">,
1579 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1581 defm rrb_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1583 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1585 "$cc, {sae}, $src2, $src1","$src1, $src2, {sae}, $cc">,
1587 }// let isAsmParserOnly = 1, hasSideEffects = 0
1589 let isCodeGenOnly = 1 in {
1590 let isCommutable = 1 in
1591 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1592 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc),
1593 !strconcat("vcmp${cc}", _.Suffix,
1594 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1595 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1598 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1599 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1601 (ins _.FRC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1602 !strconcat("vcmp${cc}", _.Suffix,
1603 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1604 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1605 (_.ScalarLdFrag addr:$src2),
1607 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1611 let Predicates = [HasAVX512] in {
1612 let ExeDomain = SSEPackedSingle in
1613 defm VCMPSSZ : avx512_cmp_scalar<f32x_info, X86cmpms, X86cmpmsRnd>,
1615 let ExeDomain = SSEPackedDouble in
1616 defm VCMPSDZ : avx512_cmp_scalar<f64x_info, X86cmpms, X86cmpmsRnd>,
1617 AVX512XDIi8Base, VEX_W;
1620 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1621 X86VectorVTInfo _, bit IsCommutable> {
1622 let isCommutable = IsCommutable in
1623 def rr : AVX512BI<opc, MRMSrcReg,
1624 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1625 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1626 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1627 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1628 def rm : AVX512BI<opc, MRMSrcMem,
1629 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1630 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1631 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1632 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1633 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1634 let isCommutable = IsCommutable in
1635 def rrk : AVX512BI<opc, MRMSrcReg,
1636 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1637 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1638 "$dst {${mask}}, $src1, $src2}"),
1639 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1640 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1641 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1642 def rmk : AVX512BI<opc, MRMSrcMem,
1643 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1644 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1645 "$dst {${mask}}, $src1, $src2}"),
1646 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1647 (OpNode (_.VT _.RC:$src1),
1649 (_.LdFrag addr:$src2))))))],
1650 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1653 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1654 X86VectorVTInfo _, bit IsCommutable> :
1655 avx512_icmp_packed<opc, OpcodeStr, OpNode, _, IsCommutable> {
1656 def rmb : AVX512BI<opc, MRMSrcMem,
1657 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1658 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1659 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1660 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1661 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1662 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1663 def rmbk : AVX512BI<opc, MRMSrcMem,
1664 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1665 _.ScalarMemOp:$src2),
1666 !strconcat(OpcodeStr,
1667 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1668 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1669 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1670 (OpNode (_.VT _.RC:$src1),
1672 (_.ScalarLdFrag addr:$src2)))))],
1673 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1676 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1677 AVX512VLVectorVTInfo VTInfo, Predicate prd,
1678 bit IsCommutable = 0> {
1679 let Predicates = [prd] in
1680 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512,
1681 IsCommutable>, EVEX_V512;
1683 let Predicates = [prd, HasVLX] in {
1684 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256,
1685 IsCommutable>, EVEX_V256;
1686 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128,
1687 IsCommutable>, EVEX_V128;
1691 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1692 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1693 Predicate prd, bit IsCommutable = 0> {
1694 let Predicates = [prd] in
1695 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512,
1696 IsCommutable>, EVEX_V512;
1698 let Predicates = [prd, HasVLX] in {
1699 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256,
1700 IsCommutable>, EVEX_V256;
1701 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128,
1702 IsCommutable>, EVEX_V128;
1706 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1707 avx512vl_i8_info, HasBWI, 1>,
1710 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1711 avx512vl_i16_info, HasBWI, 1>,
1712 EVEX_CD8<16, CD8VF>;
1714 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1715 avx512vl_i32_info, HasAVX512, 1>,
1716 EVEX_CD8<32, CD8VF>;
1718 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1719 avx512vl_i64_info, HasAVX512, 1>,
1720 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1722 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1723 avx512vl_i8_info, HasBWI>,
1726 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1727 avx512vl_i16_info, HasBWI>,
1728 EVEX_CD8<16, CD8VF>;
1730 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1731 avx512vl_i32_info, HasAVX512>,
1732 EVEX_CD8<32, CD8VF>;
1734 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1735 avx512vl_i64_info, HasAVX512>,
1736 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1738 let Predicates = [HasAVX512, NoVLX] in {
1739 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1740 (COPY_TO_REGCLASS (VPCMPGTDZrr
1741 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)),
1742 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src2, sub_ymm))), VK8)>;
1744 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1745 (COPY_TO_REGCLASS (VPCMPEQDZrr
1746 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)),
1747 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src2, sub_ymm))), VK8)>;
1750 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1751 X86VectorVTInfo _> {
1752 let isCommutable = 1 in
1753 def rri : AVX512AIi8<opc, MRMSrcReg,
1754 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1755 !strconcat("vpcmp${cc}", Suffix,
1756 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1757 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1759 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1760 def rmi : AVX512AIi8<opc, MRMSrcMem,
1761 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1762 !strconcat("vpcmp${cc}", Suffix,
1763 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1764 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1765 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1767 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1768 let isCommutable = 1 in
1769 def rrik : AVX512AIi8<opc, MRMSrcReg,
1770 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1772 !strconcat("vpcmp${cc}", Suffix,
1773 "\t{$src2, $src1, $dst {${mask}}|",
1774 "$dst {${mask}}, $src1, $src2}"),
1775 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1776 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1778 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1779 def rmik : AVX512AIi8<opc, MRMSrcMem,
1780 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1782 !strconcat("vpcmp${cc}", Suffix,
1783 "\t{$src2, $src1, $dst {${mask}}|",
1784 "$dst {${mask}}, $src1, $src2}"),
1785 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1786 (OpNode (_.VT _.RC:$src1),
1787 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1789 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1791 // Accept explicit immediate argument form instead of comparison code.
1792 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1793 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1794 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1795 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1796 "$dst, $src1, $src2, $cc}"),
1797 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1799 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1800 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1801 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1802 "$dst, $src1, $src2, $cc}"),
1803 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1804 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1805 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1807 !strconcat("vpcmp", Suffix,
1808 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1809 "$dst {${mask}}, $src1, $src2, $cc}"),
1810 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1812 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1813 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1815 !strconcat("vpcmp", Suffix,
1816 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1817 "$dst {${mask}}, $src1, $src2, $cc}"),
1818 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1822 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1823 X86VectorVTInfo _> :
1824 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1825 def rmib : AVX512AIi8<opc, MRMSrcMem,
1826 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1828 !strconcat("vpcmp${cc}", Suffix,
1829 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1830 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1831 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1832 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1834 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1835 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1836 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1837 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1838 !strconcat("vpcmp${cc}", Suffix,
1839 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1840 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1841 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1842 (OpNode (_.VT _.RC:$src1),
1843 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1845 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1847 // Accept explicit immediate argument form instead of comparison code.
1848 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1849 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1850 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1852 !strconcat("vpcmp", Suffix,
1853 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1854 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1855 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1856 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1857 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1858 _.ScalarMemOp:$src2, u8imm:$cc),
1859 !strconcat("vpcmp", Suffix,
1860 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1861 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1862 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1866 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1867 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1868 let Predicates = [prd] in
1869 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1871 let Predicates = [prd, HasVLX] in {
1872 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1873 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1877 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1878 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1879 let Predicates = [prd] in
1880 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1883 let Predicates = [prd, HasVLX] in {
1884 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1886 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1891 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1892 HasBWI>, EVEX_CD8<8, CD8VF>;
1893 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1894 HasBWI>, EVEX_CD8<8, CD8VF>;
1896 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1897 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1898 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1899 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1901 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1902 HasAVX512>, EVEX_CD8<32, CD8VF>;
1903 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1904 HasAVX512>, EVEX_CD8<32, CD8VF>;
1906 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1907 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1908 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1909 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1911 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1913 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1914 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1915 "vcmp${cc}"#_.Suffix,
1916 "$src2, $src1", "$src1, $src2",
1917 (X86cmpm (_.VT _.RC:$src1),
1921 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1922 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1923 "vcmp${cc}"#_.Suffix,
1924 "$src2, $src1", "$src1, $src2",
1925 (X86cmpm (_.VT _.RC:$src1),
1926 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1929 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1931 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1932 "vcmp${cc}"#_.Suffix,
1933 "${src2}"##_.BroadcastStr##", $src1",
1934 "$src1, ${src2}"##_.BroadcastStr,
1935 (X86cmpm (_.VT _.RC:$src1),
1936 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1938 // Accept explicit immediate argument form instead of comparison code.
1939 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1940 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1942 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1944 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1946 let mayLoad = 1 in {
1947 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1949 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1951 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1953 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1955 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1957 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1958 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1963 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1964 // comparison code form (VCMP[EQ/LT/LE/...]
1965 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1966 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1967 "vcmp${cc}"#_.Suffix,
1968 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
1969 (X86cmpmRnd (_.VT _.RC:$src1),
1972 (i32 FROUND_NO_EXC))>, EVEX_B;
1974 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1975 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1977 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1979 "$cc, {sae}, $src2, $src1",
1980 "$src1, $src2, {sae}, $cc">, EVEX_B;
1984 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1985 let Predicates = [HasAVX512] in {
1986 defm Z : avx512_vcmp_common<_.info512>,
1987 avx512_vcmp_sae<_.info512>, EVEX_V512;
1990 let Predicates = [HasAVX512,HasVLX] in {
1991 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1992 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1996 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1997 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1998 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1999 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
2001 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
2002 (COPY_TO_REGCLASS (VCMPPSZrri
2003 (v16f32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)),
2004 (v16f32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src2, sub_ymm)),
2006 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
2007 (COPY_TO_REGCLASS (VPCMPDZrri
2008 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)),
2009 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src2, sub_ymm)),
2011 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
2012 (COPY_TO_REGCLASS (VPCMPUDZrri
2013 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)),
2014 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src2, sub_ymm)),
2017 // ----------------------------------------------------------------
2019 //handle fpclass instruction mask = op(reg_scalar,imm)
2020 // op(mem_scalar,imm)
2021 multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
2022 X86VectorVTInfo _, Predicate prd> {
2023 let Predicates = [prd] in {
2024 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),//_.KRC:$dst),
2025 (ins _.RC:$src1, i32u8imm:$src2),
2026 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2027 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
2028 (i32 imm:$src2)))], NoItinerary>;
2029 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
2030 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
2031 OpcodeStr##_.Suffix#
2032 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
2033 [(set _.KRC:$dst,(or _.KRCWM:$mask,
2034 (OpNode (_.VT _.RC:$src1),
2035 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
2036 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
2037 (ins _.MemOp:$src1, i32u8imm:$src2),
2038 OpcodeStr##_.Suffix##
2039 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2041 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
2042 (i32 imm:$src2)))], NoItinerary>;
2043 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
2044 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
2045 OpcodeStr##_.Suffix##
2046 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
2047 [(set _.KRC:$dst,(or _.KRCWM:$mask,
2048 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
2049 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
2053 //handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm)
2054 // fpclass(reg_vec, mem_vec, imm)
2055 // fpclass(reg_vec, broadcast(eltVt), imm)
2056 multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
2057 X86VectorVTInfo _, string mem, string broadcast>{
2058 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
2059 (ins _.RC:$src1, i32u8imm:$src2),
2060 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2061 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
2062 (i32 imm:$src2)))], NoItinerary>;
2063 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
2064 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
2065 OpcodeStr##_.Suffix#
2066 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
2067 [(set _.KRC:$dst,(or _.KRCWM:$mask,
2068 (OpNode (_.VT _.RC:$src1),
2069 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
2070 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
2071 (ins _.MemOp:$src1, i32u8imm:$src2),
2072 OpcodeStr##_.Suffix##mem#
2073 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2074 [(set _.KRC:$dst,(OpNode
2075 (_.VT (bitconvert (_.LdFrag addr:$src1))),
2076 (i32 imm:$src2)))], NoItinerary>;
2077 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
2078 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
2079 OpcodeStr##_.Suffix##mem#
2080 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
2081 [(set _.KRC:$dst, (or _.KRCWM:$mask, (OpNode
2082 (_.VT (bitconvert (_.LdFrag addr:$src1))),
2083 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
2084 def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
2085 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
2086 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
2087 _.BroadcastStr##", $dst|$dst, ${src1}"
2088 ##_.BroadcastStr##", $src2}",
2089 [(set _.KRC:$dst,(OpNode
2090 (_.VT (X86VBroadcast
2091 (_.ScalarLdFrag addr:$src1))),
2092 (i32 imm:$src2)))], NoItinerary>,EVEX_B;
2093 def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
2094 (ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
2095 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
2096 _.BroadcastStr##", $dst {${mask}}|$dst {${mask}}, ${src1}"##
2097 _.BroadcastStr##", $src2}",
2098 [(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode
2099 (_.VT (X86VBroadcast
2100 (_.ScalarLdFrag addr:$src1))),
2101 (i32 imm:$src2))))], NoItinerary>,
2105 multiclass avx512_vector_fpclass_all<string OpcodeStr,
2106 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd,
2108 let Predicates = [prd] in {
2109 defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info512, "{z}",
2110 broadcast>, EVEX_V512;
2112 let Predicates = [prd, HasVLX] in {
2113 defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info128, "{x}",
2114 broadcast>, EVEX_V128;
2115 defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info256, "{y}",
2116 broadcast>, EVEX_V256;
2120 multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
2121 bits<8> opcScalar, SDNode VecOpNode, SDNode ScalarOpNode, Predicate prd>{
2122 defm PS : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f32_info, opcVec,
2123 VecOpNode, prd, "{l}">, EVEX_CD8<32, CD8VF>;
2124 defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec,
2125 VecOpNode, prd, "{q}">,EVEX_CD8<64, CD8VF> , VEX_W;
2126 defm SS : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
2127 f32x_info, prd>, EVEX_CD8<32, CD8VT1>;
2128 defm SD : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
2129 f64x_info, prd>, EVEX_CD8<64, CD8VT1>, VEX_W;
2132 defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass,
2133 X86Vfpclasss, HasDQI>, AVX512AIi8Base,EVEX;
2135 //-----------------------------------------------------------------
2136 // Mask register copy, including
2137 // - copy between mask registers
2138 // - load/store mask registers
2139 // - copy from GPR to mask register and vice versa
2141 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
2142 string OpcodeStr, RegisterClass KRC,
2143 ValueType vvt, X86MemOperand x86memop> {
2144 let hasSideEffects = 0 in
2145 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2146 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2147 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
2148 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2149 [(set KRC:$dst, (vvt (load addr:$src)))]>;
2150 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
2151 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2152 [(store KRC:$src, addr:$dst)]>;
2155 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
2157 RegisterClass KRC, RegisterClass GRC> {
2158 let hasSideEffects = 0 in {
2159 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
2160 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2161 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
2162 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2166 let Predicates = [HasDQI] in
2167 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
2168 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
2171 let Predicates = [HasAVX512] in
2172 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
2173 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
2176 let Predicates = [HasBWI] in {
2177 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
2179 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
2181 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
2183 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
2187 // GR from/to mask register
2188 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
2189 (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), GR16:$src, sub_16bit)), VK16)>;
2190 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
2191 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS VK16:$src, GR32)), sub_16bit)>;
2193 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2194 (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), GR8:$src, sub_8bit)), VK8)>;
2195 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2196 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS VK8:$src, GR32)), sub_8bit)>;
2198 def : Pat<(i32 (zext (i16 (bitconvert (v16i1 VK16:$src))))),
2199 (KMOVWrk VK16:$src)>;
2200 def : Pat<(i32 (anyext (i16 (bitconvert (v16i1 VK16:$src))))),
2201 (COPY_TO_REGCLASS VK16:$src, GR32)>;
2203 def : Pat<(i32 (zext (i8 (bitconvert (v8i1 VK8:$src))))),
2204 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS VK8:$src, GR32)), sub_8bit))>, Requires<[NoDQI]>;
2205 def : Pat<(i32 (zext (i8 (bitconvert (v8i1 VK8:$src))))),
2206 (KMOVBrk VK8:$src)>, Requires<[HasDQI]>;
2207 def : Pat<(i32 (anyext (i8 (bitconvert (v8i1 VK8:$src))))),
2208 (COPY_TO_REGCLASS VK8:$src, GR32)>;
2210 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))),
2211 (COPY_TO_REGCLASS GR32:$src, VK32)>;
2212 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))),
2213 (COPY_TO_REGCLASS VK32:$src, GR32)>;
2214 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))),
2215 (COPY_TO_REGCLASS GR64:$src, VK64)>;
2216 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))),
2217 (COPY_TO_REGCLASS VK64:$src, GR64)>;
2220 let Predicates = [HasDQI] in {
2221 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2222 (KMOVBmk addr:$dst, VK8:$src)>;
2223 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2224 (KMOVBkm addr:$src)>;
2226 def : Pat<(store VK4:$src, addr:$dst),
2227 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
2228 def : Pat<(store VK2:$src, addr:$dst),
2229 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK2:$src, VK8))>;
2230 def : Pat<(store VK1:$src, addr:$dst),
2231 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK8))>;
2233 def : Pat<(v2i1 (load addr:$src)),
2234 (COPY_TO_REGCLASS (KMOVBkm addr:$src), VK2)>;
2235 def : Pat<(v4i1 (load addr:$src)),
2236 (COPY_TO_REGCLASS (KMOVBkm addr:$src), VK4)>;
2238 let Predicates = [HasAVX512, NoDQI] in {
2239 def : Pat<(store VK1:$src, addr:$dst),
2241 (i8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS VK1:$src, GR32)),
2243 def : Pat<(store VK2:$src, addr:$dst),
2245 (i8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS VK2:$src, GR32)),
2247 def : Pat<(store VK4:$src, addr:$dst),
2249 (i8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS VK4:$src, GR32)),
2251 def : Pat<(store VK8:$src, addr:$dst),
2253 (i8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS VK8:$src, GR32)),
2256 def : Pat<(v8i1 (load addr:$src)),
2257 (COPY_TO_REGCLASS (MOVZX32rm8 addr:$src), VK8)>;
2258 def : Pat<(v2i1 (load addr:$src)),
2259 (COPY_TO_REGCLASS (MOVZX32rm8 addr:$src), VK2)>;
2260 def : Pat<(v4i1 (load addr:$src)),
2261 (COPY_TO_REGCLASS (MOVZX32rm8 addr:$src), VK4)>;
2264 let Predicates = [HasAVX512] in {
2265 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
2266 (KMOVWmk addr:$dst, VK16:$src)>;
2267 def : Pat<(v1i1 (load addr:$src)),
2268 (COPY_TO_REGCLASS (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1)), VK1)>;
2269 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
2270 (KMOVWkm addr:$src)>;
2272 let Predicates = [HasBWI] in {
2273 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
2274 (KMOVDmk addr:$dst, VK32:$src)>;
2275 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
2276 (KMOVDkm addr:$src)>;
2277 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
2278 (KMOVQmk addr:$dst, VK64:$src)>;
2279 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
2280 (KMOVQkm addr:$src)>;
2283 let Predicates = [HasAVX512] in {
2284 multiclass operation_gpr_mask_copy_lowering<RegisterClass maskRC, ValueType maskVT> {
2285 def : Pat<(maskVT (scalar_to_vector GR32:$src)),
2286 (COPY_TO_REGCLASS GR32:$src, maskRC)>;
2288 def : Pat<(i32 (X86Vextract maskRC:$src, (iPTR 0))),
2289 (COPY_TO_REGCLASS maskRC:$src, GR32)>;
2291 def : Pat<(maskVT (scalar_to_vector GR8:$src)),
2292 (COPY_TO_REGCLASS (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, sub_8bit), maskRC)>;
2294 def : Pat<(i8 (X86Vextract maskRC:$src, (iPTR 0))),
2295 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS maskRC:$src, GR32)), sub_8bit)>;
2297 def : Pat<(i32 (anyext (i8 (X86Vextract maskRC:$src, (iPTR 0))))),
2298 (COPY_TO_REGCLASS maskRC:$src, GR32)>;
2301 defm : operation_gpr_mask_copy_lowering<VK1, v1i1>;
2302 defm : operation_gpr_mask_copy_lowering<VK2, v2i1>;
2303 defm : operation_gpr_mask_copy_lowering<VK4, v4i1>;
2304 defm : operation_gpr_mask_copy_lowering<VK8, v8i1>;
2305 defm : operation_gpr_mask_copy_lowering<VK16, v16i1>;
2306 defm : operation_gpr_mask_copy_lowering<VK32, v32i1>;
2307 defm : operation_gpr_mask_copy_lowering<VK64, v64i1>;
2309 def : Pat<(X86kshiftr (X86kshiftl (v1i1 (scalar_to_vector GR8:$src)), (i8 15)), (i8 15)) ,
2311 (KMOVWkr (AND32ri8 (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
2312 GR8:$src, sub_8bit), (i32 1))), VK1)>;
2313 def : Pat<(X86kshiftr (X86kshiftl (v16i1 (scalar_to_vector GR8:$src)), (i8 15)), (i8 15)) ,
2315 (KMOVWkr (AND32ri8 (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
2316 GR8:$src, sub_8bit), (i32 1))), VK16)>;
2317 def : Pat<(X86kshiftr (X86kshiftl (v8i1 (scalar_to_vector GR8:$src)), (i8 15)), (i8 15)) ,
2319 (KMOVWkr (AND32ri8 (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
2320 GR8:$src, sub_8bit), (i32 1))), VK8)>;
2324 // Mask unary operation
2326 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
2327 RegisterClass KRC, SDPatternOperator OpNode,
2329 let Predicates = [prd] in
2330 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2331 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2332 [(set KRC:$dst, (OpNode KRC:$src))]>;
2335 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
2336 SDPatternOperator OpNode> {
2337 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2339 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2340 HasAVX512>, VEX, PS;
2341 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2342 HasBWI>, VEX, PD, VEX_W;
2343 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2344 HasBWI>, VEX, PS, VEX_W;
2347 defm KNOT : avx512_mask_unop_all<0x44, "knot", vnot>;
2349 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
2350 let Predicates = [HasAVX512, NoDQI] in
2351 def : Pat<(vnot VK8:$src),
2352 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
2354 def : Pat<(vnot VK4:$src),
2355 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src, VK16)), VK4)>;
2356 def : Pat<(vnot VK2:$src),
2357 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src, VK16)), VK2)>;
2359 // Mask binary operation
2360 // - KAND, KANDN, KOR, KXNOR, KXOR
2361 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
2362 RegisterClass KRC, SDPatternOperator OpNode,
2363 Predicate prd, bit IsCommutable> {
2364 let Predicates = [prd], isCommutable = IsCommutable in
2365 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2366 !strconcat(OpcodeStr,
2367 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2368 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
2371 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
2372 SDPatternOperator OpNode, bit IsCommutable,
2373 Predicate prdW = HasAVX512> {
2374 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2375 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2376 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2377 prdW, IsCommutable>, VEX_4V, VEX_L, PS;
2378 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2379 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2380 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2381 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2384 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
2385 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
2386 // These nodes use 'vnot' instead of 'not' to support vectors.
2387 def vandn : PatFrag<(ops node:$i0, node:$i1), (and (vnot node:$i0), node:$i1)>;
2388 def vxnor : PatFrag<(ops node:$i0, node:$i1), (vnot (xor node:$i0, node:$i1))>;
2390 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
2391 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
2392 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", vxnor, 1>;
2393 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
2394 defm KANDN : avx512_mask_binop_all<0x42, "kandn", vandn, 0>;
2395 defm KADD : avx512_mask_binop_all<0x4A, "kadd", add, 1, HasDQI>;
2397 multiclass avx512_binop_pat<SDPatternOperator VOpNode, SDPatternOperator OpNode,
2399 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
2400 // for the DQI set, this type is legal and KxxxB instruction is used
2401 let Predicates = [NoDQI] in
2402 def : Pat<(VOpNode VK8:$src1, VK8:$src2),
2404 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2405 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2407 // All types smaller than 8 bits require conversion anyway
2408 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2409 (COPY_TO_REGCLASS (Inst
2410 (COPY_TO_REGCLASS VK1:$src1, VK16),
2411 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2412 def : Pat<(VOpNode VK2:$src1, VK2:$src2),
2413 (COPY_TO_REGCLASS (Inst
2414 (COPY_TO_REGCLASS VK2:$src1, VK16),
2415 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2416 def : Pat<(VOpNode VK4:$src1, VK4:$src2),
2417 (COPY_TO_REGCLASS (Inst
2418 (COPY_TO_REGCLASS VK4:$src1, VK16),
2419 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2422 defm : avx512_binop_pat<and, and, KANDWrr>;
2423 defm : avx512_binop_pat<vandn, andn, KANDNWrr>;
2424 defm : avx512_binop_pat<or, or, KORWrr>;
2425 defm : avx512_binop_pat<vxnor, xnor, KXNORWrr>;
2426 defm : avx512_binop_pat<xor, xor, KXORWrr>;
2429 multiclass avx512_mask_unpck<string Suffix,RegisterClass KRC, ValueType VT,
2430 RegisterClass KRCSrc, Predicate prd> {
2431 let Predicates = [prd] in {
2432 let hasSideEffects = 0 in
2433 def rr : I<0x4b, MRMSrcReg, (outs KRC:$dst),
2434 (ins KRC:$src1, KRC:$src2),
2435 "kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2438 def : Pat<(VT (concat_vectors KRCSrc:$src1, KRCSrc:$src2)),
2439 (!cast<Instruction>(NAME##rr)
2440 (COPY_TO_REGCLASS KRCSrc:$src2, KRC),
2441 (COPY_TO_REGCLASS KRCSrc:$src1, KRC))>;
2445 defm KUNPCKBW : avx512_mask_unpck<"bw", VK16, v16i1, VK8, HasAVX512>, PD;
2446 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, HasBWI>, PS;
2447 defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, HasBWI>, PS, VEX_W;
2450 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2451 SDNode OpNode, Predicate prd> {
2452 let Predicates = [prd], Defs = [EFLAGS] in
2453 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2454 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2455 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2458 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2459 Predicate prdW = HasAVX512> {
2460 defm B : avx512_mask_testop<opc, OpcodeStr#"b", VK8, OpNode, HasDQI>,
2462 defm W : avx512_mask_testop<opc, OpcodeStr#"w", VK16, OpNode, prdW>,
2464 defm Q : avx512_mask_testop<opc, OpcodeStr#"q", VK64, OpNode, HasBWI>,
2466 defm D : avx512_mask_testop<opc, OpcodeStr#"d", VK32, OpNode, HasBWI>,
2470 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2471 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest, HasDQI>;
2474 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2476 let Predicates = [HasAVX512] in
2477 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2478 !strconcat(OpcodeStr,
2479 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2480 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2483 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2485 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2487 let Predicates = [HasDQI] in
2488 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2490 let Predicates = [HasBWI] in {
2491 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2493 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2498 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86kshiftl>;
2499 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86kshiftr>;
2501 // Mask setting all 0s or 1s
2502 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2503 let Predicates = [HasAVX512] in
2504 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2505 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2506 [(set KRC:$dst, (VT Val))]>;
2509 multiclass avx512_mask_setop_w<PatFrag Val> {
2510 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2511 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2512 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2515 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2516 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2518 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2519 let Predicates = [HasAVX512] in {
2520 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2521 def : Pat<(v4i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK4)>;
2522 def : Pat<(v2i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK2)>;
2523 def : Pat<(v1i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2524 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2525 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2526 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2527 def : Pat<(v1i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK1)>;
2530 // Patterns for kmask insert_subvector/extract_subvector to/from index=0
2531 multiclass operation_subvector_mask_lowering<RegisterClass subRC, ValueType subVT,
2532 RegisterClass RC, ValueType VT> {
2533 def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))),
2534 (subVT (COPY_TO_REGCLASS RC:$src, subRC))>;
2536 def : Pat<(VT (insert_subvector undef, subRC:$src, (iPTR 0))),
2537 (VT (COPY_TO_REGCLASS subRC:$src, RC))>;
2539 defm : operation_subvector_mask_lowering<VK1, v1i1, VK2, v2i1>;
2540 defm : operation_subvector_mask_lowering<VK1, v1i1, VK4, v4i1>;
2541 defm : operation_subvector_mask_lowering<VK1, v1i1, VK8, v8i1>;
2542 defm : operation_subvector_mask_lowering<VK1, v1i1, VK16, v16i1>;
2543 defm : operation_subvector_mask_lowering<VK1, v1i1, VK32, v32i1>;
2544 defm : operation_subvector_mask_lowering<VK1, v1i1, VK64, v64i1>;
2546 defm : operation_subvector_mask_lowering<VK2, v2i1, VK4, v4i1>;
2547 defm : operation_subvector_mask_lowering<VK2, v2i1, VK8, v8i1>;
2548 defm : operation_subvector_mask_lowering<VK2, v2i1, VK16, v16i1>;
2549 defm : operation_subvector_mask_lowering<VK2, v2i1, VK32, v32i1>;
2550 defm : operation_subvector_mask_lowering<VK2, v2i1, VK64, v64i1>;
2552 defm : operation_subvector_mask_lowering<VK4, v4i1, VK8, v8i1>;
2553 defm : operation_subvector_mask_lowering<VK4, v4i1, VK16, v16i1>;
2554 defm : operation_subvector_mask_lowering<VK4, v4i1, VK32, v32i1>;
2555 defm : operation_subvector_mask_lowering<VK4, v4i1, VK64, v64i1>;
2557 defm : operation_subvector_mask_lowering<VK8, v8i1, VK16, v16i1>;
2558 defm : operation_subvector_mask_lowering<VK8, v8i1, VK32, v32i1>;
2559 defm : operation_subvector_mask_lowering<VK8, v8i1, VK64, v64i1>;
2561 defm : operation_subvector_mask_lowering<VK16, v16i1, VK32, v32i1>;
2562 defm : operation_subvector_mask_lowering<VK16, v16i1, VK64, v64i1>;
2564 defm : operation_subvector_mask_lowering<VK32, v32i1, VK64, v64i1>;
2566 def : Pat<(v2i1 (extract_subvector (v4i1 VK4:$src), (iPTR 2))),
2567 (v2i1 (COPY_TO_REGCLASS
2568 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16), (i8 2)),
2570 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 4))),
2571 (v4i1 (COPY_TO_REGCLASS
2572 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (i8 4)),
2574 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2575 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2576 def : Pat<(v16i1 (extract_subvector (v32i1 VK32:$src), (iPTR 16))),
2577 (v16i1 (COPY_TO_REGCLASS (KSHIFTRDri VK32:$src, (i8 16)), VK16))>;
2578 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2579 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2582 // Patterns for kmask shift
2583 multiclass mask_shift_lowering<RegisterClass RC, ValueType VT> {
2584 def : Pat<(VT (X86kshiftl RC:$src, (i8 imm:$imm))),
2585 (VT (COPY_TO_REGCLASS
2586 (KSHIFTLWri (COPY_TO_REGCLASS RC:$src, VK16),
2589 def : Pat<(VT (X86kshiftr RC:$src, (i8 imm:$imm))),
2590 (VT (COPY_TO_REGCLASS
2591 (KSHIFTRWri (COPY_TO_REGCLASS RC:$src, VK16),
2596 defm : mask_shift_lowering<VK8, v8i1>, Requires<[HasAVX512, NoDQI]>;
2597 defm : mask_shift_lowering<VK4, v4i1>, Requires<[HasAVX512]>;
2598 defm : mask_shift_lowering<VK2, v2i1>, Requires<[HasAVX512]>;
2599 //===----------------------------------------------------------------------===//
2600 // AVX-512 - Aligned and unaligned load and store
2604 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2605 PatFrag ld_frag, PatFrag mload,
2606 SDPatternOperator SelectOprr = vselect> {
2607 let hasSideEffects = 0 in {
2608 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2609 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2611 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2612 (ins _.KRCWM:$mask, _.RC:$src),
2613 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2614 "${dst} {${mask}} {z}, $src}"),
2615 [(set _.RC:$dst, (_.VT (SelectOprr _.KRCWM:$mask,
2617 _.ImmAllZerosV)))], _.ExeDomain>,
2620 let canFoldAsLoad = 1, isReMaterializable = 1,
2621 SchedRW = [WriteLoad] in
2622 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2623 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2624 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2627 let Constraints = "$src0 = $dst", isConvertibleToThreeAddress = 1 in {
2628 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2629 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2630 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2631 "${dst} {${mask}}, $src1}"),
2632 [(set _.RC:$dst, (_.VT (SelectOprr _.KRCWM:$mask,
2634 (_.VT _.RC:$src0))))], _.ExeDomain>,
2636 let SchedRW = [WriteLoad] in
2637 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2638 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2639 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2640 "${dst} {${mask}}, $src1}"),
2641 [(set _.RC:$dst, (_.VT
2642 (vselect _.KRCWM:$mask,
2643 (_.VT (bitconvert (ld_frag addr:$src1))),
2644 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2646 let SchedRW = [WriteLoad] in
2647 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2648 (ins _.KRCWM:$mask, _.MemOp:$src),
2649 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2650 "${dst} {${mask}} {z}, $src}",
2651 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2652 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2653 _.ExeDomain>, EVEX, EVEX_KZ;
2655 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2656 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2658 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2659 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2661 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2662 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2663 _.KRCWM:$mask, addr:$ptr)>;
2666 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2667 AVX512VLVectorVTInfo _,
2669 let Predicates = [prd] in
2670 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2671 masked_load_aligned512>, EVEX_V512;
2673 let Predicates = [prd, HasVLX] in {
2674 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2675 masked_load_aligned256>, EVEX_V256;
2676 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2677 masked_load_aligned128>, EVEX_V128;
2681 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2682 AVX512VLVectorVTInfo _,
2684 SDPatternOperator SelectOprr = vselect> {
2685 let Predicates = [prd] in
2686 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2687 masked_load_unaligned, SelectOprr>, EVEX_V512;
2689 let Predicates = [prd, HasVLX] in {
2690 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2691 masked_load_unaligned, SelectOprr>, EVEX_V256;
2692 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2693 masked_load_unaligned, SelectOprr>, EVEX_V128;
2697 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2698 PatFrag st_frag, PatFrag mstore, string Name> {
2700 let hasSideEffects = 0 in {
2701 def rr_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2702 OpcodeStr # ".s\t{$src, $dst|$dst, $src}",
2703 [], _.ExeDomain>, EVEX, FoldGenData<Name#rr>;
2704 def rrk_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2705 (ins _.KRCWM:$mask, _.RC:$src),
2706 OpcodeStr # ".s\t{$src, ${dst} {${mask}}|"#
2707 "${dst} {${mask}}, $src}",
2708 [], _.ExeDomain>, EVEX, EVEX_K, FoldGenData<Name#rrk>;
2709 def rrkz_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2710 (ins _.KRCWM:$mask, _.RC:$src),
2711 OpcodeStr # ".s\t{$src, ${dst} {${mask}} {z}|" #
2712 "${dst} {${mask}} {z}, $src}",
2713 [], _.ExeDomain>, EVEX, EVEX_KZ, FoldGenData<Name#rrkz>;
2716 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2717 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2718 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2719 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2720 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2721 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2722 [], _.ExeDomain>, EVEX, EVEX_K;
2724 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2725 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2726 _.KRCWM:$mask, _.RC:$src)>;
2730 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2731 AVX512VLVectorVTInfo _, Predicate prd,
2733 let Predicates = [prd] in
2734 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2735 masked_store_unaligned, Name#Z>, EVEX_V512;
2737 let Predicates = [prd, HasVLX] in {
2738 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2739 masked_store_unaligned, Name#Z256>, EVEX_V256;
2740 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2741 masked_store_unaligned, Name#Z128>, EVEX_V128;
2745 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2746 AVX512VLVectorVTInfo _, Predicate prd,
2748 let Predicates = [prd] in
2749 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2750 masked_store_aligned512, Name#Z>, EVEX_V512;
2752 let Predicates = [prd, HasVLX] in {
2753 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2754 masked_store_aligned256, Name#Z256>, EVEX_V256;
2755 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2756 masked_store_aligned128, Name#Z128>, EVEX_V128;
2760 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2762 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2763 HasAVX512, "VMOVAPS">,
2764 PS, EVEX_CD8<32, CD8VF>;
2766 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2768 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2769 HasAVX512, "VMOVAPD">,
2770 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2772 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512,
2774 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512,
2776 PS, EVEX_CD8<32, CD8VF>;
2778 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512,
2780 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512,
2782 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2784 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2786 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2787 HasAVX512, "VMOVDQA32">,
2788 PD, EVEX_CD8<32, CD8VF>;
2790 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2792 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2793 HasAVX512, "VMOVDQA64">,
2794 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2796 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2797 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2798 HasBWI, "VMOVDQU8">,
2799 XD, EVEX_CD8<8, CD8VF>;
2801 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2802 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2803 HasBWI, "VMOVDQU16">,
2804 XD, VEX_W, EVEX_CD8<16, CD8VF>;
2806 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512,
2808 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2809 HasAVX512, "VMOVDQU32">,
2810 XS, EVEX_CD8<32, CD8VF>;
2812 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512,
2814 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2815 HasAVX512, "VMOVDQU64">,
2816 XS, VEX_W, EVEX_CD8<64, CD8VF>;
2818 // Special instructions to help with spilling when we don't have VLX. We need
2819 // to load or store from a ZMM register instead. These are converted in
2820 // expandPostRAPseudos.
2821 let isReMaterializable = 1, canFoldAsLoad = 1,
2822 isPseudo = 1, SchedRW = [WriteLoad], mayLoad = 1, hasSideEffects = 0 in {
2823 def VMOVAPSZ128rm_NOVLX : I<0, Pseudo, (outs VR128X:$dst), (ins f128mem:$src),
2825 def VMOVAPSZ256rm_NOVLX : I<0, Pseudo, (outs VR256X:$dst), (ins f256mem:$src),
2827 def VMOVUPSZ128rm_NOVLX : I<0, Pseudo, (outs VR128X:$dst), (ins f128mem:$src),
2829 def VMOVUPSZ256rm_NOVLX : I<0, Pseudo, (outs VR256X:$dst), (ins f256mem:$src),
2833 let isPseudo = 1, mayStore = 1, hasSideEffects = 0 in {
2834 def VMOVAPSZ128mr_NOVLX : I<0, Pseudo, (outs), (ins f128mem:$dst, VR128X:$src),
2836 def VMOVAPSZ256mr_NOVLX : I<0, Pseudo, (outs), (ins f256mem:$dst, VR256X:$src),
2838 def VMOVUPSZ128mr_NOVLX : I<0, Pseudo, (outs), (ins f128mem:$dst, VR128X:$src),
2840 def VMOVUPSZ256mr_NOVLX : I<0, Pseudo, (outs), (ins f256mem:$dst, VR256X:$src),
2844 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2845 (v8i64 VR512:$src))),
2846 (VMOVDQA64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2849 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2850 (v16i32 VR512:$src))),
2851 (VMOVDQA32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2853 // These patterns exist to prevent the above patterns from introducing a second
2854 // mask inversion when one already exists.
2855 def : Pat<(v8i64 (vselect (xor VK8:$mask, (v8i1 immAllOnesV)),
2856 (bc_v8i64 (v16i32 immAllZerosV)),
2857 (v8i64 VR512:$src))),
2858 (VMOVDQA64Zrrkz VK8:$mask, VR512:$src)>;
2859 def : Pat<(v16i32 (vselect (xor VK16:$mask, (v16i1 immAllOnesV)),
2860 (v16i32 immAllZerosV),
2861 (v16i32 VR512:$src))),
2862 (VMOVDQA32Zrrkz VK16WM:$mask, VR512:$src)>;
2864 // Patterns for handling v8i1 selects of 256-bit vectors when VLX isn't
2865 // available. Use a 512-bit operation and extract.
2866 let Predicates = [HasAVX512, NoVLX] in {
2867 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
2868 (v8f32 VR256X:$src0))),
2872 (v16f32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src0, sub_ymm)),
2873 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
2874 (v16f32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)))),
2877 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
2878 (v8i32 VR256X:$src0))),
2882 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src0, sub_ymm)),
2883 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
2884 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)))),
2888 let Predicates = [HasVLX, NoBWI] in {
2889 // 128-bit load/store without BWI.
2890 def : Pat<(alignedstore (v8i16 VR128X:$src), addr:$dst),
2891 (VMOVDQA32Z128mr addr:$dst, VR128X:$src)>;
2892 def : Pat<(alignedstore (v16i8 VR128X:$src), addr:$dst),
2893 (VMOVDQA32Z128mr addr:$dst, VR128X:$src)>;
2894 def : Pat<(store (v8i16 VR128X:$src), addr:$dst),
2895 (VMOVDQU32Z128mr addr:$dst, VR128X:$src)>;
2896 def : Pat<(store (v16i8 VR128X:$src), addr:$dst),
2897 (VMOVDQU32Z128mr addr:$dst, VR128X:$src)>;
2899 // 256-bit load/store without BWI.
2900 def : Pat<(alignedstore256 (v16i16 VR256X:$src), addr:$dst),
2901 (VMOVDQA32Z256mr addr:$dst, VR256X:$src)>;
2902 def : Pat<(alignedstore256 (v32i8 VR256X:$src), addr:$dst),
2903 (VMOVDQA32Z256mr addr:$dst, VR256X:$src)>;
2904 def : Pat<(store (v16i16 VR256X:$src), addr:$dst),
2905 (VMOVDQU32Z256mr addr:$dst, VR256X:$src)>;
2906 def : Pat<(store (v32i8 VR256X:$src), addr:$dst),
2907 (VMOVDQU32Z256mr addr:$dst, VR256X:$src)>;
2910 let Predicates = [HasVLX] in {
2911 // Special patterns for storing subvector extracts of lower 128-bits of 256.
2912 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
2913 def : Pat<(alignedstore (v2f64 (extract_subvector
2914 (v4f64 VR256X:$src), (iPTR 0))), addr:$dst),
2915 (VMOVAPDZ128mr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2916 def : Pat<(alignedstore (v4f32 (extract_subvector
2917 (v8f32 VR256X:$src), (iPTR 0))), addr:$dst),
2918 (VMOVAPSZ128mr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2919 def : Pat<(alignedstore (v2i64 (extract_subvector
2920 (v4i64 VR256X:$src), (iPTR 0))), addr:$dst),
2921 (VMOVDQA64Z128mr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2922 def : Pat<(alignedstore (v4i32 (extract_subvector
2923 (v8i32 VR256X:$src), (iPTR 0))), addr:$dst),
2924 (VMOVDQA32Z128mr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2925 def : Pat<(alignedstore (v8i16 (extract_subvector
2926 (v16i16 VR256X:$src), (iPTR 0))), addr:$dst),
2927 (VMOVDQA32Z128mr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2928 def : Pat<(alignedstore (v16i8 (extract_subvector
2929 (v32i8 VR256X:$src), (iPTR 0))), addr:$dst),
2930 (VMOVDQA32Z128mr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2932 def : Pat<(store (v2f64 (extract_subvector
2933 (v4f64 VR256X:$src), (iPTR 0))), addr:$dst),
2934 (VMOVUPDZ128mr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2935 def : Pat<(store (v4f32 (extract_subvector
2936 (v8f32 VR256X:$src), (iPTR 0))), addr:$dst),
2937 (VMOVUPSZ128mr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2938 def : Pat<(store (v2i64 (extract_subvector
2939 (v4i64 VR256X:$src), (iPTR 0))), addr:$dst),
2940 (VMOVDQU64Z128mr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2941 def : Pat<(store (v4i32 (extract_subvector
2942 (v8i32 VR256X:$src), (iPTR 0))), addr:$dst),
2943 (VMOVDQU32Z128mr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2944 def : Pat<(store (v8i16 (extract_subvector
2945 (v16i16 VR256X:$src), (iPTR 0))), addr:$dst),
2946 (VMOVDQU32Z128mr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2947 def : Pat<(store (v16i8 (extract_subvector
2948 (v32i8 VR256X:$src), (iPTR 0))), addr:$dst),
2949 (VMOVDQU32Z128mr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2951 // Special patterns for storing subvector extracts of lower 128-bits of 512.
2952 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
2953 def : Pat<(alignedstore (v2f64 (extract_subvector
2954 (v8f64 VR512:$src), (iPTR 0))), addr:$dst),
2955 (VMOVAPDZ128mr addr:$dst, (v2f64 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2956 def : Pat<(alignedstore (v4f32 (extract_subvector
2957 (v16f32 VR512:$src), (iPTR 0))), addr:$dst),
2958 (VMOVAPSZ128mr addr:$dst, (v4f32 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2959 def : Pat<(alignedstore (v2i64 (extract_subvector
2960 (v8i64 VR512:$src), (iPTR 0))), addr:$dst),
2961 (VMOVDQA64Z128mr addr:$dst, (v2i64 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2962 def : Pat<(alignedstore (v4i32 (extract_subvector
2963 (v16i32 VR512:$src), (iPTR 0))), addr:$dst),
2964 (VMOVDQA32Z128mr addr:$dst, (v4i32 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2965 def : Pat<(alignedstore (v8i16 (extract_subvector
2966 (v32i16 VR512:$src), (iPTR 0))), addr:$dst),
2967 (VMOVDQA32Z128mr addr:$dst, (v8i16 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2968 def : Pat<(alignedstore (v16i8 (extract_subvector
2969 (v64i8 VR512:$src), (iPTR 0))), addr:$dst),
2970 (VMOVDQA32Z128mr addr:$dst, (v16i8 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2972 def : Pat<(store (v2f64 (extract_subvector
2973 (v8f64 VR512:$src), (iPTR 0))), addr:$dst),
2974 (VMOVUPDZ128mr addr:$dst, (v2f64 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2975 def : Pat<(store (v4f32 (extract_subvector
2976 (v16f32 VR512:$src), (iPTR 0))), addr:$dst),
2977 (VMOVUPSZ128mr addr:$dst, (v4f32 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2978 def : Pat<(store (v2i64 (extract_subvector
2979 (v8i64 VR512:$src), (iPTR 0))), addr:$dst),
2980 (VMOVDQU64Z128mr addr:$dst, (v2i64 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2981 def : Pat<(store (v4i32 (extract_subvector
2982 (v16i32 VR512:$src), (iPTR 0))), addr:$dst),
2983 (VMOVDQU32Z128mr addr:$dst, (v4i32 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2984 def : Pat<(store (v8i16 (extract_subvector
2985 (v32i16 VR512:$src), (iPTR 0))), addr:$dst),
2986 (VMOVDQU32Z128mr addr:$dst, (v8i16 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2987 def : Pat<(store (v16i8 (extract_subvector
2988 (v64i8 VR512:$src), (iPTR 0))), addr:$dst),
2989 (VMOVDQU32Z128mr addr:$dst, (v16i8 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2991 // Special patterns for storing subvector extracts of lower 256-bits of 512.
2992 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
2993 def : Pat<(alignedstore256 (v4f64 (extract_subvector
2994 (v8f64 VR512:$src), (iPTR 0))), addr:$dst),
2995 (VMOVAPDZ256mr addr:$dst, (v4f64 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
2996 def : Pat<(alignedstore (v8f32 (extract_subvector
2997 (v16f32 VR512:$src), (iPTR 0))), addr:$dst),
2998 (VMOVAPSZ256mr addr:$dst, (v8f32 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
2999 def : Pat<(alignedstore256 (v4i64 (extract_subvector
3000 (v8i64 VR512:$src), (iPTR 0))), addr:$dst),
3001 (VMOVDQA64Z256mr addr:$dst, (v4i64 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
3002 def : Pat<(alignedstore256 (v8i32 (extract_subvector
3003 (v16i32 VR512:$src), (iPTR 0))), addr:$dst),
3004 (VMOVDQA32Z256mr addr:$dst, (v8i32 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
3005 def : Pat<(alignedstore256 (v16i16 (extract_subvector
3006 (v32i16 VR512:$src), (iPTR 0))), addr:$dst),
3007 (VMOVDQA32Z256mr addr:$dst, (v16i16 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
3008 def : Pat<(alignedstore256 (v32i8 (extract_subvector
3009 (v64i8 VR512:$src), (iPTR 0))), addr:$dst),
3010 (VMOVDQA32Z256mr addr:$dst, (v32i8 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
3012 def : Pat<(store (v4f64 (extract_subvector
3013 (v8f64 VR512:$src), (iPTR 0))), addr:$dst),
3014 (VMOVUPDZ256mr addr:$dst, (v4f64 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
3015 def : Pat<(store (v8f32 (extract_subvector
3016 (v16f32 VR512:$src), (iPTR 0))), addr:$dst),
3017 (VMOVUPSZ256mr addr:$dst, (v8f32 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
3018 def : Pat<(store (v4i64 (extract_subvector
3019 (v8i64 VR512:$src), (iPTR 0))), addr:$dst),
3020 (VMOVDQU64Z256mr addr:$dst, (v4i64 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
3021 def : Pat<(store (v8i32 (extract_subvector
3022 (v16i32 VR512:$src), (iPTR 0))), addr:$dst),
3023 (VMOVDQU32Z256mr addr:$dst, (v8i32 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
3024 def : Pat<(store (v16i16 (extract_subvector
3025 (v32i16 VR512:$src), (iPTR 0))), addr:$dst),
3026 (VMOVDQU32Z256mr addr:$dst, (v16i16 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
3027 def : Pat<(store (v32i8 (extract_subvector
3028 (v64i8 VR512:$src), (iPTR 0))), addr:$dst),
3029 (VMOVDQU32Z256mr addr:$dst, (v32i8 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
3033 // Move Int Doubleword to Packed Double Int
3035 let ExeDomain = SSEPackedInt in {
3036 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
3037 "vmovd\t{$src, $dst|$dst, $src}",
3039 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
3041 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
3042 "vmovd\t{$src, $dst|$dst, $src}",
3044 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
3045 IIC_SSE_MOVDQ>, EVEX, EVEX_CD8<32, CD8VT1>;
3046 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
3047 "vmovq\t{$src, $dst|$dst, $src}",
3049 (v2i64 (scalar_to_vector GR64:$src)))],
3050 IIC_SSE_MOVDQ>, EVEX, VEX_W;
3051 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
3052 def VMOV64toPQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
3054 "vmovq\t{$src, $dst|$dst, $src}", []>,
3055 EVEX, VEX_W, EVEX_CD8<64, CD8VT1>;
3056 let isCodeGenOnly = 1 in {
3057 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64X:$dst), (ins GR64:$src),
3058 "vmovq\t{$src, $dst|$dst, $src}",
3059 [(set FR64X:$dst, (bitconvert GR64:$src))],
3060 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
3061 def VMOV64toSDZrm : AVX512XSI<0x7E, MRMSrcMem, (outs FR64X:$dst), (ins i64mem:$src),
3062 "vmovq\t{$src, $dst|$dst, $src}",
3063 [(set FR64X:$dst, (bitconvert (loadi64 addr:$src)))]>,
3064 EVEX, VEX_W, EVEX_CD8<8, CD8VT8>;
3065 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64X:$src),
3066 "vmovq\t{$src, $dst|$dst, $src}",
3067 [(set GR64:$dst, (bitconvert FR64X:$src))],
3068 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
3069 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64X:$src),
3070 "vmovq\t{$src, $dst|$dst, $src}",
3071 [(store (i64 (bitconvert FR64X:$src)), addr:$dst)],
3072 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
3073 EVEX_CD8<64, CD8VT1>;
3075 } // ExeDomain = SSEPackedInt
3077 // Move Int Doubleword to Single Scalar
3079 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in {
3080 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
3081 "vmovd\t{$src, $dst|$dst, $src}",
3082 [(set FR32X:$dst, (bitconvert GR32:$src))],
3083 IIC_SSE_MOVDQ>, EVEX;
3085 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
3086 "vmovd\t{$src, $dst|$dst, $src}",
3087 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
3088 IIC_SSE_MOVDQ>, EVEX, EVEX_CD8<32, CD8VT1>;
3089 } // ExeDomain = SSEPackedInt, isCodeGenOnly = 1
3091 // Move doubleword from xmm register to r/m32
3093 let ExeDomain = SSEPackedInt in {
3094 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
3095 "vmovd\t{$src, $dst|$dst, $src}",
3096 [(set GR32:$dst, (extractelt (v4i32 VR128X:$src),
3097 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
3099 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
3100 (ins i32mem:$dst, VR128X:$src),
3101 "vmovd\t{$src, $dst|$dst, $src}",
3102 [(store (i32 (extractelt (v4i32 VR128X:$src),
3103 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
3104 EVEX, EVEX_CD8<32, CD8VT1>;
3105 } // ExeDomain = SSEPackedInt
3107 // Move quadword from xmm1 register to r/m64
3109 let ExeDomain = SSEPackedInt in {
3110 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
3111 "vmovq\t{$src, $dst|$dst, $src}",
3112 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
3114 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_W,
3115 Requires<[HasAVX512, In64BitMode]>;
3117 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
3118 def VMOVPQIto64Zmr : I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128X:$src),
3119 "vmovq\t{$src, $dst|$dst, $src}",
3120 [], IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_W,
3121 Requires<[HasAVX512, In64BitMode]>;
3123 def VMOVPQI2QIZmr : I<0xD6, MRMDestMem, (outs),
3124 (ins i64mem:$dst, VR128X:$src),
3125 "vmovq\t{$src, $dst|$dst, $src}",
3126 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
3127 addr:$dst)], IIC_SSE_MOVDQ>,
3128 EVEX, PD, VEX_W, EVEX_CD8<64, CD8VT1>,
3129 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
3131 let hasSideEffects = 0 in
3132 def VMOVPQI2QIZrr : AVX512BI<0xD6, MRMDestReg, (outs VR128X:$dst),
3134 "vmovq.s\t{$src, $dst|$dst, $src}",[]>,
3136 } // ExeDomain = SSEPackedInt
3138 // Move Scalar Single to Double Int
3140 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in {
3141 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
3143 "vmovd\t{$src, $dst|$dst, $src}",
3144 [(set GR32:$dst, (bitconvert FR32X:$src))],
3145 IIC_SSE_MOVD_ToGP>, EVEX;
3146 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
3147 (ins i32mem:$dst, FR32X:$src),
3148 "vmovd\t{$src, $dst|$dst, $src}",
3149 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
3150 IIC_SSE_MOVDQ>, EVEX, EVEX_CD8<32, CD8VT1>;
3151 } // ExeDomain = SSEPackedInt, isCodeGenOnly = 1
3153 // Move Quadword Int to Packed Quadword Int
3155 let ExeDomain = SSEPackedInt in {
3156 def VMOVQI2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
3158 "vmovq\t{$src, $dst|$dst, $src}",
3160 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
3161 EVEX, VEX_W, EVEX_CD8<8, CD8VT8>;
3162 } // ExeDomain = SSEPackedInt
3164 //===----------------------------------------------------------------------===//
3165 // AVX-512 MOVSS, MOVSD
3166 //===----------------------------------------------------------------------===//
3168 multiclass avx512_move_scalar<string asm, SDNode OpNode,
3169 X86VectorVTInfo _> {
3170 def rr : AVX512PI<0x10, MRMSrcReg, (outs _.RC:$dst),
3171 (ins _.RC:$src1, _.FRC:$src2),
3172 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3173 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1,
3174 (scalar_to_vector _.FRC:$src2))))],
3175 _.ExeDomain,IIC_SSE_MOV_S_RR>, EVEX_4V;
3176 def rrkz : AVX512PI<0x10, MRMSrcReg, (outs _.RC:$dst),
3177 (ins _.KRCWM:$mask, _.RC:$src1, _.FRC:$src2),
3178 !strconcat(asm, "\t{$src2, $src1, $dst {${mask}} {z}|",
3179 "$dst {${mask}} {z}, $src1, $src2}"),
3180 [(set _.RC:$dst, (_.VT (X86selects _.KRCWM:$mask,
3181 (_.VT (OpNode _.RC:$src1,
3182 (scalar_to_vector _.FRC:$src2))),
3184 _.ExeDomain,IIC_SSE_MOV_S_RR>, EVEX_4V, EVEX_KZ;
3185 let Constraints = "$src0 = $dst" in
3186 def rrk : AVX512PI<0x10, MRMSrcReg, (outs _.RC:$dst),
3187 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1, _.FRC:$src2),
3188 !strconcat(asm, "\t{$src2, $src1, $dst {${mask}}|",
3189 "$dst {${mask}}, $src1, $src2}"),
3190 [(set _.RC:$dst, (_.VT (X86selects _.KRCWM:$mask,
3191 (_.VT (OpNode _.RC:$src1,
3192 (scalar_to_vector _.FRC:$src2))),
3193 (_.VT _.RC:$src0))))],
3194 _.ExeDomain,IIC_SSE_MOV_S_RR>, EVEX_4V, EVEX_K;
3195 let canFoldAsLoad = 1, isReMaterializable = 1 in
3196 def rm : AVX512PI<0x10, MRMSrcMem, (outs _.FRC:$dst), (ins _.ScalarMemOp:$src),
3197 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
3198 [(set _.FRC:$dst, (_.ScalarLdFrag addr:$src))],
3199 _.ExeDomain, IIC_SSE_MOV_S_RM>, EVEX;
3200 let mayLoad = 1, hasSideEffects = 0 in {
3201 let Constraints = "$src0 = $dst" in
3202 def rmk : AVX512PI<0x10, MRMSrcMem, (outs _.RC:$dst),
3203 (ins _.RC:$src0, _.KRCWM:$mask, _.ScalarMemOp:$src),
3204 !strconcat(asm, "\t{$src, $dst {${mask}}|",
3205 "$dst {${mask}}, $src}"),
3206 [], _.ExeDomain, IIC_SSE_MOV_S_RM>, EVEX, EVEX_K;
3207 def rmkz : AVX512PI<0x10, MRMSrcMem, (outs _.RC:$dst),
3208 (ins _.KRCWM:$mask, _.ScalarMemOp:$src),
3209 !strconcat(asm, "\t{$src, $dst {${mask}} {z}|",
3210 "$dst {${mask}} {z}, $src}"),
3211 [], _.ExeDomain, IIC_SSE_MOV_S_RM>, EVEX, EVEX_KZ;
3213 def mr: AVX512PI<0x11, MRMDestMem, (outs), (ins _.ScalarMemOp:$dst, _.FRC:$src),
3214 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
3215 [(store _.FRC:$src, addr:$dst)], _.ExeDomain, IIC_SSE_MOV_S_MR>,
3217 let mayStore = 1, hasSideEffects = 0 in
3218 def mrk: AVX512PI<0x11, MRMDestMem, (outs),
3219 (ins _.ScalarMemOp:$dst, VK1WM:$mask, _.FRC:$src),
3220 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
3221 [], _.ExeDomain, IIC_SSE_MOV_S_MR>, EVEX, EVEX_K;
3224 defm VMOVSSZ : avx512_move_scalar<"vmovss", X86Movss, f32x_info>,
3225 VEX_LIG, XS, EVEX_CD8<32, CD8VT1>;
3227 defm VMOVSDZ : avx512_move_scalar<"vmovsd", X86Movsd, f64x_info>,
3228 VEX_LIG, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3231 multiclass avx512_move_scalar_lowering<string InstrStr, SDNode OpNode,
3232 PatLeaf ZeroFP, X86VectorVTInfo _> {
3234 def : Pat<(_.VT (OpNode _.RC:$src0,
3235 (_.VT (scalar_to_vector
3236 (_.EltVT (X86selects (scalar_to_vector (and (i8 (trunc GR32:$mask)), (i8 1))),
3237 (_.EltVT _.FRC:$src1),
3238 (_.EltVT _.FRC:$src2))))))),
3239 (COPY_TO_REGCLASS (!cast<Instruction>(InstrStr#rrk)
3240 (COPY_TO_REGCLASS _.FRC:$src2, _.RC),
3241 (COPY_TO_REGCLASS GR32:$mask, VK1WM),
3242 (_.VT _.RC:$src0), _.FRC:$src1),
3245 def : Pat<(_.VT (OpNode _.RC:$src0,
3246 (_.VT (scalar_to_vector
3247 (_.EltVT (X86selects (scalar_to_vector (and (i8 (trunc GR32:$mask)), (i8 1))),
3248 (_.EltVT _.FRC:$src1),
3249 (_.EltVT ZeroFP))))))),
3250 (COPY_TO_REGCLASS (!cast<Instruction>(InstrStr#rrkz)
3251 (COPY_TO_REGCLASS GR32:$mask, VK1WM),
3252 (_.VT _.RC:$src0), _.FRC:$src1),
3256 multiclass avx512_store_scalar_lowering<string InstrStr, AVX512VLVectorVTInfo _,
3257 dag Mask, RegisterClass MaskRC> {
3259 def : Pat<(masked_store addr:$dst, Mask,
3260 (_.info512.VT (insert_subvector undef,
3261 (_.info256.VT (insert_subvector undef,
3262 (_.info128.VT _.info128.RC:$src),
3265 (!cast<Instruction>(InstrStr#mrk) addr:$dst,
3266 (COPY_TO_REGCLASS MaskRC:$mask, VK1WM),
3267 (COPY_TO_REGCLASS _.info128.RC:$src, _.info128.FRC))>;
3271 multiclass avx512_store_scalar_lowering_subreg<string InstrStr,
3272 AVX512VLVectorVTInfo _,
3273 dag Mask, RegisterClass MaskRC,
3274 SubRegIndex subreg> {
3276 def : Pat<(masked_store addr:$dst, Mask,
3277 (_.info512.VT (insert_subvector undef,
3278 (_.info256.VT (insert_subvector undef,
3279 (_.info128.VT _.info128.RC:$src),
3282 (!cast<Instruction>(InstrStr#mrk) addr:$dst,
3283 (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
3284 (COPY_TO_REGCLASS _.info128.RC:$src, _.info128.FRC))>;
3288 multiclass avx512_load_scalar_lowering<string InstrStr, AVX512VLVectorVTInfo _,
3289 dag Mask, RegisterClass MaskRC> {
3291 def : Pat<(_.info128.VT (extract_subvector
3292 (_.info512.VT (masked_load addr:$srcAddr, Mask,
3293 (_.info512.VT (bitconvert
3294 (v16i32 immAllZerosV))))),
3296 (!cast<Instruction>(InstrStr#rmkz)
3297 (COPY_TO_REGCLASS MaskRC:$mask, VK1WM),
3300 def : Pat<(_.info128.VT (extract_subvector
3301 (_.info512.VT (masked_load addr:$srcAddr, Mask,
3302 (_.info512.VT (insert_subvector undef,
3303 (_.info256.VT (insert_subvector undef,
3304 (_.info128.VT (X86vzmovl _.info128.RC:$src)),
3308 (!cast<Instruction>(InstrStr#rmk) _.info128.RC:$src,
3309 (COPY_TO_REGCLASS MaskRC:$mask, VK1WM),
3314 multiclass avx512_load_scalar_lowering_subreg<string InstrStr,
3315 AVX512VLVectorVTInfo _,
3316 dag Mask, RegisterClass MaskRC,
3317 SubRegIndex subreg> {
3319 def : Pat<(_.info128.VT (extract_subvector
3320 (_.info512.VT (masked_load addr:$srcAddr, Mask,
3321 (_.info512.VT (bitconvert
3322 (v16i32 immAllZerosV))))),
3324 (!cast<Instruction>(InstrStr#rmkz)
3325 (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
3328 def : Pat<(_.info128.VT (extract_subvector
3329 (_.info512.VT (masked_load addr:$srcAddr, Mask,
3330 (_.info512.VT (insert_subvector undef,
3331 (_.info256.VT (insert_subvector undef,
3332 (_.info128.VT (X86vzmovl _.info128.RC:$src)),
3336 (!cast<Instruction>(InstrStr#rmk) _.info128.RC:$src,
3337 (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
3342 defm : avx512_move_scalar_lowering<"VMOVSSZ", X86Movss, fp32imm0, v4f32x_info>;
3343 defm : avx512_move_scalar_lowering<"VMOVSDZ", X86Movsd, fp64imm0, v2f64x_info>;
3345 defm : avx512_store_scalar_lowering<"VMOVSSZ", avx512vl_f32_info,
3346 (v16i1 (bitconvert (i16 (trunc (and GR32:$mask, (i32 1)))))), GR32>;
3347 defm : avx512_store_scalar_lowering_subreg<"VMOVSSZ", avx512vl_f32_info,
3348 (v16i1 (bitconvert (i16 (and GR16:$mask, (i16 1))))), GR16, sub_16bit>;
3349 defm : avx512_store_scalar_lowering_subreg<"VMOVSDZ", avx512vl_f64_info,
3350 (v8i1 (bitconvert (i8 (and GR8:$mask, (i8 1))))), GR8, sub_8bit>;
3352 defm : avx512_load_scalar_lowering<"VMOVSSZ", avx512vl_f32_info,
3353 (v16i1 (bitconvert (i16 (trunc (and GR32:$mask, (i32 1)))))), GR32>;
3354 defm : avx512_load_scalar_lowering_subreg<"VMOVSSZ", avx512vl_f32_info,
3355 (v16i1 (bitconvert (i16 (and GR16:$mask, (i16 1))))), GR16, sub_16bit>;
3356 defm : avx512_load_scalar_lowering_subreg<"VMOVSDZ", avx512vl_f64_info,
3357 (v8i1 (bitconvert (i8 (and GR8:$mask, (i8 1))))), GR8, sub_8bit>;
3359 def : Pat<(f32 (X86selects VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
3360 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
3361 VK1WM:$mask, (v4f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
3363 def : Pat<(f64 (X86selects VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
3364 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
3365 VK1WM:$mask, (v2f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
3367 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
3368 (VMOVSSZmrk addr:$dst, (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), GR8:$mask, sub_8bit)), VK1WM),
3369 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3371 let hasSideEffects = 0 in {
3372 def VMOVSSZrr_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
3373 (ins VR128X:$src1, FR32X:$src2),
3374 "vmovss.s\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3375 [], NoItinerary>, XS, EVEX_4V, VEX_LIG,
3376 FoldGenData<"VMOVSSZrr">;
3378 let Constraints = "$src0 = $dst" in
3379 def VMOVSSZrrk_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
3380 (ins f32x_info.RC:$src0, f32x_info.KRCWM:$mask,
3381 VR128X:$src1, FR32X:$src2),
3382 "vmovss.s\t{$src2, $src1, $dst {${mask}}|"#
3383 "$dst {${mask}}, $src1, $src2}",
3384 [], NoItinerary>, EVEX_K, XS, EVEX_4V, VEX_LIG,
3385 FoldGenData<"VMOVSSZrrk">;
3387 def VMOVSSZrrkz_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
3388 (ins f32x_info.KRCWM:$mask, VR128X:$src1, FR32X:$src2),
3389 "vmovss.s\t{$src2, $src1, $dst {${mask}} {z}|"#
3390 "$dst {${mask}} {z}, $src1, $src2}",
3391 [], NoItinerary>, EVEX_KZ, XS, EVEX_4V, VEX_LIG,
3392 FoldGenData<"VMOVSSZrrkz">;
3394 def VMOVSDZrr_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
3395 (ins VR128X:$src1, FR64X:$src2),
3396 "vmovsd.s\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3397 [], NoItinerary>, XD, EVEX_4V, VEX_LIG, VEX_W,
3398 FoldGenData<"VMOVSDZrr">;
3400 let Constraints = "$src0 = $dst" in
3401 def VMOVSDZrrk_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
3402 (ins f64x_info.RC:$src0, f64x_info.KRCWM:$mask,
3403 VR128X:$src1, FR64X:$src2),
3404 "vmovsd.s\t{$src2, $src1, $dst {${mask}}|"#
3405 "$dst {${mask}}, $src1, $src2}",
3406 [], NoItinerary>, EVEX_K, XD, EVEX_4V, VEX_LIG,
3407 VEX_W, FoldGenData<"VMOVSDZrrk">;
3409 def VMOVSDZrrkz_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
3410 (ins f64x_info.KRCWM:$mask, VR128X:$src1,
3412 "vmovsd.s\t{$src2, $src1, $dst {${mask}} {z}|"#
3413 "$dst {${mask}} {z}, $src1, $src2}",
3414 [], NoItinerary>, EVEX_KZ, XD, EVEX_4V, VEX_LIG,
3415 VEX_W, FoldGenData<"VMOVSDZrrkz">;
3418 let Predicates = [HasAVX512] in {
3419 let AddedComplexity = 15 in {
3420 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
3421 // MOVS{S,D} to the lower bits.
3422 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
3423 (VMOVSSZrr (v4f32 (AVX512_128_SET0)), FR32X:$src)>;
3424 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
3425 (VMOVSSZrr (v4f32 (AVX512_128_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3426 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
3427 (VMOVSSZrr (v4i32 (AVX512_128_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3428 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
3429 (VMOVSDZrr (v2f64 (AVX512_128_SET0)), FR64X:$src)>;
3432 // Move low f32 and clear high bits.
3433 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
3434 (SUBREG_TO_REG (i32 0),
3435 (VMOVSSZrr (v4f32 (AVX512_128_SET0)),
3436 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
3437 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
3438 (SUBREG_TO_REG (i32 0),
3439 (VMOVSSZrr (v4i32 (AVX512_128_SET0)),
3440 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
3441 def : Pat<(v16f32 (X86vzmovl (v16f32 VR512:$src))),
3442 (SUBREG_TO_REG (i32 0),
3443 (VMOVSSZrr (v4f32 (AVX512_128_SET0)),
3444 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm)), sub_xmm)>;
3445 def : Pat<(v16i32 (X86vzmovl (v16i32 VR512:$src))),
3446 (SUBREG_TO_REG (i32 0),
3447 (VMOVSSZrr (v4i32 (AVX512_128_SET0)),
3448 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm)), sub_xmm)>;
3450 let AddedComplexity = 20 in {
3451 // MOVSSrm zeros the high parts of the register; represent this
3452 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
3453 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
3454 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3455 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
3456 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3457 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
3458 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3459 def : Pat<(v4f32 (X86vzload addr:$src)),
3460 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3462 // MOVSDrm zeros the high parts of the register; represent this
3463 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
3464 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
3465 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3466 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
3467 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3468 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
3469 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3470 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
3471 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3472 def : Pat<(v2f64 (X86vzload addr:$src)),
3473 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3475 // Represent the same patterns above but in the form they appear for
3477 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3478 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
3479 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
3480 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
3481 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
3482 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
3483 def : Pat<(v8f32 (X86vzload addr:$src)),
3484 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
3485 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
3486 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
3487 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
3488 def : Pat<(v4f64 (X86vzload addr:$src)),
3489 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
3491 // Represent the same patterns above but in the form they appear for
3493 def : Pat<(v16i32 (X86vzmovl (insert_subvector undef,
3494 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
3495 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
3496 def : Pat<(v16f32 (X86vzmovl (insert_subvector undef,
3497 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
3498 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
3499 def : Pat<(v16f32 (X86vzload addr:$src)),
3500 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
3501 def : Pat<(v8f64 (X86vzmovl (insert_subvector undef,
3502 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
3503 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
3504 def : Pat<(v8f64 (X86vzload addr:$src)),
3505 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
3507 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
3508 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
3509 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (AVX512_128_SET0)),
3510 FR32X:$src)), sub_xmm)>;
3511 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
3512 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
3513 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (AVX512_128_SET0)),
3514 FR64X:$src)), sub_xmm)>;
3515 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3516 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
3517 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
3519 // Move low f64 and clear high bits.
3520 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
3521 (SUBREG_TO_REG (i32 0),
3522 (VMOVSDZrr (v2f64 (AVX512_128_SET0)),
3523 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
3524 def : Pat<(v8f64 (X86vzmovl (v8f64 VR512:$src))),
3525 (SUBREG_TO_REG (i32 0),
3526 (VMOVSDZrr (v2f64 (AVX512_128_SET0)),
3527 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm)), sub_xmm)>;
3529 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
3530 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (AVX512_128_SET0)),
3531 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
3532 def : Pat<(v8i64 (X86vzmovl (v8i64 VR512:$src))),
3533 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (AVX512_128_SET0)),
3534 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm)), sub_xmm)>;
3536 // Extract and store.
3537 def : Pat<(store (f32 (extractelt (v4f32 VR128X:$src), (iPTR 0))),
3539 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
3541 // Shuffle with VMOVSS
3542 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
3543 (VMOVSSZrr (v4i32 VR128X:$src1),
3544 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
3545 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
3546 (VMOVSSZrr (v4f32 VR128X:$src1),
3547 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
3550 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
3551 (SUBREG_TO_REG (i32 0),
3552 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
3553 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
3555 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
3556 (SUBREG_TO_REG (i32 0),
3557 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
3558 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
3561 // Shuffle with VMOVSD
3562 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3563 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3564 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3565 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3568 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3569 (SUBREG_TO_REG (i32 0),
3570 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
3571 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
3573 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3574 (SUBREG_TO_REG (i32 0),
3575 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
3576 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
3579 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3580 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3581 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3582 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3583 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3584 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3585 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3586 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3589 let AddedComplexity = 15 in
3590 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
3592 "vmovq\t{$src, $dst|$dst, $src}",
3593 [(set VR128X:$dst, (v2i64 (X86vzmovl
3594 (v2i64 VR128X:$src))))],
3595 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
3597 let Predicates = [HasAVX512] in {
3598 let AddedComplexity = 15 in {
3599 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
3600 (VMOVDI2PDIZrr GR32:$src)>;
3602 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
3603 (VMOV64toPQIZrr GR64:$src)>;
3605 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3606 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
3607 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
3609 def : Pat<(v8i64 (X86vzmovl (insert_subvector undef,
3610 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
3611 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
3613 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3614 let AddedComplexity = 20 in {
3615 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector (zextloadi64i32 addr:$src))))),
3616 (VMOVDI2PDIZrm addr:$src)>;
3617 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
3618 (VMOVDI2PDIZrm addr:$src)>;
3619 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3620 (VMOVDI2PDIZrm addr:$src)>;
3621 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3622 (VMOVDI2PDIZrm addr:$src)>;
3623 def : Pat<(v4i32 (X86vzload addr:$src)),
3624 (VMOVDI2PDIZrm addr:$src)>;
3625 def : Pat<(v8i32 (X86vzload addr:$src)),
3626 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
3627 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3628 (VMOVQI2PQIZrm addr:$src)>;
3629 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
3630 (VMOVZPQILo2PQIZrr VR128X:$src)>;
3631 def : Pat<(v2i64 (X86vzload addr:$src)),
3632 (VMOVQI2PQIZrm addr:$src)>;
3633 def : Pat<(v4i64 (X86vzload addr:$src)),
3634 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
3637 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3638 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3639 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
3640 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
3641 def : Pat<(v16i32 (X86vzmovl (insert_subvector undef,
3642 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
3643 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
3645 // Use regular 128-bit instructions to match 512-bit scalar_to_vec+zext.
3646 def : Pat<(v16i32 (X86vzload addr:$src)),
3647 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
3648 def : Pat<(v8i64 (X86vzload addr:$src)),
3649 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
3651 //===----------------------------------------------------------------------===//
3652 // AVX-512 - Non-temporals
3653 //===----------------------------------------------------------------------===//
3654 let SchedRW = [WriteLoad] in {
3655 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
3656 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
3657 [], SSEPackedInt>, EVEX, T8PD, EVEX_V512,
3658 EVEX_CD8<64, CD8VF>;
3660 let Predicates = [HasVLX] in {
3661 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
3663 "vmovntdqa\t{$src, $dst|$dst, $src}",
3664 [], SSEPackedInt>, EVEX, T8PD, EVEX_V256,
3665 EVEX_CD8<64, CD8VF>;
3667 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
3669 "vmovntdqa\t{$src, $dst|$dst, $src}",
3670 [], SSEPackedInt>, EVEX, T8PD, EVEX_V128,
3671 EVEX_CD8<64, CD8VF>;
3675 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3676 PatFrag st_frag = alignednontemporalstore,
3677 InstrItinClass itin = IIC_SSE_MOVNT> {
3678 let SchedRW = [WriteStore], AddedComplexity = 400 in
3679 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
3680 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3681 [(st_frag (_.VT _.RC:$src), addr:$dst)],
3682 _.ExeDomain, itin>, EVEX, EVEX_CD8<_.EltSize, CD8VF>;
3685 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr,
3686 AVX512VLVectorVTInfo VTInfo> {
3687 let Predicates = [HasAVX512] in
3688 defm Z : avx512_movnt<opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
3690 let Predicates = [HasAVX512, HasVLX] in {
3691 defm Z256 : avx512_movnt<opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
3692 defm Z128 : avx512_movnt<opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
3696 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", avx512vl_i64_info>, PD;
3697 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", avx512vl_f64_info>, PD, VEX_W;
3698 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", avx512vl_f32_info>, PS;
3700 let Predicates = [HasAVX512], AddedComplexity = 400 in {
3701 def : Pat<(alignednontemporalstore (v16i32 VR512:$src), addr:$dst),
3702 (VMOVNTDQZmr addr:$dst, VR512:$src)>;
3703 def : Pat<(alignednontemporalstore (v32i16 VR512:$src), addr:$dst),
3704 (VMOVNTDQZmr addr:$dst, VR512:$src)>;
3705 def : Pat<(alignednontemporalstore (v64i8 VR512:$src), addr:$dst),
3706 (VMOVNTDQZmr addr:$dst, VR512:$src)>;
3708 def : Pat<(v8f64 (alignednontemporalload addr:$src)),
3709 (VMOVNTDQAZrm addr:$src)>;
3710 def : Pat<(v16f32 (alignednontemporalload addr:$src)),
3711 (VMOVNTDQAZrm addr:$src)>;
3712 def : Pat<(v8i64 (alignednontemporalload addr:$src)),
3713 (VMOVNTDQAZrm addr:$src)>;
3714 def : Pat<(v16i32 (bitconvert (v8i64 (alignednontemporalload addr:$src)))),
3715 (VMOVNTDQAZrm addr:$src)>;
3716 def : Pat<(v32i16 (bitconvert (v8i64 (alignednontemporalload addr:$src)))),
3717 (VMOVNTDQAZrm addr:$src)>;
3718 def : Pat<(v64i8 (bitconvert (v8i64 (alignednontemporalload addr:$src)))),
3719 (VMOVNTDQAZrm addr:$src)>;
3722 let Predicates = [HasVLX], AddedComplexity = 400 in {
3723 def : Pat<(alignednontemporalstore (v8i32 VR256X:$src), addr:$dst),
3724 (VMOVNTDQZ256mr addr:$dst, VR256X:$src)>;
3725 def : Pat<(alignednontemporalstore (v16i16 VR256X:$src), addr:$dst),
3726 (VMOVNTDQZ256mr addr:$dst, VR256X:$src)>;
3727 def : Pat<(alignednontemporalstore (v32i8 VR256X:$src), addr:$dst),
3728 (VMOVNTDQZ256mr addr:$dst, VR256X:$src)>;
3730 def : Pat<(v4f64 (alignednontemporalload addr:$src)),
3731 (VMOVNTDQAZ256rm addr:$src)>;
3732 def : Pat<(v8f32 (alignednontemporalload addr:$src)),
3733 (VMOVNTDQAZ256rm addr:$src)>;
3734 def : Pat<(v4i64 (alignednontemporalload addr:$src)),
3735 (VMOVNTDQAZ256rm addr:$src)>;
3736 def : Pat<(v8i32 (bitconvert (v2i64 (alignednontemporalload addr:$src)))),
3737 (VMOVNTDQAZ256rm addr:$src)>;
3738 def : Pat<(v16i16 (bitconvert (v2i64 (alignednontemporalload addr:$src)))),
3739 (VMOVNTDQAZ256rm addr:$src)>;
3740 def : Pat<(v32i8 (bitconvert (v2i64 (alignednontemporalload addr:$src)))),
3741 (VMOVNTDQAZ256rm addr:$src)>;
3743 def : Pat<(alignednontemporalstore (v4i32 VR128X:$src), addr:$dst),
3744 (VMOVNTDQZ128mr addr:$dst, VR128X:$src)>;
3745 def : Pat<(alignednontemporalstore (v8i16 VR128X:$src), addr:$dst),
3746 (VMOVNTDQZ128mr addr:$dst, VR128X:$src)>;
3747 def : Pat<(alignednontemporalstore (v16i8 VR128X:$src), addr:$dst),
3748 (VMOVNTDQZ128mr addr:$dst, VR128X:$src)>;
3750 def : Pat<(v2f64 (alignednontemporalload addr:$src)),
3751 (VMOVNTDQAZ128rm addr:$src)>;
3752 def : Pat<(v4f32 (alignednontemporalload addr:$src)),
3753 (VMOVNTDQAZ128rm addr:$src)>;
3754 def : Pat<(v2i64 (alignednontemporalload addr:$src)),
3755 (VMOVNTDQAZ128rm addr:$src)>;
3756 def : Pat<(v4i32 (bitconvert (v2i64 (alignednontemporalload addr:$src)))),
3757 (VMOVNTDQAZ128rm addr:$src)>;
3758 def : Pat<(v8i16 (bitconvert (v2i64 (alignednontemporalload addr:$src)))),
3759 (VMOVNTDQAZ128rm addr:$src)>;
3760 def : Pat<(v16i8 (bitconvert (v2i64 (alignednontemporalload addr:$src)))),
3761 (VMOVNTDQAZ128rm addr:$src)>;
3764 //===----------------------------------------------------------------------===//
3765 // AVX-512 - Integer arithmetic
3767 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3768 X86VectorVTInfo _, OpndItins itins,
3769 bit IsCommutable = 0> {
3770 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3771 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3772 "$src2, $src1", "$src1, $src2",
3773 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3774 itins.rr, IsCommutable>,
3775 AVX512BIBase, EVEX_4V;
3777 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3778 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3779 "$src2, $src1", "$src1, $src2",
3780 (_.VT (OpNode _.RC:$src1,
3781 (bitconvert (_.LdFrag addr:$src2)))),
3783 AVX512BIBase, EVEX_4V;
3786 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3787 X86VectorVTInfo _, OpndItins itins,
3788 bit IsCommutable = 0> :
3789 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
3790 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3791 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3792 "${src2}"##_.BroadcastStr##", $src1",
3793 "$src1, ${src2}"##_.BroadcastStr,
3794 (_.VT (OpNode _.RC:$src1,
3796 (_.ScalarLdFrag addr:$src2)))),
3798 AVX512BIBase, EVEX_4V, EVEX_B;
3801 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3802 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3803 Predicate prd, bit IsCommutable = 0> {
3804 let Predicates = [prd] in
3805 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3806 IsCommutable>, EVEX_V512;
3808 let Predicates = [prd, HasVLX] in {
3809 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3810 IsCommutable>, EVEX_V256;
3811 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3812 IsCommutable>, EVEX_V128;
3816 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3817 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3818 Predicate prd, bit IsCommutable = 0> {
3819 let Predicates = [prd] in
3820 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3821 IsCommutable>, EVEX_V512;
3823 let Predicates = [prd, HasVLX] in {
3824 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3825 IsCommutable>, EVEX_V256;
3826 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3827 IsCommutable>, EVEX_V128;
3831 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3832 OpndItins itins, Predicate prd,
3833 bit IsCommutable = 0> {
3834 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3835 itins, prd, IsCommutable>,
3836 VEX_W, EVEX_CD8<64, CD8VF>;
3839 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3840 OpndItins itins, Predicate prd,
3841 bit IsCommutable = 0> {
3842 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3843 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3846 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3847 OpndItins itins, Predicate prd,
3848 bit IsCommutable = 0> {
3849 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3850 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3853 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3854 OpndItins itins, Predicate prd,
3855 bit IsCommutable = 0> {
3856 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3857 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3860 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3861 SDNode OpNode, OpndItins itins, Predicate prd,
3862 bit IsCommutable = 0> {
3863 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, itins, prd,
3866 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, itins, prd,
3870 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3871 SDNode OpNode, OpndItins itins, Predicate prd,
3872 bit IsCommutable = 0> {
3873 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr#"w", OpNode, itins, prd,
3876 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr#"b", OpNode, itins, prd,
3880 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3881 bits<8> opc_d, bits<8> opc_q,
3882 string OpcodeStr, SDNode OpNode,
3883 OpndItins itins, bit IsCommutable = 0> {
3884 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3885 itins, HasAVX512, IsCommutable>,
3886 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3887 itins, HasBWI, IsCommutable>;
3890 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3891 SDNode OpNode,X86VectorVTInfo _Src,
3892 X86VectorVTInfo _Dst, X86VectorVTInfo _Brdct,
3893 bit IsCommutable = 0> {
3894 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3895 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3896 "$src2, $src1","$src1, $src2",
3898 (_Src.VT _Src.RC:$src1),
3899 (_Src.VT _Src.RC:$src2))),
3900 itins.rr, IsCommutable>,
3901 AVX512BIBase, EVEX_4V;
3902 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3903 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3904 "$src2, $src1", "$src1, $src2",
3905 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3906 (bitconvert (_Src.LdFrag addr:$src2)))),
3908 AVX512BIBase, EVEX_4V;
3910 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3911 (ins _Src.RC:$src1, _Brdct.ScalarMemOp:$src2),
3913 "${src2}"##_Brdct.BroadcastStr##", $src1",
3914 "$src1, ${src2}"##_Brdct.BroadcastStr,
3915 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3916 (_Brdct.VT (X86VBroadcast
3917 (_Brdct.ScalarLdFrag addr:$src2)))))),
3919 AVX512BIBase, EVEX_4V, EVEX_B;
3922 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3923 SSE_INTALU_ITINS_P, 1>;
3924 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3925 SSE_INTALU_ITINS_P, 0>;
3926 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3927 SSE_INTALU_ITINS_P, HasBWI, 1>;
3928 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3929 SSE_INTALU_ITINS_P, HasBWI, 0>;
3930 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3931 SSE_INTALU_ITINS_P, HasBWI, 1>;
3932 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3933 SSE_INTALU_ITINS_P, HasBWI, 0>;
3934 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul,
3935 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3936 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul,
3937 SSE_INTALU_ITINS_P, HasBWI, 1>;
3938 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul,
3939 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3940 defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SSE_INTALU_ITINS_P,
3942 defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SSE_INTMUL_ITINS_P,
3944 defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, SSE_INTMUL_ITINS_P,
3946 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
3947 SSE_INTALU_ITINS_P, HasBWI, 1>;
3949 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3950 AVX512VLVectorVTInfo _SrcVTInfo, AVX512VLVectorVTInfo _DstVTInfo,
3951 SDNode OpNode, Predicate prd, bit IsCommutable = 0> {
3952 let Predicates = [prd] in
3953 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3954 _SrcVTInfo.info512, _DstVTInfo.info512,
3955 v8i64_info, IsCommutable>,
3956 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3957 let Predicates = [HasVLX, prd] in {
3958 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3959 _SrcVTInfo.info256, _DstVTInfo.info256,
3960 v4i64x_info, IsCommutable>,
3961 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3962 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3963 _SrcVTInfo.info128, _DstVTInfo.info128,
3964 v2i64x_info, IsCommutable>,
3965 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3969 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3970 avx512vl_i32_info, avx512vl_i64_info,
3971 X86pmuldq, HasAVX512, 1>,T8PD;
3972 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3973 avx512vl_i32_info, avx512vl_i64_info,
3974 X86pmuludq, HasAVX512, 1>;
3975 defm VPMULTISHIFTQB : avx512_binop_all<0x83, "vpmultishiftqb", SSE_INTALU_ITINS_P,
3976 avx512vl_i8_info, avx512vl_i8_info,
3977 X86multishift, HasVBMI, 0>, T8PD;
3979 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3980 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3981 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3982 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3984 "${src2}"##_Src.BroadcastStr##", $src1",
3985 "$src1, ${src2}"##_Src.BroadcastStr,
3986 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3987 (_Src.VT (X86VBroadcast
3988 (_Src.ScalarLdFrag addr:$src2))))))>,
3989 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3992 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3993 SDNode OpNode,X86VectorVTInfo _Src,
3994 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3995 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3996 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3997 "$src2, $src1","$src1, $src2",
3999 (_Src.VT _Src.RC:$src1),
4000 (_Src.VT _Src.RC:$src2))),
4001 NoItinerary, IsCommutable>,
4002 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
4003 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
4004 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
4005 "$src2, $src1", "$src1, $src2",
4006 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
4007 (bitconvert (_Src.LdFrag addr:$src2))))>,
4008 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
4011 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
4013 let Predicates = [HasBWI] in
4014 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
4016 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
4017 v32i16_info>, EVEX_V512;
4018 let Predicates = [HasBWI, HasVLX] in {
4019 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
4021 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
4022 v16i16x_info>, EVEX_V256;
4023 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
4025 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
4026 v8i16x_info>, EVEX_V128;
4029 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
4031 let Predicates = [HasBWI] in
4032 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
4033 v64i8_info>, EVEX_V512;
4034 let Predicates = [HasBWI, HasVLX] in {
4035 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
4036 v32i8x_info>, EVEX_V256;
4037 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
4038 v16i8x_info>, EVEX_V128;
4042 multiclass avx512_vpmadd<bits<8> opc, string OpcodeStr,
4043 SDNode OpNode, AVX512VLVectorVTInfo _Src,
4044 AVX512VLVectorVTInfo _Dst, bit IsCommutable = 0> {
4045 let Predicates = [HasBWI] in
4046 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info512,
4047 _Dst.info512, IsCommutable>, EVEX_V512;
4048 let Predicates = [HasBWI, HasVLX] in {
4049 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info256,
4050 _Dst.info256, IsCommutable>, EVEX_V256;
4051 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info128,
4052 _Dst.info128, IsCommutable>, EVEX_V128;
4056 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, AVX512BIBase;
4057 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, AVX5128IBase;
4058 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase;
4059 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase;
4061 defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw,
4062 avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD;
4063 defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd,
4064 avx512vl_i16_info, avx512vl_i32_info, 1>, AVX512BIBase;
4066 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax,
4067 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
4068 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax,
4069 SSE_INTALU_ITINS_P, HasBWI, 1>;
4070 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", smax,
4071 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
4073 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax,
4074 SSE_INTALU_ITINS_P, HasBWI, 1>;
4075 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax,
4076 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
4077 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", umax,
4078 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
4080 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin,
4081 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
4082 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin,
4083 SSE_INTALU_ITINS_P, HasBWI, 1>;
4084 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", smin,
4085 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
4087 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin,
4088 SSE_INTALU_ITINS_P, HasBWI, 1>;
4089 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
4090 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
4091 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
4092 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
4094 // PMULLQ: Use 512bit version to implement 128/256 bit in case NoVLX.
4095 let Predicates = [HasDQI, NoVLX] in {
4096 def : Pat<(v4i64 (mul (v4i64 VR256X:$src1), (v4i64 VR256X:$src2))),
4099 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src1, sub_ymm),
4100 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src2, sub_ymm)),
4103 def : Pat<(v2i64 (mul (v2i64 VR128X:$src1), (v2i64 VR128X:$src2))),
4106 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src1, sub_xmm),
4107 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src2, sub_xmm)),
4111 //===----------------------------------------------------------------------===//
4112 // AVX-512 Logical Instructions
4113 //===----------------------------------------------------------------------===//
4115 multiclass avx512_logic_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4116 X86VectorVTInfo _, bit IsCommutable = 0> {
4117 defm rr : AVX512_maskable_logic<opc, MRMSrcReg, _, (outs _.RC:$dst),
4118 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4119 "$src2, $src1", "$src1, $src2",
4120 (_.i64VT (OpNode (bitconvert (_.VT _.RC:$src1)),
4121 (bitconvert (_.VT _.RC:$src2)))),
4122 (_.VT (bitconvert (_.i64VT (OpNode _.RC:$src1,
4124 IIC_SSE_BIT_P_RR, IsCommutable>,
4125 AVX512BIBase, EVEX_4V;
4127 defm rm : AVX512_maskable_logic<opc, MRMSrcMem, _, (outs _.RC:$dst),
4128 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4129 "$src2, $src1", "$src1, $src2",
4130 (_.i64VT (OpNode (bitconvert (_.VT _.RC:$src1)),
4131 (bitconvert (_.LdFrag addr:$src2)))),
4132 (_.VT (bitconvert (_.i64VT (OpNode _.RC:$src1,
4133 (bitconvert (_.LdFrag addr:$src2)))))),
4135 AVX512BIBase, EVEX_4V;
4138 multiclass avx512_logic_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
4139 X86VectorVTInfo _, bit IsCommutable = 0> :
4140 avx512_logic_rm<opc, OpcodeStr, OpNode, _, IsCommutable> {
4141 defm rmb : AVX512_maskable_logic<opc, MRMSrcMem, _, (outs _.RC:$dst),
4142 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4143 "${src2}"##_.BroadcastStr##", $src1",
4144 "$src1, ${src2}"##_.BroadcastStr,
4145 (_.i64VT (OpNode _.RC:$src1,
4147 (_.VT (X86VBroadcast
4148 (_.ScalarLdFrag addr:$src2)))))),
4149 (_.VT (bitconvert (_.i64VT (OpNode _.RC:$src1,
4151 (_.VT (X86VBroadcast
4152 (_.ScalarLdFrag addr:$src2)))))))),
4154 AVX512BIBase, EVEX_4V, EVEX_B;
4157 multiclass avx512_logic_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
4158 AVX512VLVectorVTInfo VTInfo,
4159 bit IsCommutable = 0> {
4160 let Predicates = [HasAVX512] in
4161 defm Z : avx512_logic_rmb<opc, OpcodeStr, OpNode, VTInfo.info512,
4162 IsCommutable>, EVEX_V512;
4164 let Predicates = [HasAVX512, HasVLX] in {
4165 defm Z256 : avx512_logic_rmb<opc, OpcodeStr, OpNode, VTInfo.info256,
4166 IsCommutable>, EVEX_V256;
4167 defm Z128 : avx512_logic_rmb<opc, OpcodeStr, OpNode, VTInfo.info128,
4168 IsCommutable>, EVEX_V128;
4172 multiclass avx512_logic_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
4173 bit IsCommutable = 0> {
4174 defm NAME : avx512_logic_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
4175 IsCommutable>, EVEX_CD8<32, CD8VF>;
4178 multiclass avx512_logic_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
4179 bit IsCommutable = 0> {
4180 defm NAME : avx512_logic_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
4182 VEX_W, EVEX_CD8<64, CD8VF>;
4185 multiclass avx512_logic_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
4186 SDNode OpNode, bit IsCommutable = 0> {
4187 defm Q : avx512_logic_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, IsCommutable>;
4188 defm D : avx512_logic_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, IsCommutable>;
4191 defm VPAND : avx512_logic_rm_vl_dq<0xDB, 0xDB, "vpand", and, 1>;
4192 defm VPOR : avx512_logic_rm_vl_dq<0xEB, 0xEB, "vpor", or, 1>;
4193 defm VPXOR : avx512_logic_rm_vl_dq<0xEF, 0xEF, "vpxor", xor, 1>;
4194 defm VPANDN : avx512_logic_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp>;
4196 //===----------------------------------------------------------------------===//
4197 // AVX-512 FP arithmetic
4198 //===----------------------------------------------------------------------===//
4199 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4200 SDNode OpNode, SDNode VecNode, OpndItins itins,
4202 let ExeDomain = _.ExeDomain in {
4203 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4204 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4205 "$src2, $src1", "$src1, $src2",
4206 (_.VT (VecNode _.RC:$src1, _.RC:$src2,
4207 (i32 FROUND_CURRENT))),
4210 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4211 (ins _.RC:$src1, _.IntScalarMemOp:$src2), OpcodeStr,
4212 "$src2, $src1", "$src1, $src2",
4213 (_.VT (VecNode _.RC:$src1,
4214 _.ScalarIntMemCPat:$src2,
4215 (i32 FROUND_CURRENT))),
4217 let isCodeGenOnly = 1, Predicates = [HasAVX512] in {
4218 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
4219 (ins _.FRC:$src1, _.FRC:$src2),
4220 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4221 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
4223 let isCommutable = IsCommutable;
4225 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
4226 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
4227 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4228 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
4229 (_.ScalarLdFrag addr:$src2)))], itins.rm>;
4234 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4235 SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
4236 let ExeDomain = _.ExeDomain in
4237 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4238 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
4239 "$rc, $src2, $src1", "$src1, $src2, $rc",
4240 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4241 (i32 imm:$rc)), itins.rr, IsCommutable>,
4244 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4245 SDNode OpNode, SDNode VecNode, SDNode SaeNode,
4246 OpndItins itins, bit IsCommutable> {
4247 let ExeDomain = _.ExeDomain in {
4248 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4249 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4250 "$src2, $src1", "$src1, $src2",
4251 (_.VT (VecNode _.RC:$src1, _.RC:$src2)),
4254 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4255 (ins _.RC:$src1, _.IntScalarMemOp:$src2), OpcodeStr,
4256 "$src2, $src1", "$src1, $src2",
4257 (_.VT (VecNode _.RC:$src1,
4258 _.ScalarIntMemCPat:$src2)),
4261 let isCodeGenOnly = 1, Predicates = [HasAVX512] in {
4262 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
4263 (ins _.FRC:$src1, _.FRC:$src2),
4264 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4265 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
4267 let isCommutable = IsCommutable;
4269 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
4270 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
4271 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4272 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
4273 (_.ScalarLdFrag addr:$src2)))], itins.rm>;
4276 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4277 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4278 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
4279 (SaeNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4280 (i32 FROUND_NO_EXC))>, EVEX_B;
4284 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4286 SizeItins itins, bit IsCommutable> {
4287 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
4288 itins.s, IsCommutable>,
4289 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
4290 itins.s, IsCommutable>,
4291 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4292 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
4293 itins.d, IsCommutable>,
4294 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
4295 itins.d, IsCommutable>,
4296 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
4299 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
4300 SDNode VecNode, SDNode SaeNode,
4301 SizeItins itins, bit IsCommutable> {
4302 defm SSZ : avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, OpNode,
4303 VecNode, SaeNode, itins.s, IsCommutable>,
4304 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4305 defm SDZ : avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, OpNode,
4306 VecNode, SaeNode, itins.d, IsCommutable>,
4307 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
4309 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnds, SSE_ALU_ITINS_S, 1>;
4310 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnds, SSE_MUL_ITINS_S, 1>;
4311 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnds, SSE_ALU_ITINS_S, 0>;
4312 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnds, SSE_DIV_ITINS_S, 0>;
4313 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fmins, X86fminRnds,
4314 SSE_ALU_ITINS_S, 0>;
4315 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxs, X86fmaxRnds,
4316 SSE_ALU_ITINS_S, 0>;
4318 // MIN/MAX nodes are commutable under "unsafe-fp-math". In this case we use
4319 // X86fminc and X86fmaxc instead of X86fmin and X86fmax
4320 multiclass avx512_comutable_binop_s<bits<8> opc, string OpcodeStr,
4321 X86VectorVTInfo _, SDNode OpNode, OpndItins itins> {
4322 let isCodeGenOnly = 1, Predicates = [HasAVX512], ExeDomain = _.ExeDomain in {
4323 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
4324 (ins _.FRC:$src1, _.FRC:$src2),
4325 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4326 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
4328 let isCommutable = 1;
4330 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
4331 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
4332 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4333 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
4334 (_.ScalarLdFrag addr:$src2)))], itins.rm>;
4337 defm VMINCSSZ : avx512_comutable_binop_s<0x5D, "vminss", f32x_info, X86fminc,
4338 SSE_ALU_ITINS_S.s>, XS, EVEX_4V, VEX_LIG,
4339 EVEX_CD8<32, CD8VT1>;
4341 defm VMINCSDZ : avx512_comutable_binop_s<0x5D, "vminsd", f64x_info, X86fminc,
4342 SSE_ALU_ITINS_S.d>, XD, VEX_W, EVEX_4V, VEX_LIG,
4343 EVEX_CD8<64, CD8VT1>;
4345 defm VMAXCSSZ : avx512_comutable_binop_s<0x5F, "vmaxss", f32x_info, X86fmaxc,
4346 SSE_ALU_ITINS_S.s>, XS, EVEX_4V, VEX_LIG,
4347 EVEX_CD8<32, CD8VT1>;
4349 defm VMAXCSDZ : avx512_comutable_binop_s<0x5F, "vmaxsd", f64x_info, X86fmaxc,
4350 SSE_ALU_ITINS_S.d>, XD, VEX_W, EVEX_4V, VEX_LIG,
4351 EVEX_CD8<64, CD8VT1>;
4353 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
4354 X86VectorVTInfo _, OpndItins itins,
4356 let ExeDomain = _.ExeDomain, hasSideEffects = 0 in {
4357 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4358 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
4359 "$src2, $src1", "$src1, $src2",
4360 (_.VT (OpNode _.RC:$src1, _.RC:$src2)), itins.rr,
4361 IsCommutable>, EVEX_4V;
4362 let mayLoad = 1 in {
4363 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4364 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
4365 "$src2, $src1", "$src1, $src2",
4366 (OpNode _.RC:$src1, (_.LdFrag addr:$src2)), itins.rm>,
4368 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4369 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
4370 "${src2}"##_.BroadcastStr##", $src1",
4371 "$src1, ${src2}"##_.BroadcastStr,
4372 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4373 (_.ScalarLdFrag addr:$src2)))),
4374 itins.rm>, EVEX_4V, EVEX_B;
4379 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDPatternOperator OpNodeRnd,
4380 X86VectorVTInfo _> {
4381 let ExeDomain = _.ExeDomain in
4382 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4383 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
4384 "$rc, $src2, $src1", "$src1, $src2, $rc",
4385 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
4386 EVEX_4V, EVEX_B, EVEX_RC;
4390 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDPatternOperator OpNodeRnd,
4391 X86VectorVTInfo _> {
4392 let ExeDomain = _.ExeDomain in
4393 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4394 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
4395 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
4396 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
4400 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
4401 Predicate prd, SizeItins itins,
4402 bit IsCommutable = 0> {
4403 let Predicates = [prd] in {
4404 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
4405 itins.s, IsCommutable>, EVEX_V512, PS,
4406 EVEX_CD8<32, CD8VF>;
4407 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
4408 itins.d, IsCommutable>, EVEX_V512, PD, VEX_W,
4409 EVEX_CD8<64, CD8VF>;
4412 // Define only if AVX512VL feature is present.
4413 let Predicates = [prd, HasVLX] in {
4414 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
4415 itins.s, IsCommutable>, EVEX_V128, PS,
4416 EVEX_CD8<32, CD8VF>;
4417 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
4418 itins.s, IsCommutable>, EVEX_V256, PS,
4419 EVEX_CD8<32, CD8VF>;
4420 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
4421 itins.d, IsCommutable>, EVEX_V128, PD, VEX_W,
4422 EVEX_CD8<64, CD8VF>;
4423 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
4424 itins.d, IsCommutable>, EVEX_V256, PD, VEX_W,
4425 EVEX_CD8<64, CD8VF>;
4429 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
4430 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
4431 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4432 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
4433 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
4436 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
4437 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
4438 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4439 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
4440 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
4443 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, HasAVX512,
4444 SSE_ALU_ITINS_P, 1>,
4445 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
4446 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, HasAVX512,
4447 SSE_MUL_ITINS_P, 1>,
4448 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
4449 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub, HasAVX512, SSE_ALU_ITINS_P>,
4450 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
4451 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv, HasAVX512, SSE_DIV_ITINS_P>,
4452 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
4453 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, HasAVX512,
4454 SSE_ALU_ITINS_P, 0>,
4455 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
4456 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, HasAVX512,
4457 SSE_ALU_ITINS_P, 0>,
4458 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
4459 let isCodeGenOnly = 1 in {
4460 defm VMINC : avx512_fp_binop_p<0x5D, "vmin", X86fminc, HasAVX512,
4461 SSE_ALU_ITINS_P, 1>;
4462 defm VMAXC : avx512_fp_binop_p<0x5F, "vmax", X86fmaxc, HasAVX512,
4463 SSE_ALU_ITINS_P, 1>;
4465 defm VAND : avx512_fp_binop_p<0x54, "vand", null_frag, HasDQI,
4466 SSE_ALU_ITINS_P, 1>;
4467 defm VANDN : avx512_fp_binop_p<0x55, "vandn", null_frag, HasDQI,
4468 SSE_ALU_ITINS_P, 0>;
4469 defm VOR : avx512_fp_binop_p<0x56, "vor", null_frag, HasDQI,
4470 SSE_ALU_ITINS_P, 1>;
4471 defm VXOR : avx512_fp_binop_p<0x57, "vxor", null_frag, HasDQI,
4472 SSE_ALU_ITINS_P, 1>;
4474 // Patterns catch floating point selects with bitcasted integer logic ops.
4475 multiclass avx512_fp_logical_lowering<string InstrStr, SDNode OpNode,
4476 X86VectorVTInfo _, Predicate prd> {
4477 let Predicates = [prd] in {
4478 // Masked register-register logical operations.
4479 def : Pat<(_.VT (vselect _.KRCWM:$mask,
4480 (bitconvert (_.i64VT (OpNode _.RC:$src1, _.RC:$src2))),
4482 (!cast<Instruction>(InstrStr#rrk) _.RC:$src0, _.KRCWM:$mask,
4483 _.RC:$src1, _.RC:$src2)>;
4484 def : Pat<(_.VT (vselect _.KRCWM:$mask,
4485 (bitconvert (_.i64VT (OpNode _.RC:$src1, _.RC:$src2))),
4487 (!cast<Instruction>(InstrStr#rrkz) _.KRCWM:$mask, _.RC:$src1,
4489 // Masked register-memory logical operations.
4490 def : Pat<(_.VT (vselect _.KRCWM:$mask,
4491 (bitconvert (_.i64VT (OpNode _.RC:$src1,
4492 (load addr:$src2)))),
4494 (!cast<Instruction>(InstrStr#rmk) _.RC:$src0, _.KRCWM:$mask,
4495 _.RC:$src1, addr:$src2)>;
4496 def : Pat<(_.VT (vselect _.KRCWM:$mask,
4497 (bitconvert (_.i64VT (OpNode _.RC:$src1, (load addr:$src2)))),
4499 (!cast<Instruction>(InstrStr#rmkz) _.KRCWM:$mask, _.RC:$src1,
4501 // Register-broadcast logical operations.
4502 def : Pat<(_.i64VT (OpNode _.RC:$src1,
4503 (bitconvert (_.VT (X86VBroadcast
4504 (_.ScalarLdFrag addr:$src2)))))),
4505 (!cast<Instruction>(InstrStr#rmb) _.RC:$src1, addr:$src2)>;
4506 def : Pat<(_.VT (vselect _.KRCWM:$mask,
4508 (_.i64VT (OpNode _.RC:$src1,
4511 (_.ScalarLdFrag addr:$src2))))))),
4513 (!cast<Instruction>(InstrStr#rmbk) _.RC:$src0, _.KRCWM:$mask,
4514 _.RC:$src1, addr:$src2)>;
4515 def : Pat<(_.VT (vselect _.KRCWM:$mask,
4517 (_.i64VT (OpNode _.RC:$src1,
4520 (_.ScalarLdFrag addr:$src2))))))),
4522 (!cast<Instruction>(InstrStr#rmbkz) _.KRCWM:$mask,
4523 _.RC:$src1, addr:$src2)>;
4527 multiclass avx512_fp_logical_lowering_sizes<string InstrStr, SDNode OpNode> {
4528 defm : avx512_fp_logical_lowering<InstrStr#DZ128, OpNode, v4f32x_info, HasVLX>;
4529 defm : avx512_fp_logical_lowering<InstrStr#QZ128, OpNode, v2f64x_info, HasVLX>;
4530 defm : avx512_fp_logical_lowering<InstrStr#DZ256, OpNode, v8f32x_info, HasVLX>;
4531 defm : avx512_fp_logical_lowering<InstrStr#QZ256, OpNode, v4f64x_info, HasVLX>;
4532 defm : avx512_fp_logical_lowering<InstrStr#DZ, OpNode, v16f32_info, HasAVX512>;
4533 defm : avx512_fp_logical_lowering<InstrStr#QZ, OpNode, v8f64_info, HasAVX512>;
4536 defm : avx512_fp_logical_lowering_sizes<"VPAND", and>;
4537 defm : avx512_fp_logical_lowering_sizes<"VPOR", or>;
4538 defm : avx512_fp_logical_lowering_sizes<"VPXOR", xor>;
4539 defm : avx512_fp_logical_lowering_sizes<"VPANDN", X86andnp>;
4541 let Predicates = [HasVLX,HasDQI] in {
4542 // Use packed logical operations for scalar ops.
4543 def : Pat<(f64 (X86fand FR64X:$src1, FR64X:$src2)),
4544 (COPY_TO_REGCLASS (VANDPDZ128rr
4545 (COPY_TO_REGCLASS FR64X:$src1, VR128X),
4546 (COPY_TO_REGCLASS FR64X:$src2, VR128X)), FR64X)>;
4547 def : Pat<(f64 (X86for FR64X:$src1, FR64X:$src2)),
4548 (COPY_TO_REGCLASS (VORPDZ128rr
4549 (COPY_TO_REGCLASS FR64X:$src1, VR128X),
4550 (COPY_TO_REGCLASS FR64X:$src2, VR128X)), FR64X)>;
4551 def : Pat<(f64 (X86fxor FR64X:$src1, FR64X:$src2)),
4552 (COPY_TO_REGCLASS (VXORPDZ128rr
4553 (COPY_TO_REGCLASS FR64X:$src1, VR128X),
4554 (COPY_TO_REGCLASS FR64X:$src2, VR128X)), FR64X)>;
4555 def : Pat<(f64 (X86fandn FR64X:$src1, FR64X:$src2)),
4556 (COPY_TO_REGCLASS (VANDNPDZ128rr
4557 (COPY_TO_REGCLASS FR64X:$src1, VR128X),
4558 (COPY_TO_REGCLASS FR64X:$src2, VR128X)), FR64X)>;
4560 def : Pat<(f32 (X86fand FR32X:$src1, FR32X:$src2)),
4561 (COPY_TO_REGCLASS (VANDPSZ128rr
4562 (COPY_TO_REGCLASS FR32X:$src1, VR128X),
4563 (COPY_TO_REGCLASS FR32X:$src2, VR128X)), FR32X)>;
4564 def : Pat<(f32 (X86for FR32X:$src1, FR32X:$src2)),
4565 (COPY_TO_REGCLASS (VORPSZ128rr
4566 (COPY_TO_REGCLASS FR32X:$src1, VR128X),
4567 (COPY_TO_REGCLASS FR32X:$src2, VR128X)), FR32X)>;
4568 def : Pat<(f32 (X86fxor FR32X:$src1, FR32X:$src2)),
4569 (COPY_TO_REGCLASS (VXORPSZ128rr
4570 (COPY_TO_REGCLASS FR32X:$src1, VR128X),
4571 (COPY_TO_REGCLASS FR32X:$src2, VR128X)), FR32X)>;
4572 def : Pat<(f32 (X86fandn FR32X:$src1, FR32X:$src2)),
4573 (COPY_TO_REGCLASS (VANDNPSZ128rr
4574 (COPY_TO_REGCLASS FR32X:$src1, VR128X),
4575 (COPY_TO_REGCLASS FR32X:$src2, VR128X)), FR32X)>;
4578 multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4579 X86VectorVTInfo _> {
4580 let ExeDomain = _.ExeDomain in {
4581 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4582 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
4583 "$src2, $src1", "$src1, $src2",
4584 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>, EVEX_4V;
4585 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4586 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
4587 "$src2, $src1", "$src1, $src2",
4588 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>, EVEX_4V;
4589 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4590 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
4591 "${src2}"##_.BroadcastStr##", $src1",
4592 "$src1, ${src2}"##_.BroadcastStr,
4593 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4594 (_.ScalarLdFrag addr:$src2))), (i32 FROUND_CURRENT))>,
4599 multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
4600 X86VectorVTInfo _> {
4601 let ExeDomain = _.ExeDomain in {
4602 defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4603 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
4604 "$src2, $src1", "$src1, $src2",
4605 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
4606 defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4607 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
4608 "$src2, $src1", "$src1, $src2",
4610 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4611 (i32 FROUND_CURRENT))>;
4615 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode, SDNode OpNodeScal> {
4616 defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
4617 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
4618 EVEX_V512, EVEX_CD8<32, CD8VF>;
4619 defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
4620 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
4621 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4622 defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNodeScal, f32x_info>,
4623 avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNodeScal, SSE_ALU_ITINS_S.s>,
4624 EVEX_4V,EVEX_CD8<32, CD8VT1>;
4625 defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNodeScal, f64x_info>,
4626 avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNodeScal, SSE_ALU_ITINS_S.d>,
4627 EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
4629 // Define only if AVX512VL feature is present.
4630 let Predicates = [HasVLX] in {
4631 defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f32x_info>,
4632 EVEX_V128, EVEX_CD8<32, CD8VF>;
4633 defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f32x_info>,
4634 EVEX_V256, EVEX_CD8<32, CD8VF>;
4635 defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v2f64x_info>,
4636 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4637 defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f64x_info>,
4638 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4641 defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef, X86scalefs>, T8PD;
4643 //===----------------------------------------------------------------------===//
4644 // AVX-512 VPTESTM instructions
4645 //===----------------------------------------------------------------------===//
4647 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
4648 X86VectorVTInfo _> {
4649 let isCommutable = 1 in
4650 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
4651 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4652 "$src2, $src1", "$src1, $src2",
4653 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
4655 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
4656 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4657 "$src2, $src1", "$src1, $src2",
4658 (OpNode (_.VT _.RC:$src1),
4659 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
4661 EVEX_CD8<_.EltSize, CD8VF>;
4664 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
4665 X86VectorVTInfo _> {
4666 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
4667 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4668 "${src2}"##_.BroadcastStr##", $src1",
4669 "$src1, ${src2}"##_.BroadcastStr,
4670 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
4671 (_.ScalarLdFrag addr:$src2))))>,
4672 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4675 // Use 512bit version to implement 128/256 bit in case NoVLX.
4676 multiclass avx512_vptest_lowering<SDNode OpNode, X86VectorVTInfo ExtendInfo,
4677 X86VectorVTInfo _, string Suffix> {
4678 def : Pat<(_.KVT (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))),
4679 (_.KVT (COPY_TO_REGCLASS
4680 (!cast<Instruction>(NAME # Suffix # "Zrr")
4681 (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)),
4682 _.RC:$src1, _.SubRegIdx),
4683 (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)),
4684 _.RC:$src2, _.SubRegIdx)),
4688 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4689 AVX512VLVectorVTInfo _, string Suffix> {
4690 let Predicates = [HasAVX512] in
4691 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
4692 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4694 let Predicates = [HasAVX512, HasVLX] in {
4695 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
4696 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4697 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
4698 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
4700 let Predicates = [HasAVX512, NoVLX] in {
4701 defm Z256_Alt : avx512_vptest_lowering< OpNode, _.info512, _.info256, Suffix>;
4702 defm Z128_Alt : avx512_vptest_lowering< OpNode, _.info512, _.info128, Suffix>;
4706 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4707 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
4708 avx512vl_i32_info, "D">;
4709 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
4710 avx512vl_i64_info, "Q">, VEX_W;
4713 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
4715 let Predicates = [HasBWI] in {
4716 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
4718 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
4721 let Predicates = [HasVLX, HasBWI] in {
4723 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
4725 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
4727 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
4729 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
4733 let Predicates = [HasAVX512, NoVLX] in {
4734 defm BZ256_Alt : avx512_vptest_lowering< OpNode, v64i8_info, v32i8x_info, "B">;
4735 defm BZ128_Alt : avx512_vptest_lowering< OpNode, v64i8_info, v16i8x_info, "B">;
4736 defm WZ256_Alt : avx512_vptest_lowering< OpNode, v32i16_info, v16i16x_info, "W">;
4737 defm WZ128_Alt : avx512_vptest_lowering< OpNode, v32i16_info, v8i16x_info, "W">;
4742 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
4744 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
4745 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
4747 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
4748 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
4751 //===----------------------------------------------------------------------===//
4752 // AVX-512 Shift instructions
4753 //===----------------------------------------------------------------------===//
4754 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
4755 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
4756 let ExeDomain = _.ExeDomain in {
4757 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
4758 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
4759 "$src2, $src1", "$src1, $src2",
4760 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
4761 SSE_INTSHIFT_ITINS_P.rr>;
4762 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
4763 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
4764 "$src2, $src1", "$src1, $src2",
4765 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
4767 SSE_INTSHIFT_ITINS_P.rm>;
4771 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
4772 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
4773 let ExeDomain = _.ExeDomain in
4774 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
4775 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
4776 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
4777 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
4778 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
4781 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4782 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
4783 // src2 is always 128-bit
4784 let ExeDomain = _.ExeDomain in {
4785 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4786 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
4787 "$src2, $src1", "$src1, $src2",
4788 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
4789 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
4790 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4791 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
4792 "$src2, $src1", "$src1, $src2",
4793 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
4794 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
4799 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4800 ValueType SrcVT, PatFrag bc_frag,
4801 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
4802 let Predicates = [prd] in
4803 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4804 VTInfo.info512>, EVEX_V512,
4805 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
4806 let Predicates = [prd, HasVLX] in {
4807 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4808 VTInfo.info256>, EVEX_V256,
4809 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
4810 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4811 VTInfo.info128>, EVEX_V128,
4812 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
4816 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
4817 string OpcodeStr, SDNode OpNode> {
4818 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
4819 avx512vl_i32_info, HasAVX512>;
4820 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
4821 avx512vl_i64_info, HasAVX512>, VEX_W;
4822 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
4823 avx512vl_i16_info, HasBWI>;
4826 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4827 string OpcodeStr, SDNode OpNode,
4828 AVX512VLVectorVTInfo VTInfo> {
4829 let Predicates = [HasAVX512] in
4830 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4832 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4833 VTInfo.info512>, EVEX_V512;
4834 let Predicates = [HasAVX512, HasVLX] in {
4835 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4837 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4838 VTInfo.info256>, EVEX_V256;
4839 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4841 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4842 VTInfo.info128>, EVEX_V128;
4846 multiclass avx512_shift_rmi_w<bits<8> opcw,
4847 Format ImmFormR, Format ImmFormM,
4848 string OpcodeStr, SDNode OpNode> {
4849 let Predicates = [HasBWI] in
4850 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4851 v32i16_info>, EVEX_V512;
4852 let Predicates = [HasVLX, HasBWI] in {
4853 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4854 v16i16x_info>, EVEX_V256;
4855 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4856 v8i16x_info>, EVEX_V128;
4860 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
4861 Format ImmFormR, Format ImmFormM,
4862 string OpcodeStr, SDNode OpNode> {
4863 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
4864 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
4865 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
4866 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
4869 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
4870 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
4872 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
4873 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
4875 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
4876 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
4878 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", X86vrotri>, AVX512BIi8Base, EVEX_4V;
4879 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", X86vrotli>, AVX512BIi8Base, EVEX_4V;
4881 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
4882 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
4883 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
4885 // Use 512bit VPSRA/VPSRAI version to implement v2i64/v4i64 in case NoVLX.
4886 let Predicates = [HasAVX512, NoVLX] in {
4887 def : Pat<(v4i64 (X86vsra (v4i64 VR256X:$src1), (v2i64 VR128X:$src2))),
4888 (EXTRACT_SUBREG (v8i64
4890 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)),
4891 VR128X:$src2)), sub_ymm)>;
4893 def : Pat<(v2i64 (X86vsra (v2i64 VR128X:$src1), (v2i64 VR128X:$src2))),
4894 (EXTRACT_SUBREG (v8i64
4896 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)),
4897 VR128X:$src2)), sub_xmm)>;
4899 def : Pat<(v4i64 (X86vsrai (v4i64 VR256X:$src1), (i8 imm:$src2))),
4900 (EXTRACT_SUBREG (v8i64
4902 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)),
4903 imm:$src2)), sub_ymm)>;
4905 def : Pat<(v2i64 (X86vsrai (v2i64 VR128X:$src1), (i8 imm:$src2))),
4906 (EXTRACT_SUBREG (v8i64
4908 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)),
4909 imm:$src2)), sub_xmm)>;
4912 //===-------------------------------------------------------------------===//
4913 // Variable Bit Shifts
4914 //===-------------------------------------------------------------------===//
4915 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
4916 X86VectorVTInfo _> {
4917 let ExeDomain = _.ExeDomain in {
4918 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4919 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4920 "$src2, $src1", "$src1, $src2",
4921 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
4922 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
4923 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4924 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4925 "$src2, $src1", "$src1, $src2",
4926 (_.VT (OpNode _.RC:$src1,
4927 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
4928 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
4929 EVEX_CD8<_.EltSize, CD8VF>;
4933 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
4934 X86VectorVTInfo _> {
4935 let ExeDomain = _.ExeDomain in
4936 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4937 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4938 "${src2}"##_.BroadcastStr##", $src1",
4939 "$src1, ${src2}"##_.BroadcastStr,
4940 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4941 (_.ScalarLdFrag addr:$src2))))),
4942 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
4943 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4946 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4947 AVX512VLVectorVTInfo _> {
4948 let Predicates = [HasAVX512] in
4949 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4950 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4952 let Predicates = [HasAVX512, HasVLX] in {
4953 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4954 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4955 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
4956 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
4960 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
4962 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
4964 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
4965 avx512vl_i64_info>, VEX_W;
4968 // Use 512bit version to implement 128/256 bit in case NoVLX.
4969 multiclass avx512_var_shift_lowering<AVX512VLVectorVTInfo _, string OpcodeStr,
4970 SDNode OpNode, list<Predicate> p> {
4971 let Predicates = p in {
4972 def : Pat<(_.info256.VT (OpNode (_.info256.VT _.info256.RC:$src1),
4973 (_.info256.VT _.info256.RC:$src2))),
4975 (!cast<Instruction>(OpcodeStr#"Zrr")
4976 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR256X:$src1, sub_ymm),
4977 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR256X:$src2, sub_ymm)),
4980 def : Pat<(_.info128.VT (OpNode (_.info128.VT _.info128.RC:$src1),
4981 (_.info128.VT _.info128.RC:$src2))),
4983 (!cast<Instruction>(OpcodeStr#"Zrr")
4984 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR128X:$src1, sub_xmm),
4985 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR128X:$src2, sub_xmm)),
4989 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
4991 let Predicates = [HasBWI] in
4992 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
4994 let Predicates = [HasVLX, HasBWI] in {
4996 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
4998 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
5003 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
5004 avx512_var_shift_w<0x12, "vpsllvw", shl>;
5006 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
5007 avx512_var_shift_w<0x11, "vpsravw", sra>;
5009 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
5010 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
5012 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
5013 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
5015 defm : avx512_var_shift_lowering<avx512vl_i64_info, "VPSRAVQ", sra, [HasAVX512, NoVLX]>;
5016 defm : avx512_var_shift_lowering<avx512vl_i16_info, "VPSLLVW", shl, [HasBWI, NoVLX]>;
5017 defm : avx512_var_shift_lowering<avx512vl_i16_info, "VPSRAVW", sra, [HasBWI, NoVLX]>;
5018 defm : avx512_var_shift_lowering<avx512vl_i16_info, "VPSRLVW", srl, [HasBWI, NoVLX]>;
5020 // Special handing for handling VPSRAV intrinsics.
5021 multiclass avx512_var_shift_int_lowering<string InstrStr, X86VectorVTInfo _,
5022 list<Predicate> p> {
5023 let Predicates = p in {
5024 def : Pat<(_.VT (X86vsrav _.RC:$src1, _.RC:$src2)),
5025 (!cast<Instruction>(InstrStr#_.ZSuffix#rr) _.RC:$src1,
5027 def : Pat<(_.VT (X86vsrav _.RC:$src1, (bitconvert (_.LdFrag addr:$src2)))),
5028 (!cast<Instruction>(InstrStr#_.ZSuffix##rm)
5029 _.RC:$src1, addr:$src2)>;
5030 def : Pat<(_.VT (vselect _.KRCWM:$mask,
5031 (X86vsrav _.RC:$src1, _.RC:$src2), _.RC:$src0)),
5032 (!cast<Instruction>(InstrStr#_.ZSuffix#rrk) _.RC:$src0,
5033 _.KRC:$mask, _.RC:$src1, _.RC:$src2)>;
5034 def : Pat<(_.VT (vselect _.KRCWM:$mask,
5035 (X86vsrav _.RC:$src1, (bitconvert (_.LdFrag addr:$src2))),
5037 (!cast<Instruction>(InstrStr#_.ZSuffix##rmk) _.RC:$src0,
5038 _.KRC:$mask, _.RC:$src1, addr:$src2)>;
5039 def : Pat<(_.VT (vselect _.KRCWM:$mask,
5040 (X86vsrav _.RC:$src1, _.RC:$src2), _.ImmAllZerosV)),
5041 (!cast<Instruction>(InstrStr#_.ZSuffix#rrkz) _.KRC:$mask,
5042 _.RC:$src1, _.RC:$src2)>;
5043 def : Pat<(_.VT (vselect _.KRCWM:$mask,
5044 (X86vsrav _.RC:$src1, (bitconvert (_.LdFrag addr:$src2))),
5046 (!cast<Instruction>(InstrStr#_.ZSuffix##rmkz) _.KRC:$mask,
5047 _.RC:$src1, addr:$src2)>;
5051 multiclass avx512_var_shift_int_lowering_mb<string InstrStr, X86VectorVTInfo _,
5052 list<Predicate> p> :
5053 avx512_var_shift_int_lowering<InstrStr, _, p> {
5054 let Predicates = p in {
5055 def : Pat<(_.VT (X86vsrav _.RC:$src1,
5056 (X86VBroadcast (_.ScalarLdFrag addr:$src2)))),
5057 (!cast<Instruction>(InstrStr#_.ZSuffix##rmb)
5058 _.RC:$src1, addr:$src2)>;
5059 def : Pat<(_.VT (vselect _.KRCWM:$mask,
5060 (X86vsrav _.RC:$src1,
5061 (X86VBroadcast (_.ScalarLdFrag addr:$src2))),
5063 (!cast<Instruction>(InstrStr#_.ZSuffix##rmbk) _.RC:$src0,
5064 _.KRC:$mask, _.RC:$src1, addr:$src2)>;
5065 def : Pat<(_.VT (vselect _.KRCWM:$mask,
5066 (X86vsrav _.RC:$src1,
5067 (X86VBroadcast (_.ScalarLdFrag addr:$src2))),
5069 (!cast<Instruction>(InstrStr#_.ZSuffix##rmbkz) _.KRC:$mask,
5070 _.RC:$src1, addr:$src2)>;
5074 defm : avx512_var_shift_int_lowering<"VPSRAVW", v8i16x_info, [HasVLX, HasBWI]>;
5075 defm : avx512_var_shift_int_lowering<"VPSRAVW", v16i16x_info, [HasVLX, HasBWI]>;
5076 defm : avx512_var_shift_int_lowering<"VPSRAVW", v32i16_info, [HasBWI]>;
5077 defm : avx512_var_shift_int_lowering_mb<"VPSRAVD", v4i32x_info, [HasVLX]>;
5078 defm : avx512_var_shift_int_lowering_mb<"VPSRAVD", v8i32x_info, [HasVLX]>;
5079 defm : avx512_var_shift_int_lowering_mb<"VPSRAVD", v16i32_info, [HasAVX512]>;
5080 defm : avx512_var_shift_int_lowering_mb<"VPSRAVQ", v2i64x_info, [HasVLX]>;
5081 defm : avx512_var_shift_int_lowering_mb<"VPSRAVQ", v4i64x_info, [HasVLX]>;
5082 defm : avx512_var_shift_int_lowering_mb<"VPSRAVQ", v8i64_info, [HasAVX512]>;
5084 //===-------------------------------------------------------------------===//
5085 // 1-src variable permutation VPERMW/D/Q
5086 //===-------------------------------------------------------------------===//
5087 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
5088 AVX512VLVectorVTInfo _> {
5089 let Predicates = [HasAVX512] in
5090 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
5091 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
5093 let Predicates = [HasAVX512, HasVLX] in
5094 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
5095 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
5098 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
5099 string OpcodeStr, SDNode OpNode,
5100 AVX512VLVectorVTInfo VTInfo> {
5101 let Predicates = [HasAVX512] in
5102 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
5104 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
5105 VTInfo.info512>, EVEX_V512;
5106 let Predicates = [HasAVX512, HasVLX] in
5107 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
5109 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
5110 VTInfo.info256>, EVEX_V256;
5113 multiclass avx512_vperm_bw<bits<8> opc, string OpcodeStr,
5114 Predicate prd, SDNode OpNode,
5115 AVX512VLVectorVTInfo _> {
5116 let Predicates = [prd] in
5117 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
5119 let Predicates = [HasVLX, prd] in {
5120 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
5122 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
5127 defm VPERMW : avx512_vperm_bw<0x8D, "vpermw", HasBWI, X86VPermv,
5128 avx512vl_i16_info>, VEX_W;
5129 defm VPERMB : avx512_vperm_bw<0x8D, "vpermb", HasVBMI, X86VPermv,
5132 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
5134 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
5135 avx512vl_i64_info>, VEX_W;
5136 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
5138 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
5139 avx512vl_f64_info>, VEX_W;
5141 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
5142 X86VPermi, avx512vl_i64_info>,
5143 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
5144 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
5145 X86VPermi, avx512vl_f64_info>,
5146 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
5147 //===----------------------------------------------------------------------===//
5148 // AVX-512 - VPERMIL
5149 //===----------------------------------------------------------------------===//
5151 multiclass avx512_permil_vec<bits<8> OpcVar, string OpcodeStr, SDNode OpNode,
5152 X86VectorVTInfo _, X86VectorVTInfo Ctrl> {
5153 defm rr: AVX512_maskable<OpcVar, MRMSrcReg, _, (outs _.RC:$dst),
5154 (ins _.RC:$src1, Ctrl.RC:$src2), OpcodeStr,
5155 "$src2, $src1", "$src1, $src2",
5156 (_.VT (OpNode _.RC:$src1,
5157 (Ctrl.VT Ctrl.RC:$src2)))>,
5159 defm rm: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
5160 (ins _.RC:$src1, Ctrl.MemOp:$src2), OpcodeStr,
5161 "$src2, $src1", "$src1, $src2",
5164 (Ctrl.VT (bitconvert(Ctrl.LdFrag addr:$src2)))))>,
5165 T8PD, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
5166 defm rmb: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
5167 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
5168 "${src2}"##_.BroadcastStr##", $src1",
5169 "$src1, ${src2}"##_.BroadcastStr,
5172 (Ctrl.VT (X86VBroadcast
5173 (Ctrl.ScalarLdFrag addr:$src2)))))>,
5174 T8PD, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
5177 multiclass avx512_permil_vec_common<string OpcodeStr, bits<8> OpcVar,
5178 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
5179 let Predicates = [HasAVX512] in {
5180 defm Z : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info512,
5181 Ctrl.info512>, EVEX_V512;
5183 let Predicates = [HasAVX512, HasVLX] in {
5184 defm Z128 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info128,
5185 Ctrl.info128>, EVEX_V128;
5186 defm Z256 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info256,
5187 Ctrl.info256>, EVEX_V256;
5191 multiclass avx512_permil<string OpcodeStr, bits<8> OpcImm, bits<8> OpcVar,
5192 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
5194 defm NAME: avx512_permil_vec_common<OpcodeStr, OpcVar, _, Ctrl>;
5195 defm NAME: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem, OpcodeStr,
5197 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
5200 let ExeDomain = SSEPackedSingle in
5201 defm VPERMILPS : avx512_permil<"vpermilps", 0x04, 0x0C, avx512vl_f32_info,
5203 let ExeDomain = SSEPackedDouble in
5204 defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info,
5205 avx512vl_i64_info>, VEX_W;
5206 //===----------------------------------------------------------------------===//
5207 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
5208 //===----------------------------------------------------------------------===//
5210 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
5211 X86PShufd, avx512vl_i32_info>,
5212 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
5213 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
5214 X86PShufhw>, EVEX, AVX512XSIi8Base;
5215 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
5216 X86PShuflw>, EVEX, AVX512XDIi8Base;
5218 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5219 let Predicates = [HasBWI] in
5220 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, v64i8_info>, EVEX_V512;
5222 let Predicates = [HasVLX, HasBWI] in {
5223 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, v32i8x_info>, EVEX_V256;
5224 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, v16i8x_info>, EVEX_V128;
5228 defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>;
5230 //===----------------------------------------------------------------------===//
5231 // Move Low to High and High to Low packed FP Instructions
5232 //===----------------------------------------------------------------------===//
5233 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
5234 (ins VR128X:$src1, VR128X:$src2),
5235 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5236 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
5237 IIC_SSE_MOV_LH>, EVEX_4V;
5238 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
5239 (ins VR128X:$src1, VR128X:$src2),
5240 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5241 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
5242 IIC_SSE_MOV_LH>, EVEX_4V;
5244 let Predicates = [HasAVX512] in {
5246 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
5247 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
5248 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
5249 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
5252 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
5253 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
5256 //===----------------------------------------------------------------------===//
5257 // VMOVHPS/PD VMOVLPS Instructions
5258 // All patterns was taken from SSS implementation.
5259 //===----------------------------------------------------------------------===//
5260 multiclass avx512_mov_hilo_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
5261 X86VectorVTInfo _> {
5262 let ExeDomain = _.ExeDomain in
5263 def rm : AVX512<opc, MRMSrcMem, (outs _.RC:$dst),
5264 (ins _.RC:$src1, f64mem:$src2),
5265 !strconcat(OpcodeStr,
5266 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5270 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))))))],
5271 IIC_SSE_MOV_LH>, EVEX_4V;
5274 defm VMOVHPSZ128 : avx512_mov_hilo_packed<0x16, "vmovhps", X86Movlhps,
5275 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
5276 defm VMOVHPDZ128 : avx512_mov_hilo_packed<0x16, "vmovhpd", X86Movlhpd,
5277 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
5278 defm VMOVLPSZ128 : avx512_mov_hilo_packed<0x12, "vmovlps", X86Movlps,
5279 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
5280 defm VMOVLPDZ128 : avx512_mov_hilo_packed<0x12, "vmovlpd", X86Movlpd,
5281 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
5283 let Predicates = [HasAVX512] in {
5285 def : Pat<(X86Movlhps VR128X:$src1,
5286 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
5287 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
5288 def : Pat<(X86Movlhps VR128X:$src1,
5289 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
5290 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
5292 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
5293 (scalar_to_vector (loadf64 addr:$src2)))),
5294 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
5295 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
5296 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
5297 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
5299 def : Pat<(v4f32 (X86Movlps VR128X:$src1, (load addr:$src2))),
5300 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
5301 def : Pat<(v4i32 (X86Movlps VR128X:$src1, (load addr:$src2))),
5302 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
5304 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
5305 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
5306 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
5307 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
5308 def : Pat<(v2f64 (X86Movsd VR128X:$src1,
5309 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5310 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
5313 def VMOVHPSZ128mr : AVX512PSI<0x17, MRMDestMem, (outs),
5314 (ins f64mem:$dst, VR128X:$src),
5315 "vmovhps\t{$src, $dst|$dst, $src}",
5316 [(store (f64 (extractelt
5317 (X86Unpckh (bc_v2f64 (v4f32 VR128X:$src)),
5318 (bc_v2f64 (v4f32 VR128X:$src))),
5319 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
5320 EVEX, EVEX_CD8<32, CD8VT2>;
5321 def VMOVHPDZ128mr : AVX512PDI<0x17, MRMDestMem, (outs),
5322 (ins f64mem:$dst, VR128X:$src),
5323 "vmovhpd\t{$src, $dst|$dst, $src}",
5324 [(store (f64 (extractelt
5325 (v2f64 (X86Unpckh VR128X:$src, VR128X:$src)),
5326 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
5327 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
5328 def VMOVLPSZ128mr : AVX512PSI<0x13, MRMDestMem, (outs),
5329 (ins f64mem:$dst, VR128X:$src),
5330 "vmovlps\t{$src, $dst|$dst, $src}",
5331 [(store (f64 (extractelt (bc_v2f64 (v4f32 VR128X:$src)),
5332 (iPTR 0))), addr:$dst)],
5334 EVEX, EVEX_CD8<32, CD8VT2>;
5335 def VMOVLPDZ128mr : AVX512PDI<0x13, MRMDestMem, (outs),
5336 (ins f64mem:$dst, VR128X:$src),
5337 "vmovlpd\t{$src, $dst|$dst, $src}",
5338 [(store (f64 (extractelt (v2f64 VR128X:$src),
5339 (iPTR 0))), addr:$dst)],
5341 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
5343 let Predicates = [HasAVX512] in {
5345 def : Pat<(store (f64 (extractelt
5346 (v2f64 (X86VPermilpi VR128X:$src, (i8 1))),
5347 (iPTR 0))), addr:$dst),
5348 (VMOVHPDZ128mr addr:$dst, VR128X:$src)>;
5350 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128X:$src2)),
5352 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
5353 def : Pat<(store (v4i32 (X86Movlps
5354 (bc_v4i32 (loadv2i64 addr:$src1)), VR128X:$src2)), addr:$src1),
5355 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
5357 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
5359 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
5360 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
5362 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
5364 //===----------------------------------------------------------------------===//
5365 // FMA - Fused Multiply Operations
5368 multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5369 X86VectorVTInfo _, string Suff> {
5370 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in {
5371 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
5372 (ins _.RC:$src2, _.RC:$src3),
5373 OpcodeStr, "$src3, $src2", "$src2, $src3",
5374 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)), 1, 1>,
5377 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
5378 (ins _.RC:$src2, _.MemOp:$src3),
5379 OpcodeStr, "$src3, $src2", "$src2, $src3",
5380 (_.VT (OpNode _.RC:$src2, _.RC:$src1, (_.LdFrag addr:$src3))), 1, 0>,
5383 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
5384 (ins _.RC:$src2, _.ScalarMemOp:$src3),
5385 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
5386 !strconcat("$src2, ${src3}", _.BroadcastStr ),
5388 _.RC:$src1,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))), 1, 0>,
5389 AVX512FMA3Base, EVEX_B;
5392 // Additional pattern for folding broadcast nodes in other orders.
5393 def : Pat<(_.VT (vselect _.KRCWM:$mask,
5394 (OpNode _.RC:$src1, _.RC:$src2,
5395 (X86VBroadcast (_.ScalarLdFrag addr:$src3))),
5397 (!cast<Instruction>(NAME#Suff#_.ZSuffix#mbk) _.RC:$src1,
5398 _.KRCWM:$mask, _.RC:$src2, addr:$src3)>;
5401 multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
5402 X86VectorVTInfo _, string Suff> {
5403 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in
5404 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
5405 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
5406 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
5407 (_.VT ( OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3, (i32 imm:$rc))), 1, 1>,
5408 AVX512FMA3Base, EVEX_B, EVEX_RC;
5411 multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
5412 SDNode OpNodeRnd, AVX512VLVectorVTInfo _,
5414 let Predicates = [HasAVX512] in {
5415 defm Z : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info512, Suff>,
5416 avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512,
5417 Suff>, EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
5419 let Predicates = [HasVLX, HasAVX512] in {
5420 defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info256, Suff>,
5421 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
5422 defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info128, Suff>,
5423 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
5427 multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
5428 SDNode OpNodeRnd > {
5429 defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
5430 avx512vl_f32_info, "PS">;
5431 defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
5432 avx512vl_f64_info, "PD">, VEX_W;
5435 defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>;
5436 defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>;
5437 defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>;
5438 defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>;
5439 defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>;
5440 defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>;
5443 multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5444 X86VectorVTInfo _, string Suff> {
5445 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in {
5446 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
5447 (ins _.RC:$src2, _.RC:$src3),
5448 OpcodeStr, "$src3, $src2", "$src2, $src3",
5449 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)), 1, 1>,
5452 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
5453 (ins _.RC:$src2, _.MemOp:$src3),
5454 OpcodeStr, "$src3, $src2", "$src2, $src3",
5455 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1)), 1, 0>,
5458 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
5459 (ins _.RC:$src2, _.ScalarMemOp:$src3),
5460 OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
5461 "$src2, ${src3}"##_.BroadcastStr,
5462 (_.VT (OpNode _.RC:$src2,
5463 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
5464 _.RC:$src1)), 1, 0>, AVX512FMA3Base, EVEX_B;
5467 // Additional patterns for folding broadcast nodes in other orders.
5468 def : Pat<(_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
5469 _.RC:$src2, _.RC:$src1)),
5470 (!cast<Instruction>(NAME#Suff#_.ZSuffix#mb) _.RC:$src1,
5471 _.RC:$src2, addr:$src3)>;
5472 def : Pat<(_.VT (vselect _.KRCWM:$mask,
5473 (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
5474 _.RC:$src2, _.RC:$src1),
5476 (!cast<Instruction>(NAME#Suff#_.ZSuffix#mbk) _.RC:$src1,
5477 _.KRCWM:$mask, _.RC:$src2, addr:$src3)>;
5478 def : Pat<(_.VT (vselect _.KRCWM:$mask,
5479 (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
5480 _.RC:$src2, _.RC:$src1),
5482 (!cast<Instruction>(NAME#Suff#_.ZSuffix#mbkz) _.RC:$src1,
5483 _.KRCWM:$mask, _.RC:$src2, addr:$src3)>;
5486 multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
5487 X86VectorVTInfo _, string Suff> {
5488 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in
5489 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
5490 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
5491 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
5492 (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc))), 1, 1>,
5493 AVX512FMA3Base, EVEX_B, EVEX_RC;
5496 multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
5497 SDNode OpNodeRnd, AVX512VLVectorVTInfo _,
5499 let Predicates = [HasAVX512] in {
5500 defm Z : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info512, Suff>,
5501 avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512,
5502 Suff>, EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
5504 let Predicates = [HasVLX, HasAVX512] in {
5505 defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info256, Suff>,
5506 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
5507 defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info128, Suff>,
5508 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
5512 multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
5513 SDNode OpNodeRnd > {
5514 defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
5515 avx512vl_f32_info, "PS">;
5516 defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
5517 avx512vl_f64_info, "PD">, VEX_W;
5520 defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>;
5521 defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>;
5522 defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>;
5523 defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>;
5524 defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>;
5525 defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>;
5527 multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5528 X86VectorVTInfo _, string Suff> {
5529 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in {
5530 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
5531 (ins _.RC:$src2, _.RC:$src3),
5532 OpcodeStr, "$src3, $src2", "$src2, $src3",
5533 (_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)), 1, 1>,
5536 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
5537 (ins _.RC:$src2, _.MemOp:$src3),
5538 OpcodeStr, "$src3, $src2", "$src2, $src3",
5539 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src3), _.RC:$src2)), 1, 0>,
5542 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
5543 (ins _.RC:$src2, _.ScalarMemOp:$src3),
5544 OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
5545 "$src2, ${src3}"##_.BroadcastStr,
5546 (_.VT (OpNode _.RC:$src1,
5547 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
5548 _.RC:$src2)), 1, 0>, AVX512FMA3Base, EVEX_B;
5551 // Additional patterns for folding broadcast nodes in other orders.
5552 def : Pat<(_.VT (vselect _.KRCWM:$mask,
5553 (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
5554 _.RC:$src1, _.RC:$src2),
5556 (!cast<Instruction>(NAME#Suff#_.ZSuffix#mbk) _.RC:$src1,
5557 _.KRCWM:$mask, _.RC:$src2, addr:$src3)>;
5560 multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
5561 X86VectorVTInfo _, string Suff> {
5562 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in
5563 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
5564 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
5565 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
5566 (_.VT ( OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2, (i32 imm:$rc))), 1, 1>,
5567 AVX512FMA3Base, EVEX_B, EVEX_RC;
5570 multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
5571 SDNode OpNodeRnd, AVX512VLVectorVTInfo _,
5573 let Predicates = [HasAVX512] in {
5574 defm Z : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info512, Suff>,
5575 avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512,
5576 Suff>, EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
5578 let Predicates = [HasVLX, HasAVX512] in {
5579 defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info256, Suff>,
5580 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
5581 defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info128, Suff>,
5582 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
5586 multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
5587 SDNode OpNodeRnd > {
5588 defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
5589 avx512vl_f32_info, "PS">;
5590 defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
5591 avx512vl_f64_info, "PD">, VEX_W;
5594 defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>;
5595 defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>;
5596 defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>;
5597 defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>;
5598 defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>;
5599 defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>;
5602 let Constraints = "$src1 = $dst" in {
5603 multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5604 dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
5605 dag RHS_r, dag RHS_m > {
5606 defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5607 (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
5608 "$src3, $src2", "$src2, $src3", RHS_VEC_r, 1, 1>, AVX512FMA3Base;
5610 defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5611 (ins _.RC:$src2, _.IntScalarMemOp:$src3), OpcodeStr,
5612 "$src3, $src2", "$src2, $src3", RHS_VEC_m, 1, 1>, AVX512FMA3Base;
5614 defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5615 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
5616 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb, 1, 1>,
5617 AVX512FMA3Base, EVEX_B, EVEX_RC;
5619 let isCodeGenOnly = 1, isCommutable = 1 in {
5620 def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
5621 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
5622 !strconcat(OpcodeStr,
5623 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5625 def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
5626 (ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
5627 !strconcat(OpcodeStr,
5628 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5630 }// isCodeGenOnly = 1
5632 }// Constraints = "$src1 = $dst"
5634 multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
5635 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnds1,
5636 SDNode OpNodeRnds3, X86VectorVTInfo _ , string SUFF> {
5637 let ExeDomain = _.ExeDomain in {
5638 defm NAME#213#SUFF#Z: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
5639 // Operands for intrinsic are in 123 order to preserve passthu
5641 (_.VT (OpNodeRnds1 _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 FROUND_CURRENT))),
5642 (_.VT (OpNodeRnds1 _.RC:$src1, _.RC:$src2,
5643 _.ScalarIntMemCPat:$src3, (i32 FROUND_CURRENT))),
5644 (_.VT (OpNodeRnds1 _.RC:$src1, _.RC:$src2, _.RC:$src3,
5646 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
5648 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
5649 (_.ScalarLdFrag addr:$src3))))>;
5651 defm NAME#231#SUFF#Z: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
5652 (_.VT (OpNodeRnds3 _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 FROUND_CURRENT))),
5653 (_.VT (OpNodeRnds3 _.RC:$src2, _.ScalarIntMemCPat:$src3,
5654 _.RC:$src1, (i32 FROUND_CURRENT))),
5655 (_.VT ( OpNodeRnds3 _.RC:$src2, _.RC:$src3, _.RC:$src1,
5657 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
5659 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
5660 (_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
5662 defm NAME#132#SUFF#Z: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
5663 (_.VT (OpNodeRnds1 _.RC:$src1, _.RC:$src3, _.RC:$src2, (i32 FROUND_CURRENT))),
5664 (_.VT (OpNodeRnds1 _.RC:$src1, _.ScalarIntMemCPat:$src3,
5665 _.RC:$src2, (i32 FROUND_CURRENT))),
5666 (_.VT (OpNodeRnds1 _.RC:$src1, _.RC:$src3, _.RC:$src2,
5668 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
5670 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
5671 (_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
5675 multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
5676 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnds1,
5677 SDNode OpNodeRnds3> {
5678 let Predicates = [HasAVX512] in {
5679 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
5680 OpNodeRnds1, OpNodeRnds3, f32x_info, "SS">,
5681 EVEX_CD8<32, CD8VT1>, VEX_LIG;
5682 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
5683 OpNodeRnds1, OpNodeRnds3, f64x_info, "SD">,
5684 EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
5688 defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnds1,
5690 defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnds1,
5692 defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd,
5693 X86FnmaddRnds1, X86FnmaddRnds3>;
5694 defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub,
5695 X86FnmsubRnds1, X86FnmsubRnds3>;
5697 //===----------------------------------------------------------------------===//
5698 // AVX-512 Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit IFMA
5699 //===----------------------------------------------------------------------===//
5700 let Constraints = "$src1 = $dst" in {
5701 multiclass avx512_pmadd52_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5702 X86VectorVTInfo _> {
5703 let ExeDomain = _.ExeDomain in {
5704 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
5705 (ins _.RC:$src2, _.RC:$src3),
5706 OpcodeStr, "$src3, $src2", "$src2, $src3",
5707 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
5710 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
5711 (ins _.RC:$src2, _.MemOp:$src3),
5712 OpcodeStr, "$src3, $src2", "$src2, $src3",
5713 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
5716 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
5717 (ins _.RC:$src2, _.ScalarMemOp:$src3),
5718 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
5719 !strconcat("$src2, ${src3}", _.BroadcastStr ),
5721 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
5722 AVX512FMA3Base, EVEX_B;
5725 } // Constraints = "$src1 = $dst"
5727 multiclass avx512_pmadd52_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
5728 AVX512VLVectorVTInfo _> {
5729 let Predicates = [HasIFMA] in {
5730 defm Z : avx512_pmadd52_rm<opc, OpcodeStr, OpNode, _.info512>,
5731 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
5733 let Predicates = [HasVLX, HasIFMA] in {
5734 defm Z256 : avx512_pmadd52_rm<opc, OpcodeStr, OpNode, _.info256>,
5735 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
5736 defm Z128 : avx512_pmadd52_rm<opc, OpcodeStr, OpNode, _.info128>,
5737 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
5741 defm VPMADD52LUQ : avx512_pmadd52_common<0xb4, "vpmadd52luq", x86vpmadd52l,
5742 avx512vl_i64_info>, VEX_W;
5743 defm VPMADD52HUQ : avx512_pmadd52_common<0xb5, "vpmadd52huq", x86vpmadd52h,
5744 avx512vl_i64_info>, VEX_W;
5746 //===----------------------------------------------------------------------===//
5747 // AVX-512 Scalar convert from sign integer to float/double
5748 //===----------------------------------------------------------------------===//
5750 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
5751 X86VectorVTInfo DstVT, X86MemOperand x86memop,
5752 PatFrag ld_frag, string asm> {
5753 let hasSideEffects = 0 in {
5754 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
5755 (ins DstVT.FRC:$src1, SrcRC:$src),
5756 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
5759 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
5760 (ins DstVT.FRC:$src1, x86memop:$src),
5761 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
5763 } // hasSideEffects = 0
5764 let isCodeGenOnly = 1 in {
5765 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
5766 (ins DstVT.RC:$src1, SrcRC:$src2),
5767 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5768 [(set DstVT.RC:$dst,
5769 (OpNode (DstVT.VT DstVT.RC:$src1),
5771 (i32 FROUND_CURRENT)))]>, EVEX_4V;
5773 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
5774 (ins DstVT.RC:$src1, x86memop:$src2),
5775 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5776 [(set DstVT.RC:$dst,
5777 (OpNode (DstVT.VT DstVT.RC:$src1),
5778 (ld_frag addr:$src2),
5779 (i32 FROUND_CURRENT)))]>, EVEX_4V;
5780 }//isCodeGenOnly = 1
5783 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
5784 X86VectorVTInfo DstVT, string asm> {
5785 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
5786 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
5788 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
5789 [(set DstVT.RC:$dst,
5790 (OpNode (DstVT.VT DstVT.RC:$src1),
5792 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
5795 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
5796 X86VectorVTInfo DstVT, X86MemOperand x86memop,
5797 PatFrag ld_frag, string asm> {
5798 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
5799 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
5803 let Predicates = [HasAVX512] in {
5804 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
5805 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
5806 XS, EVEX_CD8<32, CD8VT1>;
5807 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
5808 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
5809 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
5810 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
5811 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
5812 XD, EVEX_CD8<32, CD8VT1>;
5813 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
5814 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
5815 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
5817 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
5818 (VCVTSI2SSZrm FR64X:$dst, FR64X:$src1, i32mem:$src), 0>;
5819 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
5820 (VCVTSI2SDZrm FR64X:$dst, FR64X:$src1, i32mem:$src), 0>;
5822 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
5823 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
5824 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
5825 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
5826 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
5827 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
5828 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
5829 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
5831 def : Pat<(f32 (sint_to_fp GR32:$src)),
5832 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
5833 def : Pat<(f32 (sint_to_fp GR64:$src)),
5834 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
5835 def : Pat<(f64 (sint_to_fp GR32:$src)),
5836 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
5837 def : Pat<(f64 (sint_to_fp GR64:$src)),
5838 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
5840 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR32,
5841 v4f32x_info, i32mem, loadi32,
5842 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
5843 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
5844 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
5845 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
5846 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, GR32, v2f64x_info,
5847 i32mem, loadi32, "cvtusi2sd{l}">,
5848 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
5849 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
5850 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
5851 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
5853 def : InstAlias<"vcvtusi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
5854 (VCVTUSI2SSZrm FR64X:$dst, FR64X:$src1, i32mem:$src), 0>;
5855 def : InstAlias<"vcvtusi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
5856 (VCVTUSI2SDZrm FR64X:$dst, FR64X:$src1, i32mem:$src), 0>;
5858 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
5859 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
5860 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
5861 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
5862 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
5863 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
5864 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
5865 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
5867 def : Pat<(f32 (uint_to_fp GR32:$src)),
5868 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
5869 def : Pat<(f32 (uint_to_fp GR64:$src)),
5870 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
5871 def : Pat<(f64 (uint_to_fp GR32:$src)),
5872 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
5873 def : Pat<(f64 (uint_to_fp GR64:$src)),
5874 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
5877 //===----------------------------------------------------------------------===//
5878 // AVX-512 Scalar convert from float/double to integer
5879 //===----------------------------------------------------------------------===//
5880 multiclass avx512_cvt_s_int_round<bits<8> opc, X86VectorVTInfo SrcVT ,
5881 X86VectorVTInfo DstVT, SDNode OpNode, string asm> {
5882 let Predicates = [HasAVX512] in {
5883 def rr : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst), (ins SrcVT.RC:$src),
5884 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
5885 [(set DstVT.RC:$dst, (OpNode (SrcVT.VT SrcVT.RC:$src),(i32 FROUND_CURRENT)))]>,
5887 def rb : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst), (ins SrcVT.RC:$src, AVX512RC:$rc),
5888 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
5889 [(set DstVT.RC:$dst, (OpNode (SrcVT.VT SrcVT.RC:$src),(i32 imm:$rc)))]>,
5890 EVEX, VEX_LIG, EVEX_B, EVEX_RC;
5891 def rm : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst), (ins SrcVT.IntScalarMemOp:$src),
5892 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
5893 [(set DstVT.RC:$dst, (OpNode
5894 (SrcVT.VT SrcVT.ScalarIntMemCPat:$src),
5895 (i32 FROUND_CURRENT)))]>,
5897 } // Predicates = [HasAVX512]
5900 // Convert float/double to signed/unsigned int 32/64
5901 defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, f32x_info, i32x_info,
5902 X86cvts2si, "cvtss2si">,
5903 XS, EVEX_CD8<32, CD8VT1>;
5904 defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, f32x_info, i64x_info,
5905 X86cvts2si, "cvtss2si">,
5906 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
5907 defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, f32x_info, i32x_info,
5908 X86cvts2usi, "cvtss2usi">,
5909 XS, EVEX_CD8<32, CD8VT1>;
5910 defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, f32x_info, i64x_info,
5911 X86cvts2usi, "cvtss2usi">, XS, VEX_W,
5912 EVEX_CD8<32, CD8VT1>;
5913 defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, f64x_info, i32x_info,
5914 X86cvts2si, "cvtsd2si">,
5915 XD, EVEX_CD8<64, CD8VT1>;
5916 defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, f64x_info, i64x_info,
5917 X86cvts2si, "cvtsd2si">,
5918 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
5919 defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, f64x_info, i32x_info,
5920 X86cvts2usi, "cvtsd2usi">,
5921 XD, EVEX_CD8<64, CD8VT1>;
5922 defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, f64x_info, i64x_info,
5923 X86cvts2usi, "cvtsd2usi">, XD, VEX_W,
5924 EVEX_CD8<64, CD8VT1>;
5926 // The SSE version of these instructions are disabled for AVX512.
5927 // Therefore, the SSE intrinsics are mapped to the AVX512 instructions.
5928 let Predicates = [HasAVX512] in {
5929 def : Pat<(i32 (int_x86_sse_cvtss2si (v4f32 VR128X:$src))),
5930 (VCVTSS2SIZrr VR128X:$src)>;
5931 def : Pat<(i32 (int_x86_sse_cvtss2si sse_load_f32:$src)),
5932 (VCVTSS2SIZrm sse_load_f32:$src)>;
5933 def : Pat<(i64 (int_x86_sse_cvtss2si64 (v4f32 VR128X:$src))),
5934 (VCVTSS2SI64Zrr VR128X:$src)>;
5935 def : Pat<(i64 (int_x86_sse_cvtss2si64 sse_load_f32:$src)),
5936 (VCVTSS2SI64Zrm sse_load_f32:$src)>;
5937 def : Pat<(i32 (int_x86_sse2_cvtsd2si (v2f64 VR128X:$src))),
5938 (VCVTSD2SIZrr VR128X:$src)>;
5939 def : Pat<(i32 (int_x86_sse2_cvtsd2si sse_load_f64:$src)),
5940 (VCVTSD2SIZrm sse_load_f64:$src)>;
5941 def : Pat<(i64 (int_x86_sse2_cvtsd2si64 (v2f64 VR128X:$src))),
5942 (VCVTSD2SI64Zrr VR128X:$src)>;
5943 def : Pat<(i64 (int_x86_sse2_cvtsd2si64 sse_load_f64:$src)),
5944 (VCVTSD2SI64Zrm sse_load_f64:$src)>;
5947 let Predicates = [HasAVX512] in {
5948 def : Pat<(int_x86_sse_cvtsi2ss VR128X:$src1, GR32:$src2),
5949 (VCVTSI2SSZrr_Int VR128X:$src1, GR32:$src2)>;
5950 def : Pat<(int_x86_sse_cvtsi2ss VR128X:$src1, (loadi32 addr:$src2)),
5951 (VCVTSI2SSZrm_Int VR128X:$src1, addr:$src2)>;
5952 def : Pat<(int_x86_sse_cvtsi642ss VR128X:$src1, GR64:$src2),
5953 (VCVTSI642SSZrr_Int VR128X:$src1, GR64:$src2)>;
5954 def : Pat<(int_x86_sse_cvtsi642ss VR128X:$src1, (loadi64 addr:$src2)),
5955 (VCVTSI642SSZrm_Int VR128X:$src1, addr:$src2)>;
5956 def : Pat<(int_x86_sse2_cvtsi2sd VR128X:$src1, GR32:$src2),
5957 (VCVTSI2SDZrr_Int VR128X:$src1, GR32:$src2)>;
5958 def : Pat<(int_x86_sse2_cvtsi2sd VR128X:$src1, (loadi32 addr:$src2)),
5959 (VCVTSI2SDZrm_Int VR128X:$src1, addr:$src2)>;
5960 def : Pat<(int_x86_sse2_cvtsi642sd VR128X:$src1, GR64:$src2),
5961 (VCVTSI642SDZrr_Int VR128X:$src1, GR64:$src2)>;
5962 def : Pat<(int_x86_sse2_cvtsi642sd VR128X:$src1, (loadi64 addr:$src2)),
5963 (VCVTSI642SDZrm_Int VR128X:$src1, addr:$src2)>;
5964 def : Pat<(int_x86_avx512_cvtusi2sd VR128X:$src1, GR32:$src2),
5965 (VCVTUSI2SDZrr_Int VR128X:$src1, GR32:$src2)>;
5966 def : Pat<(int_x86_avx512_cvtusi2sd VR128X:$src1, (loadi32 addr:$src2)),
5967 (VCVTUSI2SDZrm_Int VR128X:$src1, addr:$src2)>;
5968 } // Predicates = [HasAVX512]
5970 // Patterns used for matching vcvtsi2s{s,d} intrinsic sequences from clang
5971 // which produce unnecessary vmovs{s,d} instructions
5972 let Predicates = [HasAVX512] in {
5973 def : Pat<(v4f32 (X86Movss
5974 (v4f32 VR128X:$dst),
5975 (v4f32 (scalar_to_vector (f32 (sint_to_fp GR64:$src)))))),
5976 (VCVTSI642SSZrr_Int VR128X:$dst, GR64:$src)>;
5978 def : Pat<(v4f32 (X86Movss
5979 (v4f32 VR128X:$dst),
5980 (v4f32 (scalar_to_vector (f32 (sint_to_fp GR32:$src)))))),
5981 (VCVTSI2SSZrr_Int VR128X:$dst, GR32:$src)>;
5983 def : Pat<(v2f64 (X86Movsd
5984 (v2f64 VR128X:$dst),
5985 (v2f64 (scalar_to_vector (f64 (sint_to_fp GR64:$src)))))),
5986 (VCVTSI642SDZrr_Int VR128X:$dst, GR64:$src)>;
5988 def : Pat<(v2f64 (X86Movsd
5989 (v2f64 VR128X:$dst),
5990 (v2f64 (scalar_to_vector (f64 (sint_to_fp GR32:$src)))))),
5991 (VCVTSI2SDZrr_Int VR128X:$dst, GR32:$src)>;
5992 } // Predicates = [HasAVX512]
5994 // Convert float/double to signed/unsigned int 32/64 with truncation
5995 multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC,
5996 X86VectorVTInfo _DstRC, SDNode OpNode,
5997 SDNode OpNodeRnd, string aliasStr>{
5998 let Predicates = [HasAVX512] in {
5999 def rr : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
6000 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
6001 [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX;
6002 let hasSideEffects = 0 in
6003 def rb : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
6004 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
6006 def rm : AVX512<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.ScalarMemOp:$src),
6007 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
6008 [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>,
6011 def : InstAlias<asm # aliasStr # "\t{$src, $dst|$dst, $src}",
6012 (!cast<Instruction>(NAME # "rr") _DstRC.RC:$dst, _SrcRC.FRC:$src), 0>;
6013 def : InstAlias<asm # aliasStr # "\t\t{{sae}, $src, $dst|$dst, $src, {sae}}",
6014 (!cast<Instruction>(NAME # "rb") _DstRC.RC:$dst, _SrcRC.FRC:$src), 0>;
6015 def : InstAlias<asm # aliasStr # "\t{$src, $dst|$dst, $src}",
6016 (!cast<Instruction>(NAME # "rm") _DstRC.RC:$dst,
6017 _SrcRC.ScalarMemOp:$src), 0>;
6019 let isCodeGenOnly = 1 in {
6020 def rr_Int : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
6021 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
6022 [(set _DstRC.RC:$dst, (OpNodeRnd (_SrcRC.VT _SrcRC.RC:$src),
6023 (i32 FROUND_CURRENT)))]>, EVEX, VEX_LIG;
6024 def rb_Int : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
6025 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
6026 [(set _DstRC.RC:$dst, (OpNodeRnd (_SrcRC.VT _SrcRC.RC:$src),
6027 (i32 FROUND_NO_EXC)))]>,
6028 EVEX,VEX_LIG , EVEX_B;
6029 let mayLoad = 1, hasSideEffects = 0 in
6030 def rm_Int : AVX512<opc, MRMSrcMem, (outs _DstRC.RC:$dst),
6031 (ins _SrcRC.IntScalarMemOp:$src),
6032 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
6035 } // isCodeGenOnly = 1
6040 defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "vcvttss2si", f32x_info, i32x_info,
6041 fp_to_sint, X86cvtts2IntRnd, "{l}">,
6042 XS, EVEX_CD8<32, CD8VT1>;
6043 defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "vcvttss2si", f32x_info, i64x_info,
6044 fp_to_sint, X86cvtts2IntRnd, "{q}">,
6045 VEX_W, XS, EVEX_CD8<32, CD8VT1>;
6046 defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "vcvttsd2si", f64x_info, i32x_info,
6047 fp_to_sint, X86cvtts2IntRnd, "{l}">,
6048 XD, EVEX_CD8<64, CD8VT1>;
6049 defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "vcvttsd2si", f64x_info, i64x_info,
6050 fp_to_sint, X86cvtts2IntRnd, "{q}">,
6051 VEX_W, XD, EVEX_CD8<64, CD8VT1>;
6053 defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "vcvttss2usi", f32x_info, i32x_info,
6054 fp_to_uint, X86cvtts2UIntRnd, "{l}">,
6055 XS, EVEX_CD8<32, CD8VT1>;
6056 defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "vcvttss2usi", f32x_info, i64x_info,
6057 fp_to_uint, X86cvtts2UIntRnd, "{q}">,
6058 XS,VEX_W, EVEX_CD8<32, CD8VT1>;
6059 defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "vcvttsd2usi", f64x_info, i32x_info,
6060 fp_to_uint, X86cvtts2UIntRnd, "{l}">,
6061 XD, EVEX_CD8<64, CD8VT1>;
6062 defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "vcvttsd2usi", f64x_info, i64x_info,
6063 fp_to_uint, X86cvtts2UIntRnd, "{q}">,
6064 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
6065 let Predicates = [HasAVX512] in {
6066 def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))),
6067 (VCVTTSS2SIZrr_Int VR128X:$src)>;
6068 def : Pat<(i32 (int_x86_sse_cvttss2si sse_load_f32:$src)),
6069 (VCVTTSS2SIZrm_Int ssmem:$src)>;
6070 def : Pat<(i64 (int_x86_sse_cvttss2si64 (v4f32 VR128X:$src))),
6071 (VCVTTSS2SI64Zrr_Int VR128X:$src)>;
6072 def : Pat<(i64 (int_x86_sse_cvttss2si64 sse_load_f32:$src)),
6073 (VCVTTSS2SI64Zrm_Int ssmem:$src)>;
6074 def : Pat<(i32 (int_x86_sse2_cvttsd2si (v2f64 VR128X:$src))),
6075 (VCVTTSD2SIZrr_Int VR128X:$src)>;
6076 def : Pat<(i32 (int_x86_sse2_cvttsd2si sse_load_f64:$src)),
6077 (VCVTTSD2SIZrm_Int sdmem:$src)>;
6078 def : Pat<(i64 (int_x86_sse2_cvttsd2si64 (v2f64 VR128X:$src))),
6079 (VCVTTSD2SI64Zrr_Int VR128X:$src)>;
6080 def : Pat<(i64 (int_x86_sse2_cvttsd2si64 sse_load_f64:$src)),
6081 (VCVTTSD2SI64Zrm_Int sdmem:$src)>;
6083 //===----------------------------------------------------------------------===//
6084 // AVX-512 Convert form float to double and back
6085 //===----------------------------------------------------------------------===//
6086 multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6087 X86VectorVTInfo _Src, SDNode OpNode> {
6088 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6089 (ins _.RC:$src1, _Src.RC:$src2), OpcodeStr,
6090 "$src2, $src1", "$src1, $src2",
6091 (_.VT (OpNode (_.VT _.RC:$src1),
6092 (_Src.VT _Src.RC:$src2),
6093 (i32 FROUND_CURRENT)))>,
6094 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
6095 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6096 (ins _.RC:$src1, _Src.IntScalarMemOp:$src2), OpcodeStr,
6097 "$src2, $src1", "$src1, $src2",
6098 (_.VT (OpNode (_.VT _.RC:$src1),
6099 (_Src.VT _Src.ScalarIntMemCPat:$src2),
6100 (i32 FROUND_CURRENT)))>,
6101 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
6103 let isCodeGenOnly = 1, hasSideEffects = 0 in {
6104 def rr : I<opc, MRMSrcReg, (outs _.FRC:$dst),
6105 (ins _.FRC:$src1, _Src.FRC:$src2),
6106 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
6107 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
6109 def rm : I<opc, MRMSrcMem, (outs _.FRC:$dst),
6110 (ins _.FRC:$src1, _Src.ScalarMemOp:$src2),
6111 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
6112 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
6116 // Scalar Coversion with SAE - suppress all exceptions
6117 multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6118 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
6119 defm rrb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6120 (ins _.RC:$src1, _Src.RC:$src2), OpcodeStr,
6121 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
6122 (_.VT (OpNodeRnd (_.VT _.RC:$src1),
6123 (_Src.VT _Src.RC:$src2),
6124 (i32 FROUND_NO_EXC)))>,
6125 EVEX_4V, VEX_LIG, EVEX_B;
6128 // Scalar Conversion with rounding control (RC)
6129 multiclass avx512_cvt_fp_rc_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6130 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
6131 defm rrb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6132 (ins _.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,
6133 "$rc, $src2, $src1", "$src1, $src2, $rc",
6134 (_.VT (OpNodeRnd (_.VT _.RC:$src1),
6135 (_Src.VT _Src.RC:$src2), (i32 imm:$rc)))>,
6136 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
6139 multiclass avx512_cvt_fp_scalar_sd2ss<bits<8> opc, string OpcodeStr,
6140 SDNode OpNodeRnd, X86VectorVTInfo _src,
6141 X86VectorVTInfo _dst> {
6142 let Predicates = [HasAVX512] in {
6143 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
6144 avx512_cvt_fp_rc_scalar<opc, OpcodeStr, _dst, _src,
6145 OpNodeRnd>, VEX_W, EVEX_CD8<64, CD8VT1>, XD;
6149 multiclass avx512_cvt_fp_scalar_ss2sd<bits<8> opc, string OpcodeStr,
6150 SDNode OpNodeRnd, X86VectorVTInfo _src,
6151 X86VectorVTInfo _dst> {
6152 let Predicates = [HasAVX512] in {
6153 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
6154 avx512_cvt_fp_sae_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
6155 EVEX_CD8<32, CD8VT1>, XS;
6158 defm VCVTSD2SS : avx512_cvt_fp_scalar_sd2ss<0x5A, "vcvtsd2ss",
6159 X86froundRnd, f64x_info, f32x_info>;
6160 defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd",
6161 X86fpextRnd,f32x_info, f64x_info >;
6163 def : Pat<(f64 (fpextend FR32X:$src)),
6164 (VCVTSS2SDZrr (COPY_TO_REGCLASS FR32X:$src, FR64X), FR32X:$src)>,
6165 Requires<[HasAVX512]>;
6166 def : Pat<(f64 (fpextend (loadf32 addr:$src))),
6167 (VCVTSS2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>,
6168 Requires<[HasAVX512]>;
6170 def : Pat<(f64 (extloadf32 addr:$src)),
6171 (VCVTSS2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>,
6172 Requires<[HasAVX512, OptForSize]>;
6174 def : Pat<(f64 (extloadf32 addr:$src)),
6175 (VCVTSS2SDZrr (f64 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
6176 Requires<[HasAVX512, OptForSpeed]>;
6178 def : Pat<(f32 (fpround FR64X:$src)),
6179 (VCVTSD2SSZrr (COPY_TO_REGCLASS FR64X:$src, FR32X), FR64X:$src)>,
6180 Requires<[HasAVX512]>;
6182 def : Pat<(v4f32 (X86Movss
6183 (v4f32 VR128X:$dst),
6184 (v4f32 (scalar_to_vector
6185 (f32 (fpround (f64 (extractelt VR128X:$src, (iPTR 0))))))))),
6186 (VCVTSD2SSZrr_Int VR128X:$dst, VR128X:$src)>,
6187 Requires<[HasAVX512]>;
6189 def : Pat<(v2f64 (X86Movsd
6190 (v2f64 VR128X:$dst),
6191 (v2f64 (scalar_to_vector
6192 (f64 (fpextend (f32 (extractelt VR128X:$src, (iPTR 0))))))))),
6193 (VCVTSS2SDZrr_Int VR128X:$dst, VR128X:$src)>,
6194 Requires<[HasAVX512]>;
6196 //===----------------------------------------------------------------------===//
6197 // AVX-512 Vector convert from signed/unsigned integer to float/double
6198 // and from float/double to signed/unsigned integer
6199 //===----------------------------------------------------------------------===//
6201 multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6202 X86VectorVTInfo _Src, SDNode OpNode,
6203 string Broadcast = _.BroadcastStr,
6204 string Alias = "", X86MemOperand MemOp = _Src.MemOp> {
6206 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6207 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
6208 (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
6210 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6211 (ins MemOp:$src), OpcodeStr#Alias, "$src", "$src",
6212 (_.VT (OpNode (_Src.VT
6213 (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
6215 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6216 (ins _Src.ScalarMemOp:$src), OpcodeStr,
6217 "${src}"##Broadcast, "${src}"##Broadcast,
6218 (_.VT (OpNode (_Src.VT
6219 (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
6222 // Coversion with SAE - suppress all exceptions
6223 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6224 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
6225 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6226 (ins _Src.RC:$src), OpcodeStr,
6227 "{sae}, $src", "$src, {sae}",
6228 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
6229 (i32 FROUND_NO_EXC)))>,
6233 // Conversion with rounding control (RC)
6234 multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6235 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
6236 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6237 (ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
6238 "$rc, $src", "$src, $rc",
6239 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
6240 EVEX, EVEX_B, EVEX_RC;
6243 // Extend Float to Double
6244 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
6245 let Predicates = [HasAVX512] in {
6246 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fpextend>,
6247 avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
6248 X86vfpextRnd>, EVEX_V512;
6250 let Predicates = [HasVLX] in {
6251 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
6252 X86vfpext, "{1to2}", "", f64mem>, EVEX_V128;
6253 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fpextend>,
6258 // Truncate Double to Float
6259 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
6260 let Predicates = [HasAVX512] in {
6261 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fpround>,
6262 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
6263 X86vfproundRnd>, EVEX_V512;
6265 let Predicates = [HasVLX] in {
6266 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
6267 X86vfpround, "{1to2}", "{x}">, EVEX_V128;
6268 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fpround,
6269 "{1to4}", "{y}">, EVEX_V256;
6271 def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
6272 (!cast<Instruction>(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>;
6273 def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
6274 (!cast<Instruction>(NAME # "Z128rm") VR128X:$dst, f128mem:$src), 0>;
6275 def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
6276 (!cast<Instruction>(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>;
6277 def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
6278 (!cast<Instruction>(NAME # "Z256rm") VR128X:$dst, f256mem:$src), 0>;
6282 defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
6283 VEX_W, PD, EVEX_CD8<64, CD8VF>;
6284 defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
6285 PS, EVEX_CD8<32, CD8VH>;
6287 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
6288 (VCVTPS2PDZrm addr:$src)>;
6290 let Predicates = [HasVLX] in {
6291 let AddedComplexity = 15 in
6292 def : Pat<(X86vzmovl (v2f64 (bitconvert
6293 (v4f32 (X86vfpround (v2f64 VR128X:$src)))))),
6294 (VCVTPD2PSZ128rr VR128X:$src)>;
6295 def : Pat<(v2f64 (extloadv2f32 addr:$src)),
6296 (VCVTPS2PDZ128rm addr:$src)>;
6297 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
6298 (VCVTPS2PDZ256rm addr:$src)>;
6301 // Convert Signed/Unsigned Doubleword to Double
6302 multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
6304 // No rounding in this op
6305 let Predicates = [HasAVX512] in
6306 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
6309 let Predicates = [HasVLX] in {
6310 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
6311 OpNode128, "{1to2}", "", i64mem>, EVEX_V128;
6312 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
6317 // Convert Signed/Unsigned Doubleword to Float
6318 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
6320 let Predicates = [HasAVX512] in
6321 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
6322 avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
6323 OpNodeRnd>, EVEX_V512;
6325 let Predicates = [HasVLX] in {
6326 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
6328 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
6333 // Convert Float to Signed/Unsigned Doubleword with truncation
6334 multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
6335 SDNode OpNode, SDNode OpNodeRnd> {
6336 let Predicates = [HasAVX512] in {
6337 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
6338 avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
6339 OpNodeRnd>, EVEX_V512;
6341 let Predicates = [HasVLX] in {
6342 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
6344 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
6349 // Convert Float to Signed/Unsigned Doubleword
6350 multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
6351 SDNode OpNode, SDNode OpNodeRnd> {
6352 let Predicates = [HasAVX512] in {
6353 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
6354 avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
6355 OpNodeRnd>, EVEX_V512;
6357 let Predicates = [HasVLX] in {
6358 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
6360 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
6365 // Convert Double to Signed/Unsigned Doubleword with truncation
6366 multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr, SDNode OpNode,
6367 SDNode OpNode128, SDNode OpNodeRnd> {
6368 let Predicates = [HasAVX512] in {
6369 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
6370 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
6371 OpNodeRnd>, EVEX_V512;
6373 let Predicates = [HasVLX] in {
6374 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
6375 // memory forms of these instructions in Asm Parser. They have the same
6376 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
6377 // due to the same reason.
6378 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info,
6379 OpNode128, "{1to2}", "{x}">, EVEX_V128;
6380 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
6381 "{1to4}", "{y}">, EVEX_V256;
6383 def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
6384 (!cast<Instruction>(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>;
6385 def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
6386 (!cast<Instruction>(NAME # "Z128rm") VR128X:$dst, i128mem:$src), 0>;
6387 def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
6388 (!cast<Instruction>(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>;
6389 def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
6390 (!cast<Instruction>(NAME # "Z256rm") VR128X:$dst, i256mem:$src), 0>;
6394 // Convert Double to Signed/Unsigned Doubleword
6395 multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
6396 SDNode OpNode, SDNode OpNodeRnd> {
6397 let Predicates = [HasAVX512] in {
6398 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
6399 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
6400 OpNodeRnd>, EVEX_V512;
6402 let Predicates = [HasVLX] in {
6403 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
6404 // memory forms of these instructions in Asm Parcer. They have the same
6405 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
6406 // due to the same reason.
6407 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
6408 "{1to2}", "{x}">, EVEX_V128;
6409 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
6410 "{1to4}", "{y}">, EVEX_V256;
6412 def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
6413 (!cast<Instruction>(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>;
6414 def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
6415 (!cast<Instruction>(NAME # "Z128rm") VR128X:$dst, f128mem:$src), 0>;
6416 def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
6417 (!cast<Instruction>(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>;
6418 def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
6419 (!cast<Instruction>(NAME # "Z256rm") VR128X:$dst, f256mem:$src), 0>;
6423 // Convert Double to Signed/Unsigned Quardword
6424 multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
6425 SDNode OpNode, SDNode OpNodeRnd> {
6426 let Predicates = [HasDQI] in {
6427 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
6428 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
6429 OpNodeRnd>, EVEX_V512;
6431 let Predicates = [HasDQI, HasVLX] in {
6432 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
6434 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
6439 // Convert Double to Signed/Unsigned Quardword with truncation
6440 multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
6441 SDNode OpNode, SDNode OpNodeRnd> {
6442 let Predicates = [HasDQI] in {
6443 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
6444 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
6445 OpNodeRnd>, EVEX_V512;
6447 let Predicates = [HasDQI, HasVLX] in {
6448 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
6450 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
6455 // Convert Signed/Unsigned Quardword to Double
6456 multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
6457 SDNode OpNode, SDNode OpNodeRnd> {
6458 let Predicates = [HasDQI] in {
6459 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
6460 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
6461 OpNodeRnd>, EVEX_V512;
6463 let Predicates = [HasDQI, HasVLX] in {
6464 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
6466 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
6471 // Convert Float to Signed/Unsigned Quardword
6472 multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
6473 SDNode OpNode, SDNode OpNodeRnd> {
6474 let Predicates = [HasDQI] in {
6475 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
6476 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
6477 OpNodeRnd>, EVEX_V512;
6479 let Predicates = [HasDQI, HasVLX] in {
6480 // Explicitly specified broadcast string, since we take only 2 elements
6481 // from v4f32x_info source
6482 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
6483 "{1to2}", "", f64mem>, EVEX_V128;
6484 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
6489 // Convert Float to Signed/Unsigned Quardword with truncation
6490 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr, SDNode OpNode,
6491 SDNode OpNode128, SDNode OpNodeRnd> {
6492 let Predicates = [HasDQI] in {
6493 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
6494 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
6495 OpNodeRnd>, EVEX_V512;
6497 let Predicates = [HasDQI, HasVLX] in {
6498 // Explicitly specified broadcast string, since we take only 2 elements
6499 // from v4f32x_info source
6500 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode128,
6501 "{1to2}", "", f64mem>, EVEX_V128;
6502 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
6507 // Convert Signed/Unsigned Quardword to Float
6508 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
6509 SDNode OpNode128, SDNode OpNodeRnd> {
6510 let Predicates = [HasDQI] in {
6511 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
6512 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
6513 OpNodeRnd>, EVEX_V512;
6515 let Predicates = [HasDQI, HasVLX] in {
6516 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
6517 // memory forms of these instructions in Asm Parcer. They have the same
6518 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
6519 // due to the same reason.
6520 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode128,
6521 "{1to2}", "{x}">, EVEX_V128;
6522 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
6523 "{1to4}", "{y}">, EVEX_V256;
6525 def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
6526 (!cast<Instruction>(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>;
6527 def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
6528 (!cast<Instruction>(NAME # "Z128rm") VR128X:$dst, i128mem:$src), 0>;
6529 def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
6530 (!cast<Instruction>(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>;
6531 def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
6532 (!cast<Instruction>(NAME # "Z256rm") VR128X:$dst, i256mem:$src), 0>;
6536 defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86VSintToFP>,
6537 XS, EVEX_CD8<32, CD8VH>;
6539 defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
6541 PS, EVEX_CD8<32, CD8VF>;
6543 defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
6545 XS, EVEX_CD8<32, CD8VF>;
6547 defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint, X86cvttp2si,
6549 PD, VEX_W, EVEX_CD8<64, CD8VF>;
6551 defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
6552 X86cvttp2uiRnd>, PS,
6553 EVEX_CD8<32, CD8VF>;
6555 defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
6556 X86cvttp2ui, X86cvttp2uiRnd>, PS, VEX_W,
6557 EVEX_CD8<64, CD8VF>;
6559 defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86VUintToFP>,
6560 XS, EVEX_CD8<32, CD8VH>;
6562 defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
6563 X86VUintToFpRnd>, XD,
6564 EVEX_CD8<32, CD8VF>;
6566 defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtp2Int,
6567 X86cvtp2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
6569 defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtp2Int,
6570 X86cvtp2IntRnd>, XD, VEX_W,
6571 EVEX_CD8<64, CD8VF>;
6573 defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtp2UInt,
6575 PS, EVEX_CD8<32, CD8VF>;
6576 defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtp2UInt,
6577 X86cvtp2UIntRnd>, VEX_W,
6578 PS, EVEX_CD8<64, CD8VF>;
6580 defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtp2Int,
6581 X86cvtp2IntRnd>, VEX_W,
6582 PD, EVEX_CD8<64, CD8VF>;
6584 defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtp2Int,
6585 X86cvtp2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
6587 defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtp2UInt,
6588 X86cvtp2UIntRnd>, VEX_W,
6589 PD, EVEX_CD8<64, CD8VF>;
6591 defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtp2UInt,
6592 X86cvtp2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
6594 defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
6595 X86cvttp2siRnd>, VEX_W,
6596 PD, EVEX_CD8<64, CD8VF>;
6598 defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint, X86cvttp2si,
6599 X86cvttp2siRnd>, PD, EVEX_CD8<32, CD8VH>;
6601 defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
6602 X86cvttp2uiRnd>, VEX_W,
6603 PD, EVEX_CD8<64, CD8VF>;
6605 defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint, X86cvttp2ui,
6606 X86cvttp2uiRnd>, PD, EVEX_CD8<32, CD8VH>;
6608 defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
6609 X86VSintToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
6611 defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
6612 X86VUintToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
6614 defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp, X86VSintToFP,
6615 X86VSintToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
6617 defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp, X86VUintToFP,
6618 X86VUintToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
6620 let Predicates = [HasAVX512, NoVLX] in {
6621 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
6622 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
6623 (v16f32 (INSERT_SUBREG (IMPLICIT_DEF),
6624 VR256X:$src1, sub_ymm)))), sub_ymm)>;
6626 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
6627 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
6628 (v16f32 (INSERT_SUBREG (IMPLICIT_DEF),
6629 VR128X:$src1, sub_xmm)))), sub_xmm)>;
6631 def : Pat<(v4i32 (fp_to_uint (v4f64 VR256X:$src1))),
6632 (EXTRACT_SUBREG (v8i32 (VCVTTPD2UDQZrr
6633 (v8f64 (INSERT_SUBREG (IMPLICIT_DEF),
6634 VR256X:$src1, sub_ymm)))), sub_xmm)>;
6636 def : Pat<(v4i32 (X86cvttp2ui (v2f64 VR128X:$src))),
6637 (EXTRACT_SUBREG (v8i32 (VCVTTPD2UDQZrr
6638 (v8f64 (INSERT_SUBREG (IMPLICIT_DEF),
6639 VR128X:$src, sub_xmm)))), sub_xmm)>;
6641 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
6642 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
6643 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF),
6644 VR256X:$src1, sub_ymm)))), sub_ymm)>;
6646 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
6647 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
6648 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF),
6649 VR128X:$src1, sub_xmm)))), sub_xmm)>;
6651 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
6652 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
6653 (v8i32 (INSERT_SUBREG (IMPLICIT_DEF),
6654 VR128X:$src1, sub_xmm)))), sub_ymm)>;
6656 def : Pat<(v2f64 (X86VUintToFP (v4i32 VR128X:$src1))),
6657 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
6658 (v8i32 (INSERT_SUBREG (IMPLICIT_DEF),
6659 VR128X:$src1, sub_xmm)))), sub_xmm)>;
6662 let Predicates = [HasAVX512, HasVLX] in {
6663 let AddedComplexity = 15 in {
6664 def : Pat<(X86vzmovl (v2i64 (bitconvert
6665 (v4i32 (X86cvtp2Int (v2f64 VR128X:$src)))))),
6666 (VCVTPD2DQZ128rr VR128X:$src)>;
6667 def : Pat<(v4i32 (bitconvert (X86vzmovl (v2i64 (bitconvert
6668 (v4i32 (X86cvtp2UInt (v2f64 VR128X:$src)))))))),
6669 (VCVTPD2UDQZ128rr VR128X:$src)>;
6670 def : Pat<(X86vzmovl (v2i64 (bitconvert
6671 (v4i32 (X86cvttp2si (v2f64 VR128X:$src)))))),
6672 (VCVTTPD2DQZ128rr VR128X:$src)>;
6673 def : Pat<(v4i32 (bitconvert (X86vzmovl (v2i64 (bitconvert
6674 (v4i32 (X86cvttp2ui (v2f64 VR128X:$src)))))))),
6675 (VCVTTPD2UDQZ128rr VR128X:$src)>;
6679 let Predicates = [HasAVX512] in {
6680 def : Pat<(v8f32 (fpround (loadv8f64 addr:$src))),
6681 (VCVTPD2PSZrm addr:$src)>;
6682 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
6683 (VCVTPS2PDZrm addr:$src)>;
6686 let Predicates = [HasDQI, HasVLX] in {
6687 let AddedComplexity = 15 in {
6688 def : Pat<(X86vzmovl (v2f64 (bitconvert
6689 (v4f32 (X86VSintToFP (v2i64 VR128X:$src)))))),
6690 (VCVTQQ2PSZ128rr VR128X:$src)>;
6691 def : Pat<(X86vzmovl (v2f64 (bitconvert
6692 (v4f32 (X86VUintToFP (v2i64 VR128X:$src)))))),
6693 (VCVTUQQ2PSZ128rr VR128X:$src)>;
6697 let Predicates = [HasDQI, NoVLX] in {
6698 def : Pat<(v2i64 (fp_to_sint (v2f64 VR128X:$src1))),
6699 (EXTRACT_SUBREG (v8i64 (VCVTTPD2QQZrr
6700 (v8f64 (INSERT_SUBREG (IMPLICIT_DEF),
6701 VR128X:$src1, sub_xmm)))), sub_xmm)>;
6703 def : Pat<(v4i64 (fp_to_sint (v4f32 VR128X:$src1))),
6704 (EXTRACT_SUBREG (v8i64 (VCVTTPS2QQZrr
6705 (v8f32 (INSERT_SUBREG (IMPLICIT_DEF),
6706 VR128X:$src1, sub_xmm)))), sub_ymm)>;
6708 def : Pat<(v4i64 (fp_to_sint (v4f64 VR256X:$src1))),
6709 (EXTRACT_SUBREG (v8i64 (VCVTTPD2QQZrr
6710 (v8f64 (INSERT_SUBREG (IMPLICIT_DEF),
6711 VR256X:$src1, sub_ymm)))), sub_ymm)>;
6713 def : Pat<(v2i64 (fp_to_uint (v2f64 VR128X:$src1))),
6714 (EXTRACT_SUBREG (v8i64 (VCVTTPD2UQQZrr
6715 (v8f64 (INSERT_SUBREG (IMPLICIT_DEF),
6716 VR128X:$src1, sub_xmm)))), sub_xmm)>;
6718 def : Pat<(v4i64 (fp_to_uint (v4f32 VR128X:$src1))),
6719 (EXTRACT_SUBREG (v8i64 (VCVTTPS2UQQZrr
6720 (v8f32 (INSERT_SUBREG (IMPLICIT_DEF),
6721 VR128X:$src1, sub_xmm)))), sub_ymm)>;
6723 def : Pat<(v4i64 (fp_to_uint (v4f64 VR256X:$src1))),
6724 (EXTRACT_SUBREG (v8i64 (VCVTTPD2UQQZrr
6725 (v8f64 (INSERT_SUBREG (IMPLICIT_DEF),
6726 VR256X:$src1, sub_ymm)))), sub_ymm)>;
6728 def : Pat<(v4f32 (sint_to_fp (v4i64 VR256X:$src1))),
6729 (EXTRACT_SUBREG (v8f32 (VCVTQQ2PSZrr
6730 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF),
6731 VR256X:$src1, sub_ymm)))), sub_xmm)>;
6733 def : Pat<(v2f64 (sint_to_fp (v2i64 VR128X:$src1))),
6734 (EXTRACT_SUBREG (v8f64 (VCVTQQ2PDZrr
6735 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF),
6736 VR128X:$src1, sub_xmm)))), sub_xmm)>;
6738 def : Pat<(v4f64 (sint_to_fp (v4i64 VR256X:$src1))),
6739 (EXTRACT_SUBREG (v8f64 (VCVTQQ2PDZrr
6740 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF),
6741 VR256X:$src1, sub_ymm)))), sub_ymm)>;
6743 def : Pat<(v4f32 (uint_to_fp (v4i64 VR256X:$src1))),
6744 (EXTRACT_SUBREG (v8f32 (VCVTUQQ2PSZrr
6745 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF),
6746 VR256X:$src1, sub_ymm)))), sub_xmm)>;
6748 def : Pat<(v2f64 (uint_to_fp (v2i64 VR128X:$src1))),
6749 (EXTRACT_SUBREG (v8f64 (VCVTUQQ2PDZrr
6750 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF),
6751 VR128X:$src1, sub_xmm)))), sub_xmm)>;
6753 def : Pat<(v4f64 (uint_to_fp (v4i64 VR256X:$src1))),
6754 (EXTRACT_SUBREG (v8f64 (VCVTUQQ2PDZrr
6755 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF),
6756 VR256X:$src1, sub_ymm)))), sub_ymm)>;
6759 //===----------------------------------------------------------------------===//
6760 // Half precision conversion instructions
6761 //===----------------------------------------------------------------------===//
6762 multiclass avx512_cvtph2ps<X86VectorVTInfo _dest, X86VectorVTInfo _src,
6763 X86MemOperand x86memop, PatFrag ld_frag> {
6764 defm rr : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
6765 "vcvtph2ps", "$src", "$src",
6766 (X86cvtph2ps (_src.VT _src.RC:$src),
6767 (i32 FROUND_CURRENT))>, T8PD;
6768 defm rm : AVX512_maskable<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst), (ins x86memop:$src),
6769 "vcvtph2ps", "$src", "$src",
6770 (X86cvtph2ps (_src.VT (bitconvert (ld_frag addr:$src))),
6771 (i32 FROUND_CURRENT))>, T8PD;
6774 multiclass avx512_cvtph2ps_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
6775 defm rb : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
6776 "vcvtph2ps", "{sae}, $src", "$src, {sae}",
6777 (X86cvtph2ps (_src.VT _src.RC:$src),
6778 (i32 FROUND_NO_EXC))>, T8PD, EVEX_B;
6782 let Predicates = [HasAVX512] in {
6783 defm VCVTPH2PSZ : avx512_cvtph2ps<v16f32_info, v16i16x_info, f256mem, loadv4i64>,
6784 avx512_cvtph2ps_sae<v16f32_info, v16i16x_info>,
6785 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
6786 let Predicates = [HasVLX] in {
6787 defm VCVTPH2PSZ256 : avx512_cvtph2ps<v8f32x_info, v8i16x_info, f128mem,
6788 loadv2i64>,EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
6789 defm VCVTPH2PSZ128 : avx512_cvtph2ps<v4f32x_info, v8i16x_info, f64mem,
6790 loadv2i64>, EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
6794 multiclass avx512_cvtps2ph<X86VectorVTInfo _dest, X86VectorVTInfo _src,
6795 X86MemOperand x86memop> {
6796 defm rr : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
6797 (ins _src.RC:$src1, i32u8imm:$src2),
6798 "vcvtps2ph", "$src2, $src1", "$src1, $src2",
6799 (X86cvtps2ph (_src.VT _src.RC:$src1),
6801 NoItinerary, 0, 0, X86select>, AVX512AIi8Base;
6802 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
6803 (ins x86memop:$dst, _src.RC:$src1, i32u8imm:$src2),
6804 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6805 [(store (_dest.VT (X86cvtps2ph (_src.VT _src.RC:$src1),
6808 let hasSideEffects = 0, mayStore = 1 in
6809 def mrk : AVX512AIi8<0x1D, MRMDestMem, (outs),
6810 (ins x86memop:$dst, _dest.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2),
6811 "vcvtps2ph\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
6814 multiclass avx512_cvtps2ph_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
6815 let hasSideEffects = 0 in
6816 defm rb : AVX512_maskable_in_asm<0x1D, MRMDestReg, _dest,
6817 (outs _dest.RC:$dst),
6818 (ins _src.RC:$src1, i32u8imm:$src2),
6819 "vcvtps2ph", "$src2, {sae}, $src1", "$src1, {sae}, $src2",
6820 []>, EVEX_B, AVX512AIi8Base;
6822 let Predicates = [HasAVX512] in {
6823 defm VCVTPS2PHZ : avx512_cvtps2ph<v16i16x_info, v16f32_info, f256mem>,
6824 avx512_cvtps2ph_sae<v16i16x_info, v16f32_info>,
6825 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
6826 let Predicates = [HasVLX] in {
6827 defm VCVTPS2PHZ256 : avx512_cvtps2ph<v8i16x_info, v8f32x_info, f128mem>,
6828 EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
6829 defm VCVTPS2PHZ128 : avx512_cvtps2ph<v8i16x_info, v4f32x_info, f64mem>,
6830 EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
6834 // Patterns for matching conversions from float to half-float and vice versa.
6835 let Predicates = [HasVLX] in {
6836 // Use MXCSR.RC for rounding instead of explicitly specifying the default
6837 // rounding mode (Nearest-Even, encoded as 0). Both are equivalent in the
6838 // configurations we support (the default). However, falling back to MXCSR is
6839 // more consistent with other instructions, which are always controlled by it.
6840 // It's encoded as 0b100.
6841 def : Pat<(fp_to_f16 FR32X:$src),
6842 (i16 (EXTRACT_SUBREG (VMOVPDI2DIZrr (VCVTPS2PHZ128rr
6843 (COPY_TO_REGCLASS FR32X:$src, VR128X), 4)), sub_16bit))>;
6845 def : Pat<(f16_to_fp GR16:$src),
6846 (f32 (COPY_TO_REGCLASS (VCVTPH2PSZ128rr
6847 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128X)), FR32X)) >;
6849 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32X:$src))),
6850 (f32 (COPY_TO_REGCLASS (VCVTPH2PSZ128rr
6851 (VCVTPS2PHZ128rr (COPY_TO_REGCLASS FR32X:$src, VR128X), 4)), FR32X)) >;
6854 // Patterns for matching float to half-float conversion when AVX512 is supported
6855 // but F16C isn't. In that case we have to use 512-bit vectors.
6856 let Predicates = [HasAVX512, NoVLX, NoF16C] in {
6857 def : Pat<(fp_to_f16 FR32X:$src),
6858 (i16 (EXTRACT_SUBREG
6860 (v8i16 (EXTRACT_SUBREG
6862 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
6863 (v4f32 (COPY_TO_REGCLASS FR32X:$src, VR128X)),
6864 sub_xmm), 4), sub_xmm))), sub_16bit))>;
6866 def : Pat<(f16_to_fp GR16:$src),
6867 (f32 (COPY_TO_REGCLASS
6868 (v4f32 (EXTRACT_SUBREG
6870 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)),
6871 (v8i16 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128X)),
6872 sub_xmm)), sub_xmm)), FR32X))>;
6874 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32X:$src))),
6875 (f32 (COPY_TO_REGCLASS
6876 (v4f32 (EXTRACT_SUBREG
6878 (VCVTPS2PHZrr (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
6879 (v4f32 (COPY_TO_REGCLASS FR32X:$src, VR128X)),
6880 sub_xmm), 4)), sub_xmm)), FR32X))>;
6883 // Unordered/Ordered scalar fp compare with Sea and set EFLAGS
6884 multiclass avx512_ord_cmp_sae<bits<8> opc, X86VectorVTInfo _,
6886 def rb: AVX512<opc, MRMSrcReg, (outs), (ins _.RC:$src1, _.RC:$src2),
6887 !strconcat(OpcodeStr, "\t{{sae}, $src2, $src1|$src1, $src2, {sae}}"),
6888 [], IIC_SSE_COMIS_RR>, EVEX, EVEX_B, VEX_LIG, EVEX_V128,
6892 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
6893 defm VUCOMISSZ : avx512_ord_cmp_sae<0x2E, v4f32x_info, "vucomiss">,
6894 AVX512PSIi8Base, EVEX_CD8<32, CD8VT1>;
6895 defm VUCOMISDZ : avx512_ord_cmp_sae<0x2E, v2f64x_info, "vucomisd">,
6896 AVX512PDIi8Base, VEX_W, EVEX_CD8<64, CD8VT1>;
6897 defm VCOMISSZ : avx512_ord_cmp_sae<0x2F, v4f32x_info, "vcomiss">,
6898 AVX512PSIi8Base, EVEX_CD8<32, CD8VT1>;
6899 defm VCOMISDZ : avx512_ord_cmp_sae<0x2F, v2f64x_info, "vcomisd">,
6900 AVX512PDIi8Base, VEX_W, EVEX_CD8<64, CD8VT1>;
6903 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
6904 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
6905 "ucomiss">, PS, EVEX, VEX_LIG,
6906 EVEX_CD8<32, CD8VT1>;
6907 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
6908 "ucomisd">, PD, EVEX,
6909 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
6910 let Pattern = []<dag> in {
6911 defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
6912 "comiss">, PS, EVEX, VEX_LIG,
6913 EVEX_CD8<32, CD8VT1>;
6914 defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
6915 "comisd">, PD, EVEX,
6916 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
6918 let isCodeGenOnly = 1 in {
6919 defm Int_VUCOMISSZ : sse12_ord_cmp_int<0x2E, VR128X, X86ucomi, v4f32, ssmem,
6920 sse_load_f32, "ucomiss">, PS, EVEX, VEX_LIG,
6921 EVEX_CD8<32, CD8VT1>;
6922 defm Int_VUCOMISDZ : sse12_ord_cmp_int<0x2E, VR128X, X86ucomi, v2f64, sdmem,
6923 sse_load_f64, "ucomisd">, PD, EVEX,
6924 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
6926 defm Int_VCOMISSZ : sse12_ord_cmp_int<0x2F, VR128X, X86comi, v4f32, ssmem,
6927 sse_load_f32, "comiss">, PS, EVEX, VEX_LIG,
6928 EVEX_CD8<32, CD8VT1>;
6929 defm Int_VCOMISDZ : sse12_ord_cmp_int<0x2F, VR128X, X86comi, v2f64, sdmem,
6930 sse_load_f64, "comisd">, PD, EVEX,
6931 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
6935 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
6936 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
6937 X86VectorVTInfo _> {
6938 let Predicates = [HasAVX512], ExeDomain = _.ExeDomain in {
6939 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6940 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
6941 "$src2, $src1", "$src1, $src2",
6942 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>, EVEX_4V;
6943 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6944 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
6945 "$src2, $src1", "$src1, $src2",
6946 (OpNode (_.VT _.RC:$src1),
6947 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))))>, EVEX_4V;
6951 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86frcp14s, f32x_info>,
6952 EVEX_CD8<32, CD8VT1>, T8PD;
6953 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86frcp14s, f64x_info>,
6954 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
6955 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86frsqrt14s, f32x_info>,
6956 EVEX_CD8<32, CD8VT1>, T8PD;
6957 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86frsqrt14s, f64x_info>,
6958 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
6960 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
6961 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
6962 X86VectorVTInfo _> {
6963 let ExeDomain = _.ExeDomain in {
6964 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6965 (ins _.RC:$src), OpcodeStr, "$src", "$src",
6966 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
6967 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6968 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
6970 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
6971 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6972 (ins _.ScalarMemOp:$src), OpcodeStr,
6973 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
6975 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
6980 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6981 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
6982 EVEX_V512, EVEX_CD8<32, CD8VF>;
6983 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
6984 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
6986 // Define only if AVX512VL feature is present.
6987 let Predicates = [HasVLX] in {
6988 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
6989 OpNode, v4f32x_info>,
6990 EVEX_V128, EVEX_CD8<32, CD8VF>;
6991 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
6992 OpNode, v8f32x_info>,
6993 EVEX_V256, EVEX_CD8<32, CD8VF>;
6994 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
6995 OpNode, v2f64x_info>,
6996 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
6997 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
6998 OpNode, v4f64x_info>,
6999 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
7003 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
7004 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
7006 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
7007 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
7009 let ExeDomain = _.ExeDomain in {
7010 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
7011 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
7012 "$src2, $src1", "$src1, $src2",
7013 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
7014 (i32 FROUND_CURRENT))>;
7016 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
7017 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
7018 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
7019 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
7020 (i32 FROUND_NO_EXC))>, EVEX_B;
7022 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
7023 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
7024 "$src2, $src1", "$src1, $src2",
7025 (OpNode (_.VT _.RC:$src1),
7026 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
7027 (i32 FROUND_CURRENT))>;
7031 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
7032 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
7033 EVEX_CD8<32, CD8VT1>;
7034 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
7035 EVEX_CD8<64, CD8VT1>, VEX_W;
7038 let Predicates = [HasERI] in {
7039 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
7040 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
7043 defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds>, T8PD, EVEX_4V;
7044 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
7046 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
7048 let ExeDomain = _.ExeDomain in {
7049 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7050 (ins _.RC:$src), OpcodeStr, "$src", "$src",
7051 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
7053 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7054 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
7056 (bitconvert (_.LdFrag addr:$src))),
7057 (i32 FROUND_CURRENT))>;
7059 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7060 (ins _.ScalarMemOp:$src), OpcodeStr,
7061 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
7063 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
7064 (i32 FROUND_CURRENT))>, EVEX_B;
7067 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
7069 let ExeDomain = _.ExeDomain in
7070 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7071 (ins _.RC:$src), OpcodeStr,
7072 "{sae}, $src", "$src, {sae}",
7073 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
7076 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
7077 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
7078 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
7079 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
7080 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
7081 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
7082 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
7085 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
7087 // Define only if AVX512VL feature is present.
7088 let Predicates = [HasVLX] in {
7089 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
7090 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
7091 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
7092 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
7093 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
7094 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
7095 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
7096 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
7099 let Predicates = [HasERI] in {
7101 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
7102 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
7103 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
7105 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
7106 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
7108 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
7109 SDNode OpNodeRnd, X86VectorVTInfo _>{
7110 let ExeDomain = _.ExeDomain in
7111 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7112 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
7113 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
7114 EVEX, EVEX_B, EVEX_RC;
7117 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
7118 SDNode OpNode, X86VectorVTInfo _>{
7119 let ExeDomain = _.ExeDomain in {
7120 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7121 (ins _.RC:$src), OpcodeStr, "$src", "$src",
7122 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
7123 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7124 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
7126 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
7128 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7129 (ins _.ScalarMemOp:$src), OpcodeStr,
7130 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
7132 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
7137 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
7139 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
7141 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
7142 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
7144 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
7145 // Define only if AVX512VL feature is present.
7146 let Predicates = [HasVLX] in {
7147 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
7148 OpNode, v4f32x_info>,
7149 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
7150 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
7151 OpNode, v8f32x_info>,
7152 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
7153 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
7154 OpNode, v2f64x_info>,
7155 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
7156 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
7157 OpNode, v4f64x_info>,
7158 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
7162 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
7164 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
7165 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
7166 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
7167 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
7170 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
7171 string SUFF, SDNode OpNode, SDNode OpNodeRnd> {
7172 let ExeDomain = _.ExeDomain in {
7173 defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
7174 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
7175 "$src2, $src1", "$src1, $src2",
7176 (OpNodeRnd (_.VT _.RC:$src1),
7178 (i32 FROUND_CURRENT))>;
7179 defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
7180 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
7181 "$src2, $src1", "$src1, $src2",
7182 (OpNodeRnd (_.VT _.RC:$src1),
7183 (_.VT (scalar_to_vector
7184 (_.ScalarLdFrag addr:$src2))),
7185 (i32 FROUND_CURRENT))>;
7187 defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
7188 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
7189 "$rc, $src2, $src1", "$src1, $src2, $rc",
7190 (OpNodeRnd (_.VT _.RC:$src1),
7195 let isCodeGenOnly = 1, hasSideEffects = 0 in {
7196 def r : I<opc, MRMSrcReg, (outs _.FRC:$dst),
7197 (ins _.FRC:$src1, _.FRC:$src2),
7198 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
7201 def m : I<opc, MRMSrcMem, (outs _.FRC:$dst),
7202 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
7203 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
7207 def : Pat<(_.EltVT (OpNode _.FRC:$src)),
7208 (!cast<Instruction>(NAME#SUFF#Zr)
7209 (_.EltVT (IMPLICIT_DEF)), _.FRC:$src)>;
7211 def : Pat<(_.EltVT (OpNode (load addr:$src))),
7212 (!cast<Instruction>(NAME#SUFF#Zm)
7213 (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512, OptForSize]>;
7216 multiclass avx512_sqrt_scalar_all<bits<8> opc, string OpcodeStr> {
7217 defm SSZ : avx512_sqrt_scalar<opc, OpcodeStr#"ss", f32x_info, "SS", fsqrt,
7218 X86fsqrtRnds>, EVEX_CD8<32, CD8VT1>, EVEX_4V, XS;
7219 defm SDZ : avx512_sqrt_scalar<opc, OpcodeStr#"sd", f64x_info, "SD", fsqrt,
7220 X86fsqrtRnds>, EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, VEX_W;
7223 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
7224 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
7226 defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt">, VEX_LIG;
7228 let Predicates = [HasAVX512] in {
7229 def : Pat<(f32 (X86frsqrt FR32X:$src)),
7230 (COPY_TO_REGCLASS (VRSQRT14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>;
7231 def : Pat<(f32 (X86frsqrt (load addr:$src))),
7232 (COPY_TO_REGCLASS (VRSQRT14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
7233 Requires<[OptForSize]>;
7234 def : Pat<(f32 (X86frcp FR32X:$src)),
7235 (COPY_TO_REGCLASS (VRCP14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X )>;
7236 def : Pat<(f32 (X86frcp (load addr:$src))),
7237 (COPY_TO_REGCLASS (VRCP14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
7238 Requires<[OptForSize]>;
7242 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
7244 let ExeDomain = _.ExeDomain in {
7245 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
7246 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
7247 "$src3, $src2, $src1", "$src1, $src2, $src3",
7248 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
7249 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
7251 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
7252 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
7253 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
7254 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
7255 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
7257 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
7258 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
7260 "$src3, $src2, $src1", "$src1, $src2, $src3",
7261 (_.VT (X86RndScales (_.VT _.RC:$src1),
7262 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
7263 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
7265 let Predicates = [HasAVX512] in {
7266 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
7267 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
7268 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
7269 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
7270 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
7271 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
7272 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
7273 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
7274 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
7275 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
7276 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
7277 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
7278 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
7279 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
7280 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
7282 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
7283 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
7284 addr:$src, (i32 0x1))), _.FRC)>;
7285 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
7286 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
7287 addr:$src, (i32 0x2))), _.FRC)>;
7288 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
7289 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
7290 addr:$src, (i32 0x3))), _.FRC)>;
7291 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
7292 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
7293 addr:$src, (i32 0x4))), _.FRC)>;
7294 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
7295 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
7296 addr:$src, (i32 0xc))), _.FRC)>;
7300 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
7301 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
7303 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
7304 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
7306 //-------------------------------------------------
7307 // Integer truncate and extend operations
7308 //-------------------------------------------------
7310 multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
7311 X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,
7312 X86MemOperand x86memop> {
7313 let ExeDomain = DestInfo.ExeDomain in
7314 defm rr : AVX512_maskable<opc, MRMDestReg, DestInfo, (outs DestInfo.RC:$dst),
7315 (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",
7316 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,
7319 // for intrinsic patter match
7320 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
7321 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
7323 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
7326 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
7327 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
7328 DestInfo.ImmAllZerosV)),
7329 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
7332 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
7333 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
7334 DestInfo.RC:$src0)),
7335 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,
7336 DestInfo.KRCWM:$mask ,
7339 let mayStore = 1, mayLoad = 1, hasSideEffects = 0,
7340 ExeDomain = DestInfo.ExeDomain in {
7341 def mr : AVX512XS8I<opc, MRMDestMem, (outs),
7342 (ins x86memop:$dst, SrcInfo.RC:$src),
7343 OpcodeStr # "\t{$src, $dst|$dst, $src}",
7346 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
7347 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
7348 OpcodeStr # "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
7350 }//mayStore = 1, mayLoad = 1, hasSideEffects = 0
7353 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
7354 X86VectorVTInfo DestInfo,
7355 PatFrag truncFrag, PatFrag mtruncFrag > {
7357 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
7358 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)
7359 addr:$dst, SrcInfo.RC:$src)>;
7361 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
7362 (SrcInfo.VT SrcInfo.RC:$src)),
7363 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)
7364 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
7367 multiclass avx512_trunc<bits<8> opc, string OpcodeStr, SDNode OpNode,
7368 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
7369 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
7370 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
7371 X86MemOperand x86memopZ, PatFrag truncFrag, PatFrag mtruncFrag,
7372 Predicate prd = HasAVX512>{
7374 let Predicates = [HasVLX, prd] in {
7375 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
7376 DestInfoZ128, x86memopZ128>,
7377 avx512_trunc_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
7378 truncFrag, mtruncFrag>, EVEX_V128;
7380 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
7381 DestInfoZ256, x86memopZ256>,
7382 avx512_trunc_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
7383 truncFrag, mtruncFrag>, EVEX_V256;
7385 let Predicates = [prd] in
7386 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
7387 DestInfoZ, x86memopZ>,
7388 avx512_trunc_mr_lowering<VTSrcInfo.info512, DestInfoZ,
7389 truncFrag, mtruncFrag>, EVEX_V512;
7392 multiclass avx512_trunc_qb<bits<8> opc, string OpcodeStr, SDNode OpNode,
7393 PatFrag StoreNode, PatFrag MaskedStoreNode> {
7394 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
7395 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
7396 StoreNode, MaskedStoreNode>, EVEX_CD8<8, CD8VO>;
7399 multiclass avx512_trunc_qw<bits<8> opc, string OpcodeStr, SDNode OpNode,
7400 PatFrag StoreNode, PatFrag MaskedStoreNode> {
7401 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
7402 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
7403 StoreNode, MaskedStoreNode>, EVEX_CD8<16, CD8VQ>;
7406 multiclass avx512_trunc_qd<bits<8> opc, string OpcodeStr, SDNode OpNode,
7407 PatFrag StoreNode, PatFrag MaskedStoreNode> {
7408 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
7409 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
7410 StoreNode, MaskedStoreNode>, EVEX_CD8<32, CD8VH>;
7413 multiclass avx512_trunc_db<bits<8> opc, string OpcodeStr, SDNode OpNode,
7414 PatFrag StoreNode, PatFrag MaskedStoreNode> {
7415 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
7416 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
7417 StoreNode, MaskedStoreNode>, EVEX_CD8<8, CD8VQ>;
7420 multiclass avx512_trunc_dw<bits<8> opc, string OpcodeStr, SDNode OpNode,
7421 PatFrag StoreNode, PatFrag MaskedStoreNode> {
7422 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
7423 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
7424 StoreNode, MaskedStoreNode>, EVEX_CD8<16, CD8VH>;
7427 multiclass avx512_trunc_wb<bits<8> opc, string OpcodeStr, SDNode OpNode,
7428 PatFrag StoreNode, PatFrag MaskedStoreNode> {
7429 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i16_info,
7430 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
7431 StoreNode, MaskedStoreNode, HasBWI>, EVEX_CD8<16, CD8VH>;
7434 defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", X86vtrunc,
7435 truncstorevi8, masked_truncstorevi8>;
7436 defm VPMOVSQB : avx512_trunc_qb<0x22, "vpmovsqb", X86vtruncs,
7437 truncstore_s_vi8, masked_truncstore_s_vi8>;
7438 defm VPMOVUSQB : avx512_trunc_qb<0x12, "vpmovusqb", X86vtruncus,
7439 truncstore_us_vi8, masked_truncstore_us_vi8>;
7441 defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", X86vtrunc,
7442 truncstorevi16, masked_truncstorevi16>;
7443 defm VPMOVSQW : avx512_trunc_qw<0x24, "vpmovsqw", X86vtruncs,
7444 truncstore_s_vi16, masked_truncstore_s_vi16>;
7445 defm VPMOVUSQW : avx512_trunc_qw<0x14, "vpmovusqw", X86vtruncus,
7446 truncstore_us_vi16, masked_truncstore_us_vi16>;
7448 defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", X86vtrunc,
7449 truncstorevi32, masked_truncstorevi32>;
7450 defm VPMOVSQD : avx512_trunc_qd<0x25, "vpmovsqd", X86vtruncs,
7451 truncstore_s_vi32, masked_truncstore_s_vi32>;
7452 defm VPMOVUSQD : avx512_trunc_qd<0x15, "vpmovusqd", X86vtruncus,
7453 truncstore_us_vi32, masked_truncstore_us_vi32>;
7455 defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", X86vtrunc,
7456 truncstorevi8, masked_truncstorevi8>;
7457 defm VPMOVSDB : avx512_trunc_db<0x21, "vpmovsdb", X86vtruncs,
7458 truncstore_s_vi8, masked_truncstore_s_vi8>;
7459 defm VPMOVUSDB : avx512_trunc_db<0x11, "vpmovusdb", X86vtruncus,
7460 truncstore_us_vi8, masked_truncstore_us_vi8>;
7462 defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", X86vtrunc,
7463 truncstorevi16, masked_truncstorevi16>;
7464 defm VPMOVSDW : avx512_trunc_dw<0x23, "vpmovsdw", X86vtruncs,
7465 truncstore_s_vi16, masked_truncstore_s_vi16>;
7466 defm VPMOVUSDW : avx512_trunc_dw<0x13, "vpmovusdw", X86vtruncus,
7467 truncstore_us_vi16, masked_truncstore_us_vi16>;
7469 defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", X86vtrunc,
7470 truncstorevi8, masked_truncstorevi8>;
7471 defm VPMOVSWB : avx512_trunc_wb<0x20, "vpmovswb", X86vtruncs,
7472 truncstore_s_vi8, masked_truncstore_s_vi8>;
7473 defm VPMOVUSWB : avx512_trunc_wb<0x10, "vpmovuswb", X86vtruncus,
7474 truncstore_us_vi8, masked_truncstore_us_vi8>;
7476 let Predicates = [HasAVX512, NoVLX] in {
7477 def: Pat<(v8i16 (X86vtrunc (v8i32 VR256X:$src))),
7478 (v8i16 (EXTRACT_SUBREG
7479 (v16i16 (VPMOVDWZrr (v16i32 (INSERT_SUBREG (IMPLICIT_DEF),
7480 VR256X:$src, sub_ymm)))), sub_xmm))>;
7481 def: Pat<(v4i32 (X86vtrunc (v4i64 VR256X:$src))),
7482 (v4i32 (EXTRACT_SUBREG
7483 (v8i32 (VPMOVQDZrr (v8i64 (INSERT_SUBREG (IMPLICIT_DEF),
7484 VR256X:$src, sub_ymm)))), sub_xmm))>;
7487 let Predicates = [HasBWI, NoVLX] in {
7488 def: Pat<(v16i8 (X86vtrunc (v16i16 VR256X:$src))),
7489 (v16i8 (EXTRACT_SUBREG (VPMOVWBZrr (v32i16 (INSERT_SUBREG (IMPLICIT_DEF),
7490 VR256X:$src, sub_ymm))), sub_xmm))>;
7493 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
7494 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
7495 X86MemOperand x86memop, PatFrag LdFrag, SDPatternOperator OpNode>{
7496 let ExeDomain = DestInfo.ExeDomain in {
7497 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
7498 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
7499 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
7502 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
7503 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
7504 (DestInfo.VT (LdFrag addr:$src))>,
7509 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr,
7510 SDPatternOperator OpNode, SDPatternOperator InVecNode,
7511 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
7512 let Predicates = [HasVLX, HasBWI] in {
7513 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
7514 v16i8x_info, i64mem, LdFrag, InVecNode>,
7515 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
7517 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
7518 v16i8x_info, i128mem, LdFrag, OpNode>,
7519 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
7521 let Predicates = [HasBWI] in {
7522 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
7523 v32i8x_info, i256mem, LdFrag, OpNode>,
7524 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
7528 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr,
7529 SDPatternOperator OpNode, SDPatternOperator InVecNode,
7530 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
7531 let Predicates = [HasVLX, HasAVX512] in {
7532 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
7533 v16i8x_info, i32mem, LdFrag, InVecNode>,
7534 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
7536 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
7537 v16i8x_info, i64mem, LdFrag, OpNode>,
7538 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
7540 let Predicates = [HasAVX512] in {
7541 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
7542 v16i8x_info, i128mem, LdFrag, OpNode>,
7543 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
7547 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr,
7548 SDPatternOperator OpNode, SDPatternOperator InVecNode,
7549 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
7550 let Predicates = [HasVLX, HasAVX512] in {
7551 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
7552 v16i8x_info, i16mem, LdFrag, InVecNode>,
7553 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
7555 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
7556 v16i8x_info, i32mem, LdFrag, OpNode>,
7557 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
7559 let Predicates = [HasAVX512] in {
7560 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
7561 v16i8x_info, i64mem, LdFrag, OpNode>,
7562 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
7566 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr,
7567 SDPatternOperator OpNode, SDPatternOperator InVecNode,
7568 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
7569 let Predicates = [HasVLX, HasAVX512] in {
7570 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
7571 v8i16x_info, i64mem, LdFrag, InVecNode>,
7572 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
7574 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
7575 v8i16x_info, i128mem, LdFrag, OpNode>,
7576 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
7578 let Predicates = [HasAVX512] in {
7579 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
7580 v16i16x_info, i256mem, LdFrag, OpNode>,
7581 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
7585 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr,
7586 SDPatternOperator OpNode, SDPatternOperator InVecNode,
7587 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
7588 let Predicates = [HasVLX, HasAVX512] in {
7589 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
7590 v8i16x_info, i32mem, LdFrag, InVecNode>,
7591 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
7593 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
7594 v8i16x_info, i64mem, LdFrag, OpNode>,
7595 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
7597 let Predicates = [HasAVX512] in {
7598 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
7599 v8i16x_info, i128mem, LdFrag, OpNode>,
7600 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
7604 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr,
7605 SDPatternOperator OpNode, SDPatternOperator InVecNode,
7606 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
7608 let Predicates = [HasVLX, HasAVX512] in {
7609 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
7610 v4i32x_info, i64mem, LdFrag, InVecNode>,
7611 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
7613 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
7614 v4i32x_info, i128mem, LdFrag, OpNode>,
7615 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
7617 let Predicates = [HasAVX512] in {
7618 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
7619 v8i32x_info, i256mem, LdFrag, OpNode>,
7620 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
7624 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, zext_invec, "z">;
7625 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, zext_invec, "z">;
7626 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, zext_invec, "z">;
7627 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, zext_invec, "z">;
7628 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, zext_invec, "z">;
7629 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, zext_invec, "z">;
7631 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, sext_invec, "s">;
7632 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, sext_invec, "s">;
7633 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, sext_invec, "s">;
7634 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, sext_invec, "s">;
7635 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, sext_invec, "s">;
7636 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, sext_invec, "s">;
7638 // EXTLOAD patterns, implemented using vpmovz
7639 multiclass avx512_ext_lowering<string InstrStr, X86VectorVTInfo To,
7640 X86VectorVTInfo From, PatFrag LdFrag> {
7641 def : Pat<(To.VT (LdFrag addr:$src)),
7642 (!cast<Instruction>("VPMOVZX"#InstrStr#"rm") addr:$src)>;
7643 def : Pat<(To.VT (vselect To.KRCWM:$mask, (LdFrag addr:$src), To.RC:$src0)),
7644 (!cast<Instruction>("VPMOVZX"#InstrStr#"rmk") To.RC:$src0,
7645 To.KRC:$mask, addr:$src)>;
7646 def : Pat<(To.VT (vselect To.KRCWM:$mask, (LdFrag addr:$src),
7648 (!cast<Instruction>("VPMOVZX"#InstrStr#"rmkz") To.KRC:$mask,
7652 let Predicates = [HasVLX, HasBWI] in {
7653 defm : avx512_ext_lowering<"BWZ128", v8i16x_info, v16i8x_info, extloadvi8>;
7654 defm : avx512_ext_lowering<"BWZ256", v16i16x_info, v16i8x_info, extloadvi8>;
7656 let Predicates = [HasBWI] in {
7657 defm : avx512_ext_lowering<"BWZ", v32i16_info, v32i8x_info, extloadvi8>;
7659 let Predicates = [HasVLX, HasAVX512] in {
7660 defm : avx512_ext_lowering<"BDZ128", v4i32x_info, v16i8x_info, extloadvi8>;
7661 defm : avx512_ext_lowering<"BDZ256", v8i32x_info, v16i8x_info, extloadvi8>;
7662 defm : avx512_ext_lowering<"BQZ128", v2i64x_info, v16i8x_info, extloadvi8>;
7663 defm : avx512_ext_lowering<"BQZ256", v4i64x_info, v16i8x_info, extloadvi8>;
7664 defm : avx512_ext_lowering<"WDZ128", v4i32x_info, v8i16x_info, extloadvi16>;
7665 defm : avx512_ext_lowering<"WDZ256", v8i32x_info, v8i16x_info, extloadvi16>;
7666 defm : avx512_ext_lowering<"WQZ128", v2i64x_info, v8i16x_info, extloadvi16>;
7667 defm : avx512_ext_lowering<"WQZ256", v4i64x_info, v8i16x_info, extloadvi16>;
7668 defm : avx512_ext_lowering<"DQZ128", v2i64x_info, v4i32x_info, extloadvi32>;
7669 defm : avx512_ext_lowering<"DQZ256", v4i64x_info, v4i32x_info, extloadvi32>;
7671 let Predicates = [HasAVX512] in {
7672 defm : avx512_ext_lowering<"BDZ", v16i32_info, v16i8x_info, extloadvi8>;
7673 defm : avx512_ext_lowering<"BQZ", v8i64_info, v16i8x_info, extloadvi8>;
7674 defm : avx512_ext_lowering<"WDZ", v16i32_info, v16i16x_info, extloadvi16>;
7675 defm : avx512_ext_lowering<"WQZ", v8i64_info, v8i16x_info, extloadvi16>;
7676 defm : avx512_ext_lowering<"DQZ", v8i64_info, v8i32x_info, extloadvi32>;
7679 multiclass AVX512_pmovx_patterns<string OpcPrefix, SDNode ExtOp,
7680 SDNode InVecOp, PatFrag ExtLoad16> {
7682 let Predicates = [HasVLX, HasBWI] in {
7683 def : Pat<(v8i16 (InVecOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
7684 (!cast<I>(OpcPrefix#BWZ128rm) addr:$src)>;
7685 def : Pat<(v8i16 (InVecOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
7686 (!cast<I>(OpcPrefix#BWZ128rm) addr:$src)>;
7687 def : Pat<(v8i16 (InVecOp (v16i8 (vzmovl_v2i64 addr:$src)))),
7688 (!cast<I>(OpcPrefix#BWZ128rm) addr:$src)>;
7689 def : Pat<(v8i16 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))),
7690 (!cast<I>(OpcPrefix#BWZ128rm) addr:$src)>;
7691 def : Pat<(v8i16 (InVecOp (bc_v16i8 (loadv2i64 addr:$src)))),
7692 (!cast<I>(OpcPrefix#BWZ128rm) addr:$src)>;
7694 let Predicates = [HasVLX] in {
7695 def : Pat<(v4i32 (InVecOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
7696 (!cast<I>(OpcPrefix#BDZ128rm) addr:$src)>;
7697 def : Pat<(v4i32 (InVecOp (v16i8 (vzmovl_v4i32 addr:$src)))),
7698 (!cast<I>(OpcPrefix#BDZ128rm) addr:$src)>;
7699 def : Pat<(v4i32 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))),
7700 (!cast<I>(OpcPrefix#BDZ128rm) addr:$src)>;
7701 def : Pat<(v4i32 (InVecOp (bc_v16i8 (loadv2i64 addr:$src)))),
7702 (!cast<I>(OpcPrefix#BDZ128rm) addr:$src)>;
7704 def : Pat<(v2i64 (InVecOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))),
7705 (!cast<I>(OpcPrefix#BQZ128rm) addr:$src)>;
7706 def : Pat<(v2i64 (InVecOp (v16i8 (vzmovl_v4i32 addr:$src)))),
7707 (!cast<I>(OpcPrefix#BQZ128rm) addr:$src)>;
7708 def : Pat<(v2i64 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))),
7709 (!cast<I>(OpcPrefix#BQZ128rm) addr:$src)>;
7710 def : Pat<(v2i64 (InVecOp (bc_v16i8 (loadv2i64 addr:$src)))),
7711 (!cast<I>(OpcPrefix#BQZ128rm) addr:$src)>;
7713 def : Pat<(v4i32 (InVecOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
7714 (!cast<I>(OpcPrefix#WDZ128rm) addr:$src)>;
7715 def : Pat<(v4i32 (InVecOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
7716 (!cast<I>(OpcPrefix#WDZ128rm) addr:$src)>;
7717 def : Pat<(v4i32 (InVecOp (v8i16 (vzmovl_v2i64 addr:$src)))),
7718 (!cast<I>(OpcPrefix#WDZ128rm) addr:$src)>;
7719 def : Pat<(v4i32 (InVecOp (v8i16 (vzload_v2i64 addr:$src)))),
7720 (!cast<I>(OpcPrefix#WDZ128rm) addr:$src)>;
7721 def : Pat<(v4i32 (InVecOp (bc_v8i16 (loadv2i64 addr:$src)))),
7722 (!cast<I>(OpcPrefix#WDZ128rm) addr:$src)>;
7724 def : Pat<(v2i64 (InVecOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
7725 (!cast<I>(OpcPrefix#WQZ128rm) addr:$src)>;
7726 def : Pat<(v2i64 (InVecOp (v8i16 (vzmovl_v4i32 addr:$src)))),
7727 (!cast<I>(OpcPrefix#WQZ128rm) addr:$src)>;
7728 def : Pat<(v2i64 (InVecOp (v8i16 (vzload_v2i64 addr:$src)))),
7729 (!cast<I>(OpcPrefix#WQZ128rm) addr:$src)>;
7730 def : Pat<(v2i64 (InVecOp (bc_v8i16 (loadv2i64 addr:$src)))),
7731 (!cast<I>(OpcPrefix#WQZ128rm) addr:$src)>;
7733 def : Pat<(v2i64 (InVecOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
7734 (!cast<I>(OpcPrefix#DQZ128rm) addr:$src)>;
7735 def : Pat<(v2i64 (InVecOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
7736 (!cast<I>(OpcPrefix#DQZ128rm) addr:$src)>;
7737 def : Pat<(v2i64 (InVecOp (v4i32 (vzmovl_v2i64 addr:$src)))),
7738 (!cast<I>(OpcPrefix#DQZ128rm) addr:$src)>;
7739 def : Pat<(v2i64 (InVecOp (v4i32 (vzload_v2i64 addr:$src)))),
7740 (!cast<I>(OpcPrefix#DQZ128rm) addr:$src)>;
7741 def : Pat<(v2i64 (InVecOp (bc_v4i32 (loadv2i64 addr:$src)))),
7742 (!cast<I>(OpcPrefix#DQZ128rm) addr:$src)>;
7745 let Predicates = [HasVLX, HasBWI] in {
7746 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
7747 (!cast<I>(OpcPrefix#BWZ256rm) addr:$src)>;
7748 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
7749 (!cast<I>(OpcPrefix#BWZ256rm) addr:$src)>;
7750 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
7751 (!cast<I>(OpcPrefix#BWZ256rm) addr:$src)>;
7753 let Predicates = [HasVLX] in {
7754 def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
7755 (!cast<I>(OpcPrefix#BDZ256rm) addr:$src)>;
7756 def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
7757 (!cast<I>(OpcPrefix#BDZ256rm) addr:$src)>;
7758 def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
7759 (!cast<I>(OpcPrefix#BDZ256rm) addr:$src)>;
7760 def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
7761 (!cast<I>(OpcPrefix#BDZ256rm) addr:$src)>;
7763 def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
7764 (!cast<I>(OpcPrefix#BQZ256rm) addr:$src)>;
7765 def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
7766 (!cast<I>(OpcPrefix#BQZ256rm) addr:$src)>;
7767 def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
7768 (!cast<I>(OpcPrefix#BQZ256rm) addr:$src)>;
7769 def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
7770 (!cast<I>(OpcPrefix#BQZ256rm) addr:$src)>;
7772 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
7773 (!cast<I>(OpcPrefix#WDZ256rm) addr:$src)>;
7774 def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
7775 (!cast<I>(OpcPrefix#WDZ256rm) addr:$src)>;
7776 def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
7777 (!cast<I>(OpcPrefix#WDZ256rm) addr:$src)>;
7779 def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
7780 (!cast<I>(OpcPrefix#WQZ256rm) addr:$src)>;
7781 def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
7782 (!cast<I>(OpcPrefix#WQZ256rm) addr:$src)>;
7783 def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
7784 (!cast<I>(OpcPrefix#WQZ256rm) addr:$src)>;
7785 def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
7786 (!cast<I>(OpcPrefix#WQZ256rm) addr:$src)>;
7788 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
7789 (!cast<I>(OpcPrefix#DQZ256rm) addr:$src)>;
7790 def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
7791 (!cast<I>(OpcPrefix#DQZ256rm) addr:$src)>;
7792 def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
7793 (!cast<I>(OpcPrefix#DQZ256rm) addr:$src)>;
7796 let Predicates = [HasBWI] in {
7797 def : Pat<(v32i16 (ExtOp (bc_v32i8 (loadv4i64 addr:$src)))),
7798 (!cast<I>(OpcPrefix#BWZrm) addr:$src)>;
7800 let Predicates = [HasAVX512] in {
7801 def : Pat<(v16i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
7802 (!cast<I>(OpcPrefix#BDZrm) addr:$src)>;
7804 def : Pat<(v8i64 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
7805 (!cast<I>(OpcPrefix#BQZrm) addr:$src)>;
7806 def : Pat<(v8i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
7807 (!cast<I>(OpcPrefix#BQZrm) addr:$src)>;
7809 def : Pat<(v16i32 (ExtOp (bc_v16i16 (loadv4i64 addr:$src)))),
7810 (!cast<I>(OpcPrefix#WDZrm) addr:$src)>;
7812 def : Pat<(v8i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
7813 (!cast<I>(OpcPrefix#WQZrm) addr:$src)>;
7815 def : Pat<(v8i64 (ExtOp (bc_v8i32 (loadv4i64 addr:$src)))),
7816 (!cast<I>(OpcPrefix#DQZrm) addr:$src)>;
7820 defm : AVX512_pmovx_patterns<"VPMOVSX", X86vsext, sext_invec, extloadi32i16>;
7821 defm : AVX512_pmovx_patterns<"VPMOVZX", X86vzext, zext_invec, loadi16_anyext>;
7823 //===----------------------------------------------------------------------===//
7824 // GATHER - SCATTER Operations
7826 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
7827 X86MemOperand memop, PatFrag GatherNode> {
7828 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb",
7829 ExeDomain = _.ExeDomain in
7830 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
7831 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
7832 !strconcat(OpcodeStr#_.Suffix,
7833 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
7834 [(set _.RC:$dst, _.KRCWM:$mask_wb,
7835 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
7836 vectoraddr:$src2))]>, EVEX, EVEX_K,
7837 EVEX_CD8<_.EltSize, CD8VT1>;
7840 multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
7841 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
7842 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512,
7843 vy512mem, mgatherv8i32>, EVEX_V512, VEX_W;
7844 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info512,
7845 vz512mem, mgatherv8i64>, EVEX_V512, VEX_W;
7846 let Predicates = [HasVLX] in {
7847 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
7848 vx256xmem, mgatherv4i32>, EVEX_V256, VEX_W;
7849 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info256,
7850 vy256xmem, mgatherv4i64>, EVEX_V256, VEX_W;
7851 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
7852 vx128xmem, mgatherv4i32>, EVEX_V128, VEX_W;
7853 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
7854 vx128xmem, mgatherv2i64>, EVEX_V128, VEX_W;
7858 multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
7859 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
7860 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512, vz512mem,
7861 mgatherv16i32>, EVEX_V512;
7862 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info256, vz256xmem,
7863 mgatherv8i64>, EVEX_V512;
7864 let Predicates = [HasVLX] in {
7865 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
7866 vy256xmem, mgatherv8i32>, EVEX_V256;
7867 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info128,
7868 vy128xmem, mgatherv4i64>, EVEX_V256;
7869 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
7870 vx128xmem, mgatherv4i32>, EVEX_V128;
7871 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
7872 vx64xmem, mgatherv2i64>, EVEX_V128;
7877 defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">,
7878 avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">;
7880 defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">,
7881 avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">;
7883 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
7884 X86MemOperand memop, PatFrag ScatterNode> {
7886 let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in
7888 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
7889 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
7890 !strconcat(OpcodeStr#_.Suffix,
7891 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
7892 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
7893 _.KRCWM:$mask, vectoraddr:$dst))]>,
7894 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
7897 multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
7898 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
7899 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512,
7900 vy512mem, mscatterv8i32>, EVEX_V512, VEX_W;
7901 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info512,
7902 vz512mem, mscatterv8i64>, EVEX_V512, VEX_W;
7903 let Predicates = [HasVLX] in {
7904 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
7905 vx256xmem, mscatterv4i32>, EVEX_V256, VEX_W;
7906 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info256,
7907 vy256xmem, mscatterv4i64>, EVEX_V256, VEX_W;
7908 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
7909 vx128xmem, mscatterv4i32>, EVEX_V128, VEX_W;
7910 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
7911 vx128xmem, mscatterv2i64>, EVEX_V128, VEX_W;
7915 multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
7916 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
7917 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512, vz512mem,
7918 mscatterv16i32>, EVEX_V512;
7919 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info256, vz256xmem,
7920 mscatterv8i64>, EVEX_V512;
7921 let Predicates = [HasVLX] in {
7922 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
7923 vy256xmem, mscatterv8i32>, EVEX_V256;
7924 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
7925 vy128xmem, mscatterv4i64>, EVEX_V256;
7926 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
7927 vx128xmem, mscatterv4i32>, EVEX_V128;
7928 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
7929 vx64xmem, mscatterv2i64>, EVEX_V128;
7933 defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">,
7934 avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">;
7936 defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">,
7937 avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">;
7940 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
7941 RegisterClass KRC, X86MemOperand memop> {
7942 let Predicates = [HasPFI], hasSideEffects = 1 in
7943 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
7944 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
7948 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
7949 VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
7951 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
7952 VK8WM, vz256xmem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
7954 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
7955 VK8WM, vy512mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
7957 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
7958 VK8WM, vz512mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
7960 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
7961 VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
7963 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
7964 VK8WM, vz256xmem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
7966 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
7967 VK8WM, vy512mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
7969 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
7970 VK8WM, vz512mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
7972 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
7973 VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
7975 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
7976 VK8WM, vz256xmem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
7978 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
7979 VK8WM, vy512mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
7981 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
7982 VK8WM, vz512mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
7984 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
7985 VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
7987 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
7988 VK8WM, vz256xmem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
7990 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
7991 VK8WM, vy512mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
7993 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
7994 VK8WM, vz512mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
7996 // Helper fragments to match sext vXi1 to vXiY.
7997 def v64i1sextv64i8 : PatLeaf<(v64i8
8000 (bc_v64i8 (v16i32 immAllZerosV)),
8002 def v32i1sextv32i16 : PatLeaf<(v32i16 (X86vsrai VR512:$src, (i8 15)))>;
8003 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
8004 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
8006 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
8007 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
8008 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
8009 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
8012 // Use 512bit version to implement 128/256 bit in case NoVLX.
8013 multiclass avx512_convert_mask_to_vector_lowering<X86VectorVTInfo X86Info,
8014 X86VectorVTInfo _> {
8016 def : Pat<(X86Info.VT (X86vsext (X86Info.KVT X86Info.KRC:$src))),
8017 (X86Info.VT (EXTRACT_SUBREG
8018 (_.VT (!cast<Instruction>(NAME#"Zrr")
8019 (_.KVT (COPY_TO_REGCLASS X86Info.KRC:$src,_.KRC)))),
8020 X86Info.SubRegIdx))>;
8023 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
8024 string OpcodeStr, Predicate prd> {
8025 let Predicates = [prd] in
8026 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
8028 let Predicates = [prd, HasVLX] in {
8029 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
8030 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
8032 let Predicates = [prd, NoVLX] in {
8033 defm Z256_Alt : avx512_convert_mask_to_vector_lowering<VTInfo.info256,VTInfo.info512>;
8034 defm Z128_Alt : avx512_convert_mask_to_vector_lowering<VTInfo.info128,VTInfo.info512>;
8039 defm VPMOVM2B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, "vpmovm2" , HasBWI>;
8040 defm VPMOVM2W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, "vpmovm2", HasBWI> , VEX_W;
8041 defm VPMOVM2D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, "vpmovm2", HasDQI>;
8042 defm VPMOVM2Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, "vpmovm2", HasDQI> , VEX_W;
8044 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
8045 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
8046 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8047 [(set _.KRC:$dst, (X86cvt2mask (_.VT _.RC:$src)))]>, EVEX;
8050 // Use 512bit version to implement 128/256 bit in case NoVLX.
8051 multiclass convert_vector_to_mask_lowering<X86VectorVTInfo ExtendInfo,
8052 X86VectorVTInfo _> {
8054 def : Pat<(_.KVT (X86cvt2mask (_.VT _.RC:$src))),
8055 (_.KVT (COPY_TO_REGCLASS
8056 (!cast<Instruction>(NAME#"Zrr")
8057 (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)),
8058 _.RC:$src, _.SubRegIdx)),
8062 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
8063 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
8064 let Predicates = [prd] in
8065 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
8068 let Predicates = [prd, HasVLX] in {
8069 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
8071 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
8074 let Predicates = [prd, NoVLX] in {
8075 defm Z256_Alt : convert_vector_to_mask_lowering<VTInfo.info512, VTInfo.info256>;
8076 defm Z128_Alt : convert_vector_to_mask_lowering<VTInfo.info512, VTInfo.info128>;
8080 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
8081 avx512vl_i8_info, HasBWI>;
8082 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
8083 avx512vl_i16_info, HasBWI>, VEX_W;
8084 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
8085 avx512vl_i32_info, HasDQI>;
8086 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
8087 avx512vl_i64_info, HasDQI>, VEX_W;
8089 //===----------------------------------------------------------------------===//
8090 // AVX-512 - COMPRESS and EXPAND
8093 multiclass compress_by_vec_width_common<bits<8> opc, X86VectorVTInfo _,
8095 defm rr : AVX512_maskable<opc, MRMDestReg, _, (outs _.RC:$dst),
8096 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
8097 (_.VT (X86compress _.RC:$src1))>, AVX5128IBase;
8099 let mayStore = 1, hasSideEffects = 0 in
8100 def mr : AVX5128I<opc, MRMDestMem, (outs),
8101 (ins _.MemOp:$dst, _.RC:$src),
8102 OpcodeStr # "\t{$src, $dst|$dst, $src}",
8103 []>, EVEX_CD8<_.EltSize, CD8VT1>;
8105 def mrk : AVX5128I<opc, MRMDestMem, (outs),
8106 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
8107 OpcodeStr # "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
8109 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
8112 multiclass compress_by_vec_width_lowering<X86VectorVTInfo _ > {
8114 def : Pat<(X86mCompressingStore addr:$dst, _.KRCWM:$mask,
8116 (!cast<Instruction>(NAME#_.ZSuffix##mrk)
8117 addr:$dst, _.KRCWM:$mask, _.RC:$src)>;
8120 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
8121 AVX512VLVectorVTInfo VTInfo> {
8122 defm Z : compress_by_vec_width_common<opc, VTInfo.info512, OpcodeStr>,
8123 compress_by_vec_width_lowering<VTInfo.info512>, EVEX_V512;
8125 let Predicates = [HasVLX] in {
8126 defm Z256 : compress_by_vec_width_common<opc, VTInfo.info256, OpcodeStr>,
8127 compress_by_vec_width_lowering<VTInfo.info256>, EVEX_V256;
8128 defm Z128 : compress_by_vec_width_common<opc, VTInfo.info128, OpcodeStr>,
8129 compress_by_vec_width_lowering<VTInfo.info128>, EVEX_V128;
8133 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
8135 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
8137 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
8139 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
8143 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
8145 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
8146 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
8147 (_.VT (X86expand _.RC:$src1))>, AVX5128IBase;
8149 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
8150 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
8151 (_.VT (X86expand (_.VT (bitconvert
8152 (_.LdFrag addr:$src1)))))>,
8153 AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>;
8156 multiclass expand_by_vec_width_lowering<X86VectorVTInfo _ > {
8158 def : Pat<(_.VT (X86mExpandingLoad addr:$src, _.KRCWM:$mask, undef)),
8159 (!cast<Instruction>(NAME#_.ZSuffix##rmkz)
8160 _.KRCWM:$mask, addr:$src)>;
8162 def : Pat<(_.VT (X86mExpandingLoad addr:$src, _.KRCWM:$mask,
8163 (_.VT _.RC:$src0))),
8164 (!cast<Instruction>(NAME#_.ZSuffix##rmk)
8165 _.RC:$src0, _.KRCWM:$mask, addr:$src)>;
8168 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
8169 AVX512VLVectorVTInfo VTInfo> {
8170 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>,
8171 expand_by_vec_width_lowering<VTInfo.info512>, EVEX_V512;
8173 let Predicates = [HasVLX] in {
8174 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>,
8175 expand_by_vec_width_lowering<VTInfo.info256>, EVEX_V256;
8176 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>,
8177 expand_by_vec_width_lowering<VTInfo.info128>, EVEX_V128;
8181 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
8183 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
8185 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
8187 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
8190 //handle instruction reg_vec1 = op(reg_vec,imm)
8192 // op(broadcast(eltVt),imm)
8193 //all instruction created with FROUND_CURRENT
8194 multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
8196 let ExeDomain = _.ExeDomain in {
8197 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
8198 (ins _.RC:$src1, i32u8imm:$src2),
8199 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
8200 (OpNode (_.VT _.RC:$src1),
8202 (i32 FROUND_CURRENT))>;
8203 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
8204 (ins _.MemOp:$src1, i32u8imm:$src2),
8205 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
8206 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
8208 (i32 FROUND_CURRENT))>;
8209 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
8210 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
8211 OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
8212 "${src1}"##_.BroadcastStr##", $src2",
8213 (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
8215 (i32 FROUND_CURRENT))>, EVEX_B;
8219 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
8220 multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
8221 SDNode OpNode, X86VectorVTInfo _>{
8222 let ExeDomain = _.ExeDomain in
8223 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
8224 (ins _.RC:$src1, i32u8imm:$src2),
8225 OpcodeStr##_.Suffix, "$src2, {sae}, $src1",
8226 "$src1, {sae}, $src2",
8227 (OpNode (_.VT _.RC:$src1),
8229 (i32 FROUND_NO_EXC))>, EVEX_B;
8232 multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
8233 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
8234 let Predicates = [prd] in {
8235 defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
8236 avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
8239 let Predicates = [prd, HasVLX] in {
8240 defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
8242 defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
8247 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
8248 // op(reg_vec2,mem_vec,imm)
8249 // op(reg_vec2,broadcast(eltVt),imm)
8250 //all instruction created with FROUND_CURRENT
8251 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
8253 let ExeDomain = _.ExeDomain in {
8254 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
8255 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
8256 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
8257 (OpNode (_.VT _.RC:$src1),
8260 (i32 FROUND_CURRENT))>;
8261 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
8262 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
8263 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
8264 (OpNode (_.VT _.RC:$src1),
8265 (_.VT (bitconvert (_.LdFrag addr:$src2))),
8267 (i32 FROUND_CURRENT))>;
8268 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
8269 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
8270 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
8271 "$src1, ${src2}"##_.BroadcastStr##", $src3",
8272 (OpNode (_.VT _.RC:$src1),
8273 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
8275 (i32 FROUND_CURRENT))>, EVEX_B;
8279 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
8280 // op(reg_vec2,mem_vec,imm)
8281 multiclass avx512_3Op_rm_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
8282 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo>{
8283 let ExeDomain = DestInfo.ExeDomain in {
8284 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
8285 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
8286 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
8287 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
8288 (SrcInfo.VT SrcInfo.RC:$src2),
8290 defm rmi : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
8291 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
8292 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
8293 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
8294 (SrcInfo.VT (bitconvert
8295 (SrcInfo.LdFrag addr:$src2))),
8300 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
8301 // op(reg_vec2,mem_vec,imm)
8302 // op(reg_vec2,broadcast(eltVt),imm)
8303 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
8305 avx512_3Op_rm_imm8<opc, OpcodeStr, OpNode, _, _>{
8307 let ExeDomain = _.ExeDomain in
8308 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
8309 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
8310 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
8311 "$src1, ${src2}"##_.BroadcastStr##", $src3",
8312 (OpNode (_.VT _.RC:$src1),
8313 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
8314 (i8 imm:$src3))>, EVEX_B;
8317 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
8318 // op(reg_vec2,mem_scalar,imm)
8319 //all instruction created with FROUND_CURRENT
8320 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
8321 X86VectorVTInfo _> {
8322 let ExeDomain = _.ExeDomain in {
8323 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
8324 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
8325 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
8326 (OpNode (_.VT _.RC:$src1),
8329 (i32 FROUND_CURRENT))>;
8330 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
8331 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
8332 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
8333 (OpNode (_.VT _.RC:$src1),
8334 (_.VT (scalar_to_vector
8335 (_.ScalarLdFrag addr:$src2))),
8337 (i32 FROUND_CURRENT))>;
8341 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
8342 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
8343 SDNode OpNode, X86VectorVTInfo _>{
8344 let ExeDomain = _.ExeDomain in
8345 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
8346 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
8347 OpcodeStr, "$src3, {sae}, $src2, $src1",
8348 "$src1, $src2, {sae}, $src3",
8349 (OpNode (_.VT _.RC:$src1),
8352 (i32 FROUND_NO_EXC))>, EVEX_B;
8354 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
8355 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
8356 SDNode OpNode, X86VectorVTInfo _> {
8357 let ExeDomain = _.ExeDomain in
8358 defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
8359 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
8360 OpcodeStr, "$src3, {sae}, $src2, $src1",
8361 "$src1, $src2, {sae}, $src3",
8362 (OpNode (_.VT _.RC:$src1),
8365 (i32 FROUND_NO_EXC))>, EVEX_B;
8368 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
8369 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
8370 let Predicates = [prd] in {
8371 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
8372 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
8376 let Predicates = [prd, HasVLX] in {
8377 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
8379 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
8384 multiclass avx512_common_3Op_rm_imm8<bits<8> opc, SDNode OpNode, string OpStr,
8385 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo>{
8386 let Predicates = [HasBWI] in {
8387 defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info512,
8388 SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX_4V;
8390 let Predicates = [HasBWI, HasVLX] in {
8391 defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info128,
8392 SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX_4V;
8393 defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info256,
8394 SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX_4V;
8398 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
8399 bits<8> opc, SDNode OpNode>{
8400 let Predicates = [HasAVX512] in {
8401 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
8403 let Predicates = [HasAVX512, HasVLX] in {
8404 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
8405 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
8409 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
8410 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
8411 let Predicates = [prd] in {
8412 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
8413 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
8417 multiclass avx512_common_unary_fp_sae_packed_imm_all<string OpcodeStr,
8418 bits<8> opcPs, bits<8> opcPd, SDNode OpNode, Predicate prd>{
8419 defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info,
8420 opcPs, OpNode, prd>, EVEX_CD8<32, CD8VF>;
8421 defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info,
8422 opcPd, OpNode, prd>, EVEX_CD8<64, CD8VF>, VEX_W;
8426 defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56,
8427 X86VReduce, HasDQI>, AVX512AIi8Base, EVEX;
8428 defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09,
8429 X86VRndScale, HasAVX512>, AVX512AIi8Base, EVEX;
8430 defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26,
8431 X86VGetMant, HasAVX512>, AVX512AIi8Base, EVEX;
8434 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
8435 0x50, X86VRange, HasDQI>,
8436 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
8437 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
8438 0x50, X86VRange, HasDQI>,
8439 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
8441 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
8442 0x51, X86VRange, HasDQI>,
8443 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
8444 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
8445 0x51, X86VRange, HasDQI>,
8446 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
8448 defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
8449 0x57, X86Reduces, HasDQI>,
8450 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
8451 defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
8452 0x57, X86Reduces, HasDQI>,
8453 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
8455 defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info,
8456 0x27, X86GetMants, HasAVX512>,
8457 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
8458 defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info,
8459 0x27, X86GetMants, HasAVX512>,
8460 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
8462 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
8463 bits<8> opc, SDNode OpNode = X86Shuf128>{
8464 let Predicates = [HasAVX512] in {
8465 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
8468 let Predicates = [HasAVX512, HasVLX] in {
8469 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
8472 let Predicates = [HasAVX512] in {
8473 def : Pat<(v16f32 (ffloor VR512:$src)),
8474 (VRNDSCALEPSZrri VR512:$src, (i32 0x1))>;
8475 def : Pat<(v16f32 (fnearbyint VR512:$src)),
8476 (VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;
8477 def : Pat<(v16f32 (fceil VR512:$src)),
8478 (VRNDSCALEPSZrri VR512:$src, (i32 0x2))>;
8479 def : Pat<(v16f32 (frint VR512:$src)),
8480 (VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;
8481 def : Pat<(v16f32 (ftrunc VR512:$src)),
8482 (VRNDSCALEPSZrri VR512:$src, (i32 0x3))>;
8484 def : Pat<(v8f64 (ffloor VR512:$src)),
8485 (VRNDSCALEPDZrri VR512:$src, (i32 0x1))>;
8486 def : Pat<(v8f64 (fnearbyint VR512:$src)),
8487 (VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;
8488 def : Pat<(v8f64 (fceil VR512:$src)),
8489 (VRNDSCALEPDZrri VR512:$src, (i32 0x2))>;
8490 def : Pat<(v8f64 (frint VR512:$src)),
8491 (VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;
8492 def : Pat<(v8f64 (ftrunc VR512:$src)),
8493 (VRNDSCALEPDZrri VR512:$src, (i32 0x3))>;
8496 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
8497 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
8498 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
8499 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
8500 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
8501 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
8502 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
8503 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
8505 let Predicates = [HasAVX512] in {
8506 // Provide fallback in case the load node that is used in the broadcast
8507 // patterns above is used by additional users, which prevents the pattern
8509 def : Pat<(v8f64 (X86SubVBroadcast (v2f64 VR128X:$src))),
8510 (VSHUFF64X2Zrri (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
8511 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
8513 def : Pat<(v8i64 (X86SubVBroadcast (v2i64 VR128X:$src))),
8514 (VSHUFI64X2Zrri (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
8515 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
8518 def : Pat<(v16f32 (X86SubVBroadcast (v4f32 VR128X:$src))),
8519 (VSHUFF32X4Zrri (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
8520 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
8522 def : Pat<(v16i32 (X86SubVBroadcast (v4i32 VR128X:$src))),
8523 (VSHUFI32X4Zrri (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
8524 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
8527 def : Pat<(v32i16 (X86SubVBroadcast (v8i16 VR128X:$src))),
8528 (VSHUFI32X4Zrri (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
8529 (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
8532 def : Pat<(v64i8 (X86SubVBroadcast (v16i8 VR128X:$src))),
8533 (VSHUFI32X4Zrri (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
8534 (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
8538 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I> {
8539 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
8540 AVX512AIi8Base, EVEX_4V;
8543 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info>,
8544 EVEX_CD8<32, CD8VF>;
8545 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info>,
8546 EVEX_CD8<64, CD8VF>, VEX_W;
8548 multiclass avx512_vpalignr_lowering<X86VectorVTInfo _ , list<Predicate> p>{
8549 let Predicates = p in
8550 def NAME#_.VTName#rri:
8551 Pat<(_.VT (X86PAlignr _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
8552 (!cast<Instruction>(NAME#_.ZSuffix#rri)
8553 _.RC:$src1, _.RC:$src2, imm:$imm)>;
8556 multiclass avx512_vpalignr_lowering_common<AVX512VLVectorVTInfo _>:
8557 avx512_vpalignr_lowering<_.info512, [HasBWI]>,
8558 avx512_vpalignr_lowering<_.info128, [HasBWI, HasVLX]>,
8559 avx512_vpalignr_lowering<_.info256, [HasBWI, HasVLX]>;
8561 defm VPALIGNR: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" ,
8562 avx512vl_i8_info, avx512vl_i8_info>,
8563 avx512_vpalignr_lowering_common<avx512vl_i16_info>,
8564 avx512_vpalignr_lowering_common<avx512vl_i32_info>,
8565 avx512_vpalignr_lowering_common<avx512vl_f32_info>,
8566 avx512_vpalignr_lowering_common<avx512vl_i64_info>,
8567 avx512_vpalignr_lowering_common<avx512vl_f64_info>,
8570 defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" ,
8571 avx512vl_i16_info, avx512vl_i8_info>, EVEX_CD8<8, CD8VF>;
8573 multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
8574 X86VectorVTInfo _> {
8575 let ExeDomain = _.ExeDomain in {
8576 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
8577 (ins _.RC:$src1), OpcodeStr,
8579 (_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
8581 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
8582 (ins _.MemOp:$src1), OpcodeStr,
8584 (_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
8585 EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
8589 multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
8590 X86VectorVTInfo _> :
8591 avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
8592 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
8593 (ins _.ScalarMemOp:$src1), OpcodeStr,
8594 "${src1}"##_.BroadcastStr,
8595 "${src1}"##_.BroadcastStr,
8596 (_.VT (OpNode (X86VBroadcast
8597 (_.ScalarLdFrag addr:$src1))))>,
8598 EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
8601 multiclass avx512_unary_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
8602 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
8603 let Predicates = [prd] in
8604 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
8606 let Predicates = [prd, HasVLX] in {
8607 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
8609 defm Z128 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info128>,
8614 multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
8615 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
8616 let Predicates = [prd] in
8617 defm Z : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
8620 let Predicates = [prd, HasVLX] in {
8621 defm Z256 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
8623 defm Z128 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
8628 multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
8629 SDNode OpNode, Predicate prd> {
8630 defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr#"q", OpNode, avx512vl_i64_info,
8632 defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr#"d", OpNode, avx512vl_i32_info,
8636 multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
8637 SDNode OpNode, Predicate prd> {
8638 defm W : avx512_unary_rm_vl<opc_w, OpcodeStr#"w", OpNode, avx512vl_i16_info, prd>;
8639 defm B : avx512_unary_rm_vl<opc_b, OpcodeStr#"b", OpNode, avx512vl_i8_info, prd>;
8642 multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
8643 bits<8> opc_d, bits<8> opc_q,
8644 string OpcodeStr, SDNode OpNode> {
8645 defm NAME : avx512_unary_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
8647 avx512_unary_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
8651 defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", abs>;
8653 // VPABS: Use 512bit version to implement 128/256 bit in case NoVLX.
8654 let Predicates = [HasAVX512, NoVLX] in {
8655 def : Pat<(v4i64 (abs VR256X:$src)),
8658 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)),
8660 def : Pat<(v2i64 (abs VR128X:$src)),
8663 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm)),
8667 multiclass avx512_ctlz<bits<8> opc, string OpcodeStr, Predicate prd>{
8669 defm NAME : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr, ctlz, prd>;
8672 defm VPLZCNT : avx512_ctlz<0x44, "vplzcnt", HasCDI>;
8673 defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, HasCDI>;
8675 // VPLZCNT: Use 512bit version to implement 128/256 bit in case NoVLX.
8676 let Predicates = [HasCDI, NoVLX] in {
8677 def : Pat<(v4i64 (ctlz VR256X:$src)),
8680 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)),
8682 def : Pat<(v2i64 (ctlz VR128X:$src)),
8685 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm)),
8688 def : Pat<(v8i32 (ctlz VR256X:$src)),
8691 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)),
8693 def : Pat<(v4i32 (ctlz VR128X:$src)),
8696 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm)),
8700 //===---------------------------------------------------------------------===//
8701 // Counts number of ones - VPOPCNTD and VPOPCNTQ
8702 //===---------------------------------------------------------------------===//
8704 multiclass avx512_unary_rmb_popcnt<bits<8> opc, string OpcodeStr, X86VectorVTInfo VTInfo> {
8705 let Predicates = [HasVPOPCNTDQ] in
8706 defm Z : avx512_unary_rmb<opc, OpcodeStr, ctpop, VTInfo>, EVEX_V512;
8709 // Use 512bit version to implement 128/256 bit.
8710 multiclass avx512_unary_lowering<SDNode OpNode, AVX512VLVectorVTInfo _, Predicate prd> {
8711 let Predicates = [prd] in {
8712 def Z256_Alt : Pat<(_.info256.VT(OpNode _.info256.RC:$src1)),
8714 (!cast<Instruction>(NAME # "Zrr")
8715 (INSERT_SUBREG(_.info512.VT(IMPLICIT_DEF)),
8717 _.info256.SubRegIdx)),
8718 _.info256.SubRegIdx)>;
8720 def Z128_Alt : Pat<(_.info128.VT(OpNode _.info128.RC:$src1)),
8722 (!cast<Instruction>(NAME # "Zrr")
8723 (INSERT_SUBREG(_.info512.VT(IMPLICIT_DEF)),
8725 _.info128.SubRegIdx)),
8726 _.info128.SubRegIdx)>;
8730 defm VPOPCNTD : avx512_unary_rmb_popcnt<0x55, "vpopcntd", v16i32_info>,
8731 avx512_unary_lowering<ctpop, avx512vl_i32_info, HasVPOPCNTDQ>;
8732 defm VPOPCNTQ : avx512_unary_rmb_popcnt<0x55, "vpopcntq", v8i64_info>,
8733 avx512_unary_lowering<ctpop, avx512vl_i64_info, HasVPOPCNTDQ>, VEX_W;
8735 //===---------------------------------------------------------------------===//
8736 // Replicate Single FP - MOVSHDUP and MOVSLDUP
8737 //===---------------------------------------------------------------------===//
8738 multiclass avx512_replicate<bits<8> opc, string OpcodeStr, SDNode OpNode>{
8739 defm NAME: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_f32_info,
8743 defm VMOVSHDUP : avx512_replicate<0x16, "vmovshdup", X86Movshdup>;
8744 defm VMOVSLDUP : avx512_replicate<0x12, "vmovsldup", X86Movsldup>;
8746 //===----------------------------------------------------------------------===//
8747 // AVX-512 - MOVDDUP
8748 //===----------------------------------------------------------------------===//
8750 multiclass avx512_movddup_128<bits<8> opc, string OpcodeStr, SDNode OpNode,
8751 X86VectorVTInfo _> {
8752 let ExeDomain = _.ExeDomain in {
8753 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
8754 (ins _.RC:$src), OpcodeStr, "$src", "$src",
8755 (_.VT (OpNode (_.VT _.RC:$src)))>, EVEX;
8756 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
8757 (ins _.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
8758 (_.VT (OpNode (_.VT (scalar_to_vector
8759 (_.ScalarLdFrag addr:$src)))))>,
8760 EVEX, EVEX_CD8<_.EltSize, CD8VH>;
8764 multiclass avx512_movddup_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
8765 AVX512VLVectorVTInfo VTInfo> {
8767 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
8769 let Predicates = [HasAVX512, HasVLX] in {
8770 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
8772 defm Z128 : avx512_movddup_128<opc, OpcodeStr, OpNode, VTInfo.info128>,
8777 multiclass avx512_movddup<bits<8> opc, string OpcodeStr, SDNode OpNode>{
8778 defm NAME: avx512_movddup_common<opc, OpcodeStr, OpNode,
8779 avx512vl_f64_info>, XD, VEX_W;
8782 defm VMOVDDUP : avx512_movddup<0x12, "vmovddup", X86Movddup>;
8784 let Predicates = [HasVLX] in {
8785 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
8786 (VMOVDDUPZ128rm addr:$src)>;
8787 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
8788 (VMOVDDUPZ128rm addr:$src)>;
8789 def : Pat<(v2f64 (X86VBroadcast f64:$src)),
8790 (VMOVDDUPZ128rr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
8792 def : Pat<(vselect (v2i1 VK2WM:$mask), (X86Movddup (loadv2f64 addr:$src)),
8793 (v2f64 VR128X:$src0)),
8794 (VMOVDDUPZ128rmk VR128X:$src0, VK2WM:$mask, addr:$src)>;
8795 def : Pat<(vselect (v2i1 VK2WM:$mask), (X86Movddup (loadv2f64 addr:$src)),
8796 (bitconvert (v4i32 immAllZerosV))),
8797 (VMOVDDUPZ128rmkz VK2WM:$mask, addr:$src)>;
8799 def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast f64:$src)),
8800 (v2f64 VR128X:$src0)),
8801 (VMOVDDUPZ128rrk VR128X:$src0, VK2WM:$mask,
8802 (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
8803 def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast f64:$src)),
8804 (bitconvert (v4i32 immAllZerosV))),
8805 (VMOVDDUPZ128rrkz VK2WM:$mask, (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
8807 def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast (loadf64 addr:$src))),
8808 (v2f64 VR128X:$src0)),
8809 (VMOVDDUPZ128rmk VR128X:$src0, VK2WM:$mask, addr:$src)>;
8810 def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast (loadf64 addr:$src))),
8811 (bitconvert (v4i32 immAllZerosV))),
8812 (VMOVDDUPZ128rmkz VK2WM:$mask, addr:$src)>;
8815 //===----------------------------------------------------------------------===//
8816 // AVX-512 - Unpack Instructions
8817 //===----------------------------------------------------------------------===//
8818 defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh, HasAVX512,
8820 defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl, HasAVX512,
8823 defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl,
8824 SSE_INTALU_ITINS_P, HasBWI>;
8825 defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh,
8826 SSE_INTALU_ITINS_P, HasBWI>;
8827 defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl,
8828 SSE_INTALU_ITINS_P, HasBWI>;
8829 defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh,
8830 SSE_INTALU_ITINS_P, HasBWI>;
8832 defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl,
8833 SSE_INTALU_ITINS_P, HasAVX512>;
8834 defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh,
8835 SSE_INTALU_ITINS_P, HasAVX512>;
8836 defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl,
8837 SSE_INTALU_ITINS_P, HasAVX512>;
8838 defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh,
8839 SSE_INTALU_ITINS_P, HasAVX512>;
8841 //===----------------------------------------------------------------------===//
8842 // AVX-512 - Extract & Insert Integer Instructions
8843 //===----------------------------------------------------------------------===//
8845 multiclass avx512_extract_elt_bw_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
8846 X86VectorVTInfo _> {
8847 def mr : AVX512Ii8<opc, MRMDestMem, (outs),
8848 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
8849 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8850 [(store (_.EltVT (trunc (assertzext (OpNode (_.VT _.RC:$src1),
8853 EVEX, EVEX_CD8<_.EltSize, CD8VT1>;
8856 multiclass avx512_extract_elt_b<string OpcodeStr, X86VectorVTInfo _> {
8857 let Predicates = [HasBWI] in {
8858 def rr : AVX512Ii8<0x14, MRMDestReg, (outs GR32orGR64:$dst),
8859 (ins _.RC:$src1, u8imm:$src2),
8860 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8861 [(set GR32orGR64:$dst,
8862 (X86pextrb (_.VT _.RC:$src1), imm:$src2))]>,
8865 defm NAME : avx512_extract_elt_bw_m<0x14, OpcodeStr, X86pextrb, _>, TAPD;
8869 multiclass avx512_extract_elt_w<string OpcodeStr, X86VectorVTInfo _> {
8870 let Predicates = [HasBWI] in {
8871 def rr : AVX512Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst),
8872 (ins _.RC:$src1, u8imm:$src2),
8873 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8874 [(set GR32orGR64:$dst,
8875 (X86pextrw (_.VT _.RC:$src1), imm:$src2))]>,
8878 let hasSideEffects = 0 in
8879 def rr_REV : AVX512Ii8<0x15, MRMDestReg, (outs GR32orGR64:$dst),
8880 (ins _.RC:$src1, u8imm:$src2),
8881 OpcodeStr#".s\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8882 EVEX, TAPD, FoldGenData<NAME#rr>;
8884 defm NAME : avx512_extract_elt_bw_m<0x15, OpcodeStr, X86pextrw, _>, TAPD;
8888 multiclass avx512_extract_elt_dq<string OpcodeStr, X86VectorVTInfo _,
8889 RegisterClass GRC> {
8890 let Predicates = [HasDQI] in {
8891 def rr : AVX512Ii8<0x16, MRMDestReg, (outs GRC:$dst),
8892 (ins _.RC:$src1, u8imm:$src2),
8893 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8895 (extractelt (_.VT _.RC:$src1), imm:$src2))]>,
8898 def mr : AVX512Ii8<0x16, MRMDestMem, (outs),
8899 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
8900 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8901 [(store (extractelt (_.VT _.RC:$src1),
8902 imm:$src2),addr:$dst)]>,
8903 EVEX, EVEX_CD8<_.EltSize, CD8VT1>, TAPD;
8907 defm VPEXTRBZ : avx512_extract_elt_b<"vpextrb", v16i8x_info>;
8908 defm VPEXTRWZ : avx512_extract_elt_w<"vpextrw", v8i16x_info>;
8909 defm VPEXTRDZ : avx512_extract_elt_dq<"vpextrd", v4i32x_info, GR32>;
8910 defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, VEX_W;
8912 multiclass avx512_insert_elt_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
8913 X86VectorVTInfo _, PatFrag LdFrag> {
8914 def rm : AVX512Ii8<opc, MRMSrcMem, (outs _.RC:$dst),
8915 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
8916 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8918 (_.VT (OpNode _.RC:$src1, (LdFrag addr:$src2), imm:$src3)))]>,
8919 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
8922 multiclass avx512_insert_elt_bw<bits<8> opc, string OpcodeStr, SDNode OpNode,
8923 X86VectorVTInfo _, PatFrag LdFrag> {
8924 let Predicates = [HasBWI] in {
8925 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
8926 (ins _.RC:$src1, GR32orGR64:$src2, u8imm:$src3),
8927 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8929 (OpNode _.RC:$src1, GR32orGR64:$src2, imm:$src3))]>, EVEX_4V;
8931 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, OpNode, _, LdFrag>;
8935 multiclass avx512_insert_elt_dq<bits<8> opc, string OpcodeStr,
8936 X86VectorVTInfo _, RegisterClass GRC> {
8937 let Predicates = [HasDQI] in {
8938 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
8939 (ins _.RC:$src1, GRC:$src2, u8imm:$src3),
8940 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8942 (_.VT (insertelt _.RC:$src1, GRC:$src2, imm:$src3)))]>,
8945 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, insertelt, _,
8946 _.ScalarLdFrag>, TAPD;
8950 defm VPINSRBZ : avx512_insert_elt_bw<0x20, "vpinsrb", X86pinsrb, v16i8x_info,
8952 defm VPINSRWZ : avx512_insert_elt_bw<0xC4, "vpinsrw", X86pinsrw, v8i16x_info,
8954 defm VPINSRDZ : avx512_insert_elt_dq<0x22, "vpinsrd", v4i32x_info, GR32>;
8955 defm VPINSRQZ : avx512_insert_elt_dq<0x22, "vpinsrq", v2i64x_info, GR64>, VEX_W;
8956 //===----------------------------------------------------------------------===//
8957 // VSHUFPS - VSHUFPD Operations
8958 //===----------------------------------------------------------------------===//
8959 multiclass avx512_shufp<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
8960 AVX512VLVectorVTInfo VTInfo_FP>{
8961 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0xC6, X86Shufp>,
8962 EVEX_CD8<VTInfo_FP.info512.EltSize, CD8VF>,
8963 AVX512AIi8Base, EVEX_4V;
8966 defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_i32_info, avx512vl_f32_info>, PS;
8967 defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD, VEX_W;
8968 //===----------------------------------------------------------------------===//
8969 // AVX-512 - Byte shift Left/Right
8970 //===----------------------------------------------------------------------===//
8972 multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
8973 Format MRMm, string OpcodeStr, X86VectorVTInfo _>{
8974 def rr : AVX512<opc, MRMr,
8975 (outs _.RC:$dst), (ins _.RC:$src1, u8imm:$src2),
8976 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8977 [(set _.RC:$dst,(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>;
8978 def rm : AVX512<opc, MRMm,
8979 (outs _.RC:$dst), (ins _.MemOp:$src1, u8imm:$src2),
8980 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8981 [(set _.RC:$dst,(_.VT (OpNode
8982 (_.VT (bitconvert (_.LdFrag addr:$src1))),
8983 (i8 imm:$src2))))]>;
8986 multiclass avx512_shift_packed_all<bits<8> opc, SDNode OpNode, Format MRMr,
8987 Format MRMm, string OpcodeStr, Predicate prd>{
8988 let Predicates = [prd] in
8989 defm Z512 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
8990 OpcodeStr, v64i8_info>, EVEX_V512;
8991 let Predicates = [prd, HasVLX] in {
8992 defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
8993 OpcodeStr, v32i8x_info>, EVEX_V256;
8994 defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
8995 OpcodeStr, v16i8x_info>, EVEX_V128;
8998 defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq",
8999 HasBWI>, AVX512PDIi8Base, EVEX_4V;
9000 defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq",
9001 HasBWI>, AVX512PDIi8Base, EVEX_4V;
9004 multiclass avx512_psadbw_packed<bits<8> opc, SDNode OpNode,
9005 string OpcodeStr, X86VectorVTInfo _dst,
9006 X86VectorVTInfo _src>{
9007 def rr : AVX512BI<opc, MRMSrcReg,
9008 (outs _dst.RC:$dst), (ins _src.RC:$src1, _src.RC:$src2),
9009 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9010 [(set _dst.RC:$dst,(_dst.VT
9011 (OpNode (_src.VT _src.RC:$src1),
9012 (_src.VT _src.RC:$src2))))]>;
9013 def rm : AVX512BI<opc, MRMSrcMem,
9014 (outs _dst.RC:$dst), (ins _src.RC:$src1, _src.MemOp:$src2),
9015 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9016 [(set _dst.RC:$dst,(_dst.VT
9017 (OpNode (_src.VT _src.RC:$src1),
9018 (_src.VT (bitconvert
9019 (_src.LdFrag addr:$src2))))))]>;
9022 multiclass avx512_psadbw_packed_all<bits<8> opc, SDNode OpNode,
9023 string OpcodeStr, Predicate prd> {
9024 let Predicates = [prd] in
9025 defm Z512 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v8i64_info,
9026 v64i8_info>, EVEX_V512;
9027 let Predicates = [prd, HasVLX] in {
9028 defm Z256 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v4i64x_info,
9029 v32i8x_info>, EVEX_V256;
9030 defm Z128 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v2i64x_info,
9031 v16i8x_info>, EVEX_V128;
9035 defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw",
9038 // Transforms to swizzle an immediate to enable better matching when
9039 // memory operand isn't in the right place.
9040 def VPTERNLOG321_imm8 : SDNodeXForm<imm, [{
9041 // Convert a VPTERNLOG immediate by swapping operand 0 and operand 2.
9042 uint8_t Imm = N->getZExtValue();
9043 // Swap bits 1/4 and 3/6.
9044 uint8_t NewImm = Imm & 0xa5;
9045 if (Imm & 0x02) NewImm |= 0x10;
9046 if (Imm & 0x10) NewImm |= 0x02;
9047 if (Imm & 0x08) NewImm |= 0x40;
9048 if (Imm & 0x40) NewImm |= 0x08;
9049 return getI8Imm(NewImm, SDLoc(N));
9051 def VPTERNLOG213_imm8 : SDNodeXForm<imm, [{
9052 // Convert a VPTERNLOG immediate by swapping operand 1 and operand 2.
9053 uint8_t Imm = N->getZExtValue();
9054 // Swap bits 2/4 and 3/5.
9055 uint8_t NewImm = Imm & 0xc3;
9056 if (Imm & 0x04) NewImm |= 0x10;
9057 if (Imm & 0x10) NewImm |= 0x04;
9058 if (Imm & 0x08) NewImm |= 0x20;
9059 if (Imm & 0x20) NewImm |= 0x08;
9060 return getI8Imm(NewImm, SDLoc(N));
9062 def VPTERNLOG132_imm8 : SDNodeXForm<imm, [{
9063 // Convert a VPTERNLOG immediate by swapping operand 1 and operand 2.
9064 uint8_t Imm = N->getZExtValue();
9065 // Swap bits 1/2 and 5/6.
9066 uint8_t NewImm = Imm & 0x99;
9067 if (Imm & 0x02) NewImm |= 0x04;
9068 if (Imm & 0x04) NewImm |= 0x02;
9069 if (Imm & 0x20) NewImm |= 0x40;
9070 if (Imm & 0x40) NewImm |= 0x20;
9071 return getI8Imm(NewImm, SDLoc(N));
9073 def VPTERNLOG231_imm8 : SDNodeXForm<imm, [{
9074 // Convert a VPTERNLOG immediate by moving operand 1 to the end.
9075 uint8_t Imm = N->getZExtValue();
9076 // Move bits 1->2, 2->4, 3->6, 4->1, 5->3, 6->5
9077 uint8_t NewImm = Imm & 0x81;
9078 if (Imm & 0x02) NewImm |= 0x04;
9079 if (Imm & 0x04) NewImm |= 0x10;
9080 if (Imm & 0x08) NewImm |= 0x40;
9081 if (Imm & 0x10) NewImm |= 0x02;
9082 if (Imm & 0x20) NewImm |= 0x08;
9083 if (Imm & 0x40) NewImm |= 0x20;
9084 return getI8Imm(NewImm, SDLoc(N));
9086 def VPTERNLOG312_imm8 : SDNodeXForm<imm, [{
9087 // Convert a VPTERNLOG immediate by moving operand 2 to the beginning.
9088 uint8_t Imm = N->getZExtValue();
9089 // Move bits 1->4, 2->1, 3->5, 4->2, 5->6, 6->3
9090 uint8_t NewImm = Imm & 0x81;
9091 if (Imm & 0x02) NewImm |= 0x10;
9092 if (Imm & 0x04) NewImm |= 0x02;
9093 if (Imm & 0x08) NewImm |= 0x20;
9094 if (Imm & 0x10) NewImm |= 0x04;
9095 if (Imm & 0x20) NewImm |= 0x40;
9096 if (Imm & 0x40) NewImm |= 0x08;
9097 return getI8Imm(NewImm, SDLoc(N));
9100 multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
9102 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in {
9103 defm rri : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
9104 (ins _.RC:$src2, _.RC:$src3, u8imm:$src4),
9105 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src4",
9106 (OpNode (_.VT _.RC:$src1),
9109 (i8 imm:$src4)), 1, 1>, AVX512AIi8Base, EVEX_4V;
9110 defm rmi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
9111 (ins _.RC:$src2, _.MemOp:$src3, u8imm:$src4),
9112 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src4",
9113 (OpNode (_.VT _.RC:$src1),
9115 (_.VT (bitconvert (_.LdFrag addr:$src3))),
9116 (i8 imm:$src4)), 1, 0>,
9117 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
9118 defm rmbi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
9119 (ins _.RC:$src2, _.ScalarMemOp:$src3, u8imm:$src4),
9120 OpcodeStr, "$src4, ${src3}"##_.BroadcastStr##", $src2",
9121 "$src2, ${src3}"##_.BroadcastStr##", $src4",
9122 (OpNode (_.VT _.RC:$src1),
9124 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
9125 (i8 imm:$src4)), 1, 0>, EVEX_B,
9126 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
9127 }// Constraints = "$src1 = $dst"
9129 // Additional patterns for matching passthru operand in other positions.
9130 def : Pat<(_.VT (vselect _.KRCWM:$mask,
9131 (OpNode _.RC:$src3, _.RC:$src2, _.RC:$src1, (i8 imm:$src4)),
9133 (!cast<Instruction>(NAME#_.ZSuffix#rrik) _.RC:$src1, _.KRCWM:$mask,
9134 _.RC:$src2, _.RC:$src3, (VPTERNLOG321_imm8 imm:$src4))>;
9135 def : Pat<(_.VT (vselect _.KRCWM:$mask,
9136 (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3, (i8 imm:$src4)),
9138 (!cast<Instruction>(NAME#_.ZSuffix#rrik) _.RC:$src1, _.KRCWM:$mask,
9139 _.RC:$src2, _.RC:$src3, (VPTERNLOG213_imm8 imm:$src4))>;
9141 // Additional patterns for matching loads in other positions.
9142 def : Pat<(_.VT (OpNode (bitconvert (_.LdFrag addr:$src3)),
9143 _.RC:$src2, _.RC:$src1, (i8 imm:$src4))),
9144 (!cast<Instruction>(NAME#_.ZSuffix#rmi) _.RC:$src1, _.RC:$src2,
9145 addr:$src3, (VPTERNLOG321_imm8 imm:$src4))>;
9146 def : Pat<(_.VT (OpNode _.RC:$src1,
9147 (bitconvert (_.LdFrag addr:$src3)),
9148 _.RC:$src2, (i8 imm:$src4))),
9149 (!cast<Instruction>(NAME#_.ZSuffix#rmi) _.RC:$src1, _.RC:$src2,
9150 addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>;
9152 // Additional patterns for matching zero masking with loads in other
9154 def : Pat<(_.VT (vselect _.KRCWM:$mask,
9155 (OpNode (bitconvert (_.LdFrag addr:$src3)),
9156 _.RC:$src2, _.RC:$src1, (i8 imm:$src4)),
9158 (!cast<Instruction>(NAME#_.ZSuffix#rmikz) _.RC:$src1, _.KRCWM:$mask,
9159 _.RC:$src2, addr:$src3, (VPTERNLOG321_imm8 imm:$src4))>;
9160 def : Pat<(_.VT (vselect _.KRCWM:$mask,
9161 (OpNode _.RC:$src1, (bitconvert (_.LdFrag addr:$src3)),
9162 _.RC:$src2, (i8 imm:$src4)),
9164 (!cast<Instruction>(NAME#_.ZSuffix#rmikz) _.RC:$src1, _.KRCWM:$mask,
9165 _.RC:$src2, addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>;
9167 // Additional patterns for matching masked loads with different
9169 def : Pat<(_.VT (vselect _.KRCWM:$mask,
9170 (OpNode _.RC:$src1, (bitconvert (_.LdFrag addr:$src3)),
9171 _.RC:$src2, (i8 imm:$src4)),
9173 (!cast<Instruction>(NAME#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
9174 _.RC:$src2, addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>;
9175 def : Pat<(_.VT (vselect _.KRCWM:$mask,
9176 (OpNode (bitconvert (_.LdFrag addr:$src3)),
9177 _.RC:$src2, _.RC:$src1, (i8 imm:$src4)),
9179 (!cast<Instruction>(NAME#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
9180 _.RC:$src2, addr:$src3, (VPTERNLOG321_imm8 imm:$src4))>;
9181 def : Pat<(_.VT (vselect _.KRCWM:$mask,
9182 (OpNode _.RC:$src2, _.RC:$src1,
9183 (bitconvert (_.LdFrag addr:$src3)), (i8 imm:$src4)),
9185 (!cast<Instruction>(NAME#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
9186 _.RC:$src2, addr:$src3, (VPTERNLOG213_imm8 imm:$src4))>;
9187 def : Pat<(_.VT (vselect _.KRCWM:$mask,
9188 (OpNode _.RC:$src2, (bitconvert (_.LdFrag addr:$src3)),
9189 _.RC:$src1, (i8 imm:$src4)),
9191 (!cast<Instruction>(NAME#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
9192 _.RC:$src2, addr:$src3, (VPTERNLOG231_imm8 imm:$src4))>;
9193 def : Pat<(_.VT (vselect _.KRCWM:$mask,
9194 (OpNode (bitconvert (_.LdFrag addr:$src3)),
9195 _.RC:$src1, _.RC:$src2, (i8 imm:$src4)),
9197 (!cast<Instruction>(NAME#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
9198 _.RC:$src2, addr:$src3, (VPTERNLOG312_imm8 imm:$src4))>;
9200 // Additional patterns for matching broadcasts in other positions.
9201 def : Pat<(_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
9202 _.RC:$src2, _.RC:$src1, (i8 imm:$src4))),
9203 (!cast<Instruction>(NAME#_.ZSuffix#rmbi) _.RC:$src1, _.RC:$src2,
9204 addr:$src3, (VPTERNLOG321_imm8 imm:$src4))>;
9205 def : Pat<(_.VT (OpNode _.RC:$src1,
9206 (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
9207 _.RC:$src2, (i8 imm:$src4))),
9208 (!cast<Instruction>(NAME#_.ZSuffix#rmbi) _.RC:$src1, _.RC:$src2,
9209 addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>;
9211 // Additional patterns for matching zero masking with broadcasts in other
9213 def : Pat<(_.VT (vselect _.KRCWM:$mask,
9214 (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
9215 _.RC:$src2, _.RC:$src1, (i8 imm:$src4)),
9217 (!cast<Instruction>(NAME#_.ZSuffix#rmbikz) _.RC:$src1,
9218 _.KRCWM:$mask, _.RC:$src2, addr:$src3,
9219 (VPTERNLOG321_imm8 imm:$src4))>;
9220 def : Pat<(_.VT (vselect _.KRCWM:$mask,
9222 (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
9223 _.RC:$src2, (i8 imm:$src4)),
9225 (!cast<Instruction>(NAME#_.ZSuffix#rmbikz) _.RC:$src1,
9226 _.KRCWM:$mask, _.RC:$src2, addr:$src3,
9227 (VPTERNLOG132_imm8 imm:$src4))>;
9229 // Additional patterns for matching masked broadcasts with different
9231 def : Pat<(_.VT (vselect _.KRCWM:$mask,
9233 (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
9234 _.RC:$src2, (i8 imm:$src4)),
9236 (!cast<Instruction>(NAME#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask,
9237 _.RC:$src2, addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>;
9238 def : Pat<(_.VT (vselect _.KRCWM:$mask,
9239 (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
9240 _.RC:$src2, _.RC:$src1, (i8 imm:$src4)),
9242 (!cast<Instruction>(NAME#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
9243 _.RC:$src2, addr:$src3, (VPTERNLOG321_imm8 imm:$src4))>;
9244 def : Pat<(_.VT (vselect _.KRCWM:$mask,
9245 (OpNode _.RC:$src2, _.RC:$src1,
9246 (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
9247 (i8 imm:$src4)), _.RC:$src1)),
9248 (!cast<Instruction>(NAME#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
9249 _.RC:$src2, addr:$src3, (VPTERNLOG213_imm8 imm:$src4))>;
9250 def : Pat<(_.VT (vselect _.KRCWM:$mask,
9252 (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
9253 _.RC:$src1, (i8 imm:$src4)),
9255 (!cast<Instruction>(NAME#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
9256 _.RC:$src2, addr:$src3, (VPTERNLOG231_imm8 imm:$src4))>;
9257 def : Pat<(_.VT (vselect _.KRCWM:$mask,
9258 (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
9259 _.RC:$src1, _.RC:$src2, (i8 imm:$src4)),
9261 (!cast<Instruction>(NAME#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
9262 _.RC:$src2, addr:$src3, (VPTERNLOG312_imm8 imm:$src4))>;
9265 multiclass avx512_common_ternlog<string OpcodeStr, AVX512VLVectorVTInfo _>{
9266 let Predicates = [HasAVX512] in
9267 defm Z : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info512>, EVEX_V512;
9268 let Predicates = [HasAVX512, HasVLX] in {
9269 defm Z128 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info128>, EVEX_V128;
9270 defm Z256 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info256>, EVEX_V256;
9274 defm VPTERNLOGD : avx512_common_ternlog<"vpternlogd", avx512vl_i32_info>;
9275 defm VPTERNLOGQ : avx512_common_ternlog<"vpternlogq", avx512vl_i64_info>, VEX_W;
9277 //===----------------------------------------------------------------------===//
9278 // AVX-512 - FixupImm
9279 //===----------------------------------------------------------------------===//
9281 multiclass avx512_fixupimm_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
9283 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in {
9284 defm rri : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
9285 (ins _.RC:$src2, _.RC:$src3, i32u8imm:$src4),
9286 OpcodeStr##_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
9287 (OpNode (_.VT _.RC:$src1),
9289 (_.IntVT _.RC:$src3),
9291 (i32 FROUND_CURRENT))>;
9292 defm rmi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
9293 (ins _.RC:$src2, _.MemOp:$src3, i32u8imm:$src4),
9294 OpcodeStr##_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
9295 (OpNode (_.VT _.RC:$src1),
9297 (_.IntVT (bitconvert (_.LdFrag addr:$src3))),
9299 (i32 FROUND_CURRENT))>;
9300 defm rmbi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
9301 (ins _.RC:$src2, _.ScalarMemOp:$src3, i32u8imm:$src4),
9302 OpcodeStr##_.Suffix, "$src4, ${src3}"##_.BroadcastStr##", $src2",
9303 "$src2, ${src3}"##_.BroadcastStr##", $src4",
9304 (OpNode (_.VT _.RC:$src1),
9306 (_.IntVT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
9308 (i32 FROUND_CURRENT))>, EVEX_B;
9309 } // Constraints = "$src1 = $dst"
9312 multiclass avx512_fixupimm_packed_sae<bits<8> opc, string OpcodeStr,
9313 SDNode OpNode, X86VectorVTInfo _>{
9314 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in {
9315 defm rrib : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
9316 (ins _.RC:$src2, _.RC:$src3, i32u8imm:$src4),
9317 OpcodeStr##_.Suffix, "$src4, {sae}, $src3, $src2",
9318 "$src2, $src3, {sae}, $src4",
9319 (OpNode (_.VT _.RC:$src1),
9321 (_.IntVT _.RC:$src3),
9323 (i32 FROUND_NO_EXC))>, EVEX_B;
9327 multiclass avx512_fixupimm_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
9328 X86VectorVTInfo _, X86VectorVTInfo _src3VT> {
9329 let Constraints = "$src1 = $dst" , Predicates = [HasAVX512],
9330 ExeDomain = _.ExeDomain in {
9331 defm rri : AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
9332 (ins _.RC:$src2, _.RC:$src3, i32u8imm:$src4),
9333 OpcodeStr##_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
9334 (OpNode (_.VT _.RC:$src1),
9336 (_src3VT.VT _src3VT.RC:$src3),
9338 (i32 FROUND_CURRENT))>;
9340 defm rrib : AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
9341 (ins _.RC:$src2, _.RC:$src3, i32u8imm:$src4),
9342 OpcodeStr##_.Suffix, "$src4, {sae}, $src3, $src2",
9343 "$src2, $src3, {sae}, $src4",
9344 (OpNode (_.VT _.RC:$src1),
9346 (_src3VT.VT _src3VT.RC:$src3),
9348 (i32 FROUND_NO_EXC))>, EVEX_B;
9349 defm rmi : AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
9350 (ins _.RC:$src2, _.ScalarMemOp:$src3, i32u8imm:$src4),
9351 OpcodeStr##_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
9352 (OpNode (_.VT _.RC:$src1),
9354 (_src3VT.VT (scalar_to_vector
9355 (_src3VT.ScalarLdFrag addr:$src3))),
9357 (i32 FROUND_CURRENT))>;
9361 multiclass avx512_fixupimm_packed_all<AVX512VLVectorVTInfo _Vec>{
9362 let Predicates = [HasAVX512] in
9363 defm Z : avx512_fixupimm_packed<0x54, "vfixupimm", X86VFixupimm, _Vec.info512>,
9364 avx512_fixupimm_packed_sae<0x54, "vfixupimm", X86VFixupimm, _Vec.info512>,
9365 AVX512AIi8Base, EVEX_4V, EVEX_V512;
9366 let Predicates = [HasAVX512, HasVLX] in {
9367 defm Z128 : avx512_fixupimm_packed<0x54, "vfixupimm", X86VFixupimm, _Vec.info128>,
9368 AVX512AIi8Base, EVEX_4V, EVEX_V128;
9369 defm Z256 : avx512_fixupimm_packed<0x54, "vfixupimm", X86VFixupimm, _Vec.info256>,
9370 AVX512AIi8Base, EVEX_4V, EVEX_V256;
9374 defm VFIXUPIMMSS : avx512_fixupimm_scalar<0x55, "vfixupimm", X86VFixupimmScalar,
9375 f32x_info, v4i32x_info>,
9376 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
9377 defm VFIXUPIMMSD : avx512_fixupimm_scalar<0x55, "vfixupimm", X86VFixupimmScalar,
9378 f64x_info, v2i64x_info>,
9379 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
9380 defm VFIXUPIMMPS : avx512_fixupimm_packed_all<avx512vl_f32_info>,
9381 EVEX_CD8<32, CD8VF>;
9382 defm VFIXUPIMMPD : avx512_fixupimm_packed_all<avx512vl_f64_info>,
9383 EVEX_CD8<64, CD8VF>, VEX_W;
9387 // Patterns used to select SSE scalar fp arithmetic instructions from
9390 // (1) a scalar fp operation followed by a blend
9392 // The effect is that the backend no longer emits unnecessary vector
9393 // insert instructions immediately after SSE scalar fp instructions
9394 // like addss or mulss.
9396 // For example, given the following code:
9397 // __m128 foo(__m128 A, __m128 B) {
9402 // Previously we generated:
9403 // addss %xmm0, %xmm1
9404 // movss %xmm1, %xmm0
9407 // addss %xmm1, %xmm0
9409 // (2) a vector packed single/double fp operation followed by a vector insert
9411 // The effect is that the backend converts the packed fp instruction
9412 // followed by a vector insert into a single SSE scalar fp instruction.
9414 // For example, given the following code:
9415 // __m128 foo(__m128 A, __m128 B) {
9416 // __m128 C = A + B;
9417 // return (__m128) {c[0], a[1], a[2], a[3]};
9420 // Previously we generated:
9421 // addps %xmm0, %xmm1
9422 // movss %xmm1, %xmm0
9425 // addss %xmm1, %xmm0
9427 // TODO: Some canonicalization in lowering would simplify the number of
9428 // patterns we have to try to match.
9429 multiclass AVX512_scalar_math_f32_patterns<SDNode Op, string OpcPrefix> {
9430 let Predicates = [HasAVX512] in {
9431 // extracted scalar math op with insert via movss
9432 def : Pat<(v4f32 (X86Movss (v4f32 VR128X:$dst), (v4f32 (scalar_to_vector
9433 (Op (f32 (extractelt (v4f32 VR128X:$dst), (iPTR 0))),
9435 (!cast<I>("V"#OpcPrefix#SSZrr_Int) v4f32:$dst,
9436 (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
9438 // extracted scalar math op with insert via blend
9439 def : Pat<(v4f32 (X86Blendi (v4f32 VR128X:$dst), (v4f32 (scalar_to_vector
9440 (Op (f32 (extractelt (v4f32 VR128X:$dst), (iPTR 0))),
9441 FR32X:$src))), (i8 1))),
9442 (!cast<I>("V"#OpcPrefix#SSZrr_Int) v4f32:$dst,
9443 (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
9445 // vector math op with insert via movss
9446 def : Pat<(v4f32 (X86Movss (v4f32 VR128X:$dst),
9447 (Op (v4f32 VR128X:$dst), (v4f32 VR128X:$src)))),
9448 (!cast<I>("V"#OpcPrefix#SSZrr_Int) v4f32:$dst, v4f32:$src)>;
9450 // vector math op with insert via blend
9451 def : Pat<(v4f32 (X86Blendi (v4f32 VR128X:$dst),
9452 (Op (v4f32 VR128X:$dst), (v4f32 VR128X:$src)), (i8 1))),
9453 (!cast<I>("V"#OpcPrefix#SSZrr_Int) v4f32:$dst, v4f32:$src)>;
9455 // extracted masked scalar math op with insert via movss
9456 def : Pat<(X86Movss (v4f32 VR128X:$src1),
9458 (X86selects VK1WM:$mask,
9459 (Op (f32 (extractelt (v4f32 VR128X:$src1), (iPTR 0))),
9462 (!cast<I>("V"#OpcPrefix#SSZrr_Intk) (COPY_TO_REGCLASS FR32X:$src0, VR128X),
9463 VK1WM:$mask, v4f32:$src1,
9464 (COPY_TO_REGCLASS FR32X:$src2, VR128X))>;
9468 defm : AVX512_scalar_math_f32_patterns<fadd, "ADD">;
9469 defm : AVX512_scalar_math_f32_patterns<fsub, "SUB">;
9470 defm : AVX512_scalar_math_f32_patterns<fmul, "MUL">;
9471 defm : AVX512_scalar_math_f32_patterns<fdiv, "DIV">;
9473 multiclass AVX512_scalar_math_f64_patterns<SDNode Op, string OpcPrefix> {
9474 let Predicates = [HasAVX512] in {
9475 // extracted scalar math op with insert via movsd
9476 def : Pat<(v2f64 (X86Movsd (v2f64 VR128X:$dst), (v2f64 (scalar_to_vector
9477 (Op (f64 (extractelt (v2f64 VR128X:$dst), (iPTR 0))),
9479 (!cast<I>("V"#OpcPrefix#SDZrr_Int) v2f64:$dst,
9480 (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
9482 // extracted scalar math op with insert via blend
9483 def : Pat<(v2f64 (X86Blendi (v2f64 VR128X:$dst), (v2f64 (scalar_to_vector
9484 (Op (f64 (extractelt (v2f64 VR128X:$dst), (iPTR 0))),
9485 FR64X:$src))), (i8 1))),
9486 (!cast<I>("V"#OpcPrefix#SDZrr_Int) v2f64:$dst,
9487 (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
9489 // vector math op with insert via movsd
9490 def : Pat<(v2f64 (X86Movsd (v2f64 VR128X:$dst),
9491 (Op (v2f64 VR128X:$dst), (v2f64 VR128X:$src)))),
9492 (!cast<I>("V"#OpcPrefix#SDZrr_Int) v2f64:$dst, v2f64:$src)>;
9494 // vector math op with insert via blend
9495 def : Pat<(v2f64 (X86Blendi (v2f64 VR128X:$dst),
9496 (Op (v2f64 VR128X:$dst), (v2f64 VR128X:$src)), (i8 1))),
9497 (!cast<I>("V"#OpcPrefix#SDZrr_Int) v2f64:$dst, v2f64:$src)>;
9499 // extracted masked scalar math op with insert via movss
9500 def : Pat<(X86Movsd (v2f64 VR128X:$src1),
9502 (X86selects VK1WM:$mask,
9503 (Op (f64 (extractelt (v2f64 VR128X:$src1), (iPTR 0))),
9506 (!cast<I>("V"#OpcPrefix#SDZrr_Intk) (COPY_TO_REGCLASS FR64X:$src0, VR128X),
9507 VK1WM:$mask, v2f64:$src1,
9508 (COPY_TO_REGCLASS FR64X:$src2, VR128X))>;
9512 defm : AVX512_scalar_math_f64_patterns<fadd, "ADD">;
9513 defm : AVX512_scalar_math_f64_patterns<fsub, "SUB">;
9514 defm : AVX512_scalar_math_f64_patterns<fmul, "MUL">;
9515 defm : AVX512_scalar_math_f64_patterns<fdiv, "DIV">;