1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
34 ValueType KVT = !cast<ValueType>(!if (!eq (NumElts, 1), "i1",
35 "v" # NumElts # "i1"));
37 // The GPR register class that can hold the write mask. Use GR8 for fewer
38 // than 8 elements. Use shift-right and equal to work around the lack of
41 !cast<RegisterClass>("GR" #
42 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
44 // Suffix used in the instruction mnemonic.
45 string Suffix = suffix;
47 // VTName is a string name for vector VT. For vector types it will be
48 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
49 // It is a little bit complex for scalar types, where NumElts = 1.
50 // In this case we build v4f32 or v2f64
51 string VTName = "v" # !if (!eq (NumElts, 1),
52 !if (!eq (EltVT.Size, 32), 4,
53 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
56 ValueType VT = !cast<ValueType>(VTName);
58 string EltTypeName = !cast<string>(EltVT);
59 // Size of the element type in bits, e.g. 32 for v16i32.
60 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
61 int EltSize = EltVT.Size;
63 // "i" for integer types and "f" for floating-point types
64 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
66 // Size of RC in bits, e.g. 512 for VR512.
69 // The corresponding memory operand, e.g. i512mem for VR512.
70 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
71 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
74 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
75 // due to load promotion during legalization
76 PatFrag LdFrag = !cast<PatFrag>("load" #
77 !if (!eq (TypeVariantName, "i"),
78 !if (!eq (Size, 128), "v2i64",
79 !if (!eq (Size, 256), "v4i64",
82 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
83 !if (!eq (TypeVariantName, "i"),
84 !if (!eq (Size, 128), "v2i64",
85 !if (!eq (Size, 256), "v4i64",
87 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
90 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
92 // The corresponding float type, e.g. v16f32 for v16i32
93 // Note: For EltSize < 32, FloatVT is illegal and TableGen
94 // fails to compile, so we choose FloatVT = VT
95 ValueType FloatVT = !cast<ValueType>(
96 !if (!eq (!srl(EltSize,5),0),
98 !if (!eq(TypeVariantName, "i"),
99 "v" # NumElts # "f" # EltSize,
102 ValueType IntVT = !cast<ValueType>(
103 !if (!eq (!srl(EltSize,5),0),
105 !if (!eq(TypeVariantName, "f"),
106 "v" # NumElts # "i" # EltSize,
108 // The string to specify embedded broadcast in assembly.
109 string BroadcastStr = "{1to" # NumElts # "}";
111 // 8-bit compressed displacement tuple/subvector format. This is only
112 // defined for NumElts <= 8.
113 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
114 !cast<CD8VForm>("CD8VT" # NumElts), ?);
116 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
117 !if (!eq (Size, 256), sub_ymm, ?));
119 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
120 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
123 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
125 // A vector type of the same width with element type i32. This is used to
126 // create the canonical constant zero node ImmAllZerosV.
127 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
128 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
130 string ZSuffix = !if (!eq (Size, 128), "Z128",
131 !if (!eq (Size, 256), "Z256", "Z"));
134 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
135 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
136 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
137 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
138 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
139 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
141 // "x" in v32i8x_info means RC = VR256X
142 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
143 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
144 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
145 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
146 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
147 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
149 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
150 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
151 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
152 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
153 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
154 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
156 // We map scalar types to the smallest (128-bit) vector type
157 // with the appropriate element type. This allows to use the same masking logic.
158 def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">;
159 def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">;
160 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
161 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
163 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
164 X86VectorVTInfo i128> {
165 X86VectorVTInfo info512 = i512;
166 X86VectorVTInfo info256 = i256;
167 X86VectorVTInfo info128 = i128;
170 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
172 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
174 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
176 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
178 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
180 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
183 // This multiclass generates the masking variants from the non-masking
184 // variant. It only provides the assembly pieces for the masking variants.
185 // It assumes custom ISel patterns for masking which can be provided as
186 // template arguments.
187 multiclass AVX512_maskable_custom<bits<8> O, Format F,
189 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
191 string AttSrcAsm, string IntelSrcAsm,
193 list<dag> MaskingPattern,
194 list<dag> ZeroMaskingPattern,
195 string MaskingConstraint = "",
196 InstrItinClass itin = NoItinerary,
197 bit IsCommutable = 0> {
198 let isCommutable = IsCommutable in
199 def NAME: AVX512<O, F, Outs, Ins,
200 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
201 "$dst, "#IntelSrcAsm#"}",
204 // Prefer over VMOV*rrk Pat<>
205 let AddedComplexity = 20 in
206 def NAME#k: AVX512<O, F, Outs, MaskingIns,
207 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
208 "$dst {${mask}}, "#IntelSrcAsm#"}",
209 MaskingPattern, itin>,
211 // In case of the 3src subclass this is overridden with a let.
212 string Constraints = MaskingConstraint;
214 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
215 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
216 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
217 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
224 // Common base class of AVX512_maskable and AVX512_maskable_3src.
225 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
227 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
229 string AttSrcAsm, string IntelSrcAsm,
230 dag RHS, dag MaskingRHS,
231 SDNode Select = vselect,
232 string MaskingConstraint = "",
233 InstrItinClass itin = NoItinerary,
234 bit IsCommutable = 0> :
235 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
236 AttSrcAsm, IntelSrcAsm,
237 [(set _.RC:$dst, RHS)],
238 [(set _.RC:$dst, MaskingRHS)],
240 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
241 MaskingConstraint, NoItinerary, IsCommutable>;
243 // This multiclass generates the unconditional/non-masking, the masking and
244 // the zero-masking variant of the vector instruction. In the masking case, the
245 // perserved vector elements come from a new dummy input operand tied to $dst.
246 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
247 dag Outs, dag Ins, string OpcodeStr,
248 string AttSrcAsm, string IntelSrcAsm,
250 InstrItinClass itin = NoItinerary,
251 bit IsCommutable = 0, SDNode Select = vselect> :
252 AVX512_maskable_common<O, F, _, Outs, Ins,
253 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
254 !con((ins _.KRCWM:$mask), Ins),
255 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
256 (Select _.KRCWM:$mask, RHS, _.RC:$src0), Select,
257 "$src0 = $dst", itin, IsCommutable>;
259 // This multiclass generates the unconditional/non-masking, the masking and
260 // the zero-masking variant of the scalar instruction.
261 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
262 dag Outs, dag Ins, string OpcodeStr,
263 string AttSrcAsm, string IntelSrcAsm,
265 InstrItinClass itin = NoItinerary,
266 bit IsCommutable = 0> :
267 AVX512_maskable_common<O, F, _, Outs, Ins,
268 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
269 !con((ins _.KRCWM:$mask), Ins),
270 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
271 (X86selects _.KRCWM:$mask, RHS, _.RC:$src0),
272 X86selects, "$src0 = $dst", itin, IsCommutable>;
274 // Similar to AVX512_maskable but in this case one of the source operands
275 // ($src1) is already tied to $dst so we just use that for the preserved
276 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
278 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
279 dag Outs, dag NonTiedIns, string OpcodeStr,
280 string AttSrcAsm, string IntelSrcAsm,
282 AVX512_maskable_common<O, F, _, Outs,
283 !con((ins _.RC:$src1), NonTiedIns),
284 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
285 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
286 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
287 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
289 // Similar to AVX512_maskable_3rc but in this case the input VT for the tied
290 // operand differs from the output VT. This requires a bitconvert on
291 // the preserved vector going into the vselect.
292 multiclass AVX512_maskable_3src_cast<bits<8> O, Format F, X86VectorVTInfo OutVT,
293 X86VectorVTInfo InVT,
294 dag Outs, dag NonTiedIns, string OpcodeStr,
295 string AttSrcAsm, string IntelSrcAsm,
297 AVX512_maskable_common<O, F, OutVT, Outs,
298 !con((ins InVT.RC:$src1), NonTiedIns),
299 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
300 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
301 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
302 (vselect InVT.KRCWM:$mask, RHS,
303 (bitconvert InVT.RC:$src1))>;
305 multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
306 dag Outs, dag NonTiedIns, string OpcodeStr,
307 string AttSrcAsm, string IntelSrcAsm,
309 AVX512_maskable_common<O, F, _, Outs,
310 !con((ins _.RC:$src1), NonTiedIns),
311 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
312 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
313 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
314 (X86selects _.KRCWM:$mask, RHS, _.RC:$src1),
317 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
320 string AttSrcAsm, string IntelSrcAsm,
322 AVX512_maskable_custom<O, F, Outs, Ins,
323 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
324 !con((ins _.KRCWM:$mask), Ins),
325 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
329 // Instruction with mask that puts result in mask register,
330 // like "compare" and "vptest"
331 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
333 dag Ins, dag MaskingIns,
335 string AttSrcAsm, string IntelSrcAsm,
337 list<dag> MaskingPattern> {
338 def NAME: AVX512<O, F, Outs, Ins,
339 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
340 "$dst, "#IntelSrcAsm#"}",
341 Pattern, NoItinerary>;
343 def NAME#k: AVX512<O, F, Outs, MaskingIns,
344 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
345 "$dst {${mask}}, "#IntelSrcAsm#"}",
346 MaskingPattern, NoItinerary>, EVEX_K;
349 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
351 dag Ins, dag MaskingIns,
353 string AttSrcAsm, string IntelSrcAsm,
354 dag RHS, dag MaskingRHS> :
355 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
356 AttSrcAsm, IntelSrcAsm,
357 [(set _.KRC:$dst, RHS)],
358 [(set _.KRC:$dst, MaskingRHS)]>;
360 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
361 dag Outs, dag Ins, string OpcodeStr,
362 string AttSrcAsm, string IntelSrcAsm,
364 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
365 !con((ins _.KRCWM:$mask), Ins),
366 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
367 (and _.KRCWM:$mask, RHS)>;
369 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
370 dag Outs, dag Ins, string OpcodeStr,
371 string AttSrcAsm, string IntelSrcAsm> :
372 AVX512_maskable_custom_cmp<O, F, Outs,
373 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
374 AttSrcAsm, IntelSrcAsm, [],[]>;
376 // Bitcasts between 512-bit vector types. Return the original type since
377 // no instruction is needed for the conversion.
378 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
379 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
380 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
381 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
382 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
383 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
384 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
385 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
386 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
387 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
388 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
389 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
390 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
391 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
392 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
393 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
394 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
395 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
396 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
397 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
398 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
399 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
400 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
401 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
402 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
403 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
404 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
405 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
406 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
407 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
408 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
410 // Alias instruction that maps zero vector to pxor / xorp* for AVX-512.
411 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
412 // swizzled by ExecutionDepsFix to pxor.
413 // We set canFoldAsLoad because this can be converted to a constant-pool
414 // load of an all-zeros value if folding it would be beneficial.
415 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
416 isPseudo = 1, Predicates = [HasAVX512], SchedRW = [WriteZero] in {
417 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
418 [(set VR512:$dst, (v16i32 immAllZerosV))]>;
419 def AVX512_512_SETALLONES : I<0, Pseudo, (outs VR512:$dst), (ins), "",
420 [(set VR512:$dst, (v16i32 immAllOnesV))]>;
423 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
424 isPseudo = 1, Predicates = [HasVLX], SchedRW = [WriteZero] in {
425 def AVX512_128_SET0 : I<0, Pseudo, (outs VR128X:$dst), (ins), "",
426 [(set VR128X:$dst, (v4i32 immAllZerosV))]>;
427 def AVX512_256_SET0 : I<0, Pseudo, (outs VR256X:$dst), (ins), "",
428 [(set VR256X:$dst, (v8i32 immAllZerosV))]>;
431 //===----------------------------------------------------------------------===//
432 // AVX-512 - VECTOR INSERT
434 multiclass vinsert_for_size<int Opcode, X86VectorVTInfo From, X86VectorVTInfo To,
435 PatFrag vinsert_insert> {
436 let ExeDomain = To.ExeDomain in {
437 defm rr : AVX512_maskable<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
438 (ins To.RC:$src1, From.RC:$src2, i32u8imm:$src3),
439 "vinsert" # From.EltTypeName # "x" # From.NumElts,
440 "$src3, $src2, $src1", "$src1, $src2, $src3",
441 (vinsert_insert:$src3 (To.VT To.RC:$src1),
442 (From.VT From.RC:$src2),
443 (iPTR imm))>, AVX512AIi8Base, EVEX_4V;
445 defm rm : AVX512_maskable<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
446 (ins To.RC:$src1, From.MemOp:$src2, i32u8imm:$src3),
447 "vinsert" # From.EltTypeName # "x" # From.NumElts,
448 "$src3, $src2, $src1", "$src1, $src2, $src3",
449 (vinsert_insert:$src3 (To.VT To.RC:$src1),
450 (From.VT (bitconvert (From.LdFrag addr:$src2))),
451 (iPTR imm))>, AVX512AIi8Base, EVEX_4V,
452 EVEX_CD8<From.EltSize, From.CD8TupleForm>;
456 multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
457 X86VectorVTInfo To, PatFrag vinsert_insert,
458 SDNodeXForm INSERT_get_vinsert_imm , list<Predicate> p> {
459 let Predicates = p in {
460 def : Pat<(vinsert_insert:$ins
461 (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
462 (To.VT (!cast<Instruction>(InstrStr#"rr")
463 To.RC:$src1, From.RC:$src2,
464 (INSERT_get_vinsert_imm To.RC:$ins)))>;
466 def : Pat<(vinsert_insert:$ins
468 (From.VT (bitconvert (From.LdFrag addr:$src2))),
470 (To.VT (!cast<Instruction>(InstrStr#"rm")
471 To.RC:$src1, addr:$src2,
472 (INSERT_get_vinsert_imm To.RC:$ins)))>;
476 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
477 ValueType EltVT64, int Opcode256> {
479 let Predicates = [HasVLX] in
480 defm NAME # "32x4Z256" : vinsert_for_size<Opcode128,
481 X86VectorVTInfo< 4, EltVT32, VR128X>,
482 X86VectorVTInfo< 8, EltVT32, VR256X>,
483 vinsert128_insert>, EVEX_V256;
485 defm NAME # "32x4Z" : vinsert_for_size<Opcode128,
486 X86VectorVTInfo< 4, EltVT32, VR128X>,
487 X86VectorVTInfo<16, EltVT32, VR512>,
488 vinsert128_insert>, EVEX_V512;
490 defm NAME # "64x4Z" : vinsert_for_size<Opcode256,
491 X86VectorVTInfo< 4, EltVT64, VR256X>,
492 X86VectorVTInfo< 8, EltVT64, VR512>,
493 vinsert256_insert>, VEX_W, EVEX_V512;
495 let Predicates = [HasVLX, HasDQI] in
496 defm NAME # "64x2Z256" : vinsert_for_size<Opcode128,
497 X86VectorVTInfo< 2, EltVT64, VR128X>,
498 X86VectorVTInfo< 4, EltVT64, VR256X>,
499 vinsert128_insert>, VEX_W, EVEX_V256;
501 let Predicates = [HasDQI] in {
502 defm NAME # "64x2Z" : vinsert_for_size<Opcode128,
503 X86VectorVTInfo< 2, EltVT64, VR128X>,
504 X86VectorVTInfo< 8, EltVT64, VR512>,
505 vinsert128_insert>, VEX_W, EVEX_V512;
507 defm NAME # "32x8Z" : vinsert_for_size<Opcode256,
508 X86VectorVTInfo< 8, EltVT32, VR256X>,
509 X86VectorVTInfo<16, EltVT32, VR512>,
510 vinsert256_insert>, EVEX_V512;
514 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
515 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
517 // Codegen pattern with the alternative types,
518 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
519 defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info,
520 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
521 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info,
522 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
524 defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v2f64x_info, v8f64_info,
525 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
526 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v2i64x_info, v8i64_info,
527 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
529 defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v8f32x_info, v16f32_info,
530 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
531 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v8i32x_info, v16i32_info,
532 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
534 // Codegen pattern with the alternative types insert VEC128 into VEC256
535 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info,
536 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
537 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info,
538 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
539 // Codegen pattern with the alternative types insert VEC128 into VEC512
540 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v8i16x_info, v32i16_info,
541 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
542 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v16i8x_info, v64i8_info,
543 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
544 // Codegen pattern with the alternative types insert VEC256 into VEC512
545 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v16i16x_info, v32i16_info,
546 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
547 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v32i8x_info, v64i8_info,
548 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
550 // vinsertps - insert f32 to XMM
551 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
552 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
553 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
554 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
556 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
557 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
558 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
559 [(set VR128X:$dst, (X86insertps VR128X:$src1,
560 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
561 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
563 //===----------------------------------------------------------------------===//
564 // AVX-512 VECTOR EXTRACT
567 multiclass vextract_for_size<int Opcode,
568 X86VectorVTInfo From, X86VectorVTInfo To,
569 PatFrag vextract_extract> {
571 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
572 // use AVX512_maskable_in_asm (AVX512_maskable can't be used due to
573 // vextract_extract), we interesting only in patterns without mask,
574 // intrinsics pattern match generated bellow.
575 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
576 (ins From.RC:$src1, i32u8imm:$idx),
577 "vextract" # To.EltTypeName # "x" # To.NumElts,
578 "$idx, $src1", "$src1, $idx",
579 [(set To.RC:$dst, (vextract_extract:$idx (From.VT From.RC:$src1),
581 AVX512AIi8Base, EVEX;
582 def mr : AVX512AIi8<Opcode, MRMDestMem, (outs),
583 (ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$idx),
584 "vextract" # To.EltTypeName # "x" # To.NumElts #
585 "\t{$idx, $src1, $dst|$dst, $src1, $idx}",
586 [(store (To.VT (vextract_extract:$idx
587 (From.VT From.RC:$src1), (iPTR imm))),
590 let mayStore = 1, hasSideEffects = 0 in
591 def mrk : AVX512AIi8<Opcode, MRMDestMem, (outs),
592 (ins To.MemOp:$dst, To.KRCWM:$mask,
593 From.RC:$src1, i32u8imm:$idx),
594 "vextract" # To.EltTypeName # "x" # To.NumElts #
595 "\t{$idx, $src1, $dst {${mask}}|"
596 "$dst {${mask}}, $src1, $idx}",
600 // Intrinsic call with masking.
601 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
602 "x" # To.NumElts # "_" # From.Size)
603 From.RC:$src1, (iPTR imm:$idx), To.RC:$src0, To.MRC:$mask),
604 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
605 From.ZSuffix # "rrk")
607 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
608 From.RC:$src1, imm:$idx)>;
610 // Intrinsic call with zero-masking.
611 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
612 "x" # To.NumElts # "_" # From.Size)
613 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, To.MRC:$mask),
614 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
615 From.ZSuffix # "rrkz")
616 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
617 From.RC:$src1, imm:$idx)>;
619 // Intrinsic call without masking.
620 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
621 "x" # To.NumElts # "_" # From.Size)
622 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
623 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
625 From.RC:$src1, imm:$idx)>;
628 // Codegen pattern for the alternative types
629 multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
630 X86VectorVTInfo To, PatFrag vextract_extract,
631 SDNodeXForm EXTRACT_get_vextract_imm, list<Predicate> p> {
632 let Predicates = p in {
633 def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
634 (To.VT (!cast<Instruction>(InstrStr#"rr")
636 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
637 def : Pat<(store (To.VT (vextract_extract:$ext (From.VT From.RC:$src1),
638 (iPTR imm))), addr:$dst),
639 (!cast<Instruction>(InstrStr#"mr") addr:$dst, From.RC:$src1,
640 (EXTRACT_get_vextract_imm To.RC:$ext))>;
644 multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
645 ValueType EltVT64, int Opcode256> {
646 defm NAME # "32x4Z" : vextract_for_size<Opcode128,
647 X86VectorVTInfo<16, EltVT32, VR512>,
648 X86VectorVTInfo< 4, EltVT32, VR128X>,
649 vextract128_extract>,
650 EVEX_V512, EVEX_CD8<32, CD8VT4>;
651 defm NAME # "64x4Z" : vextract_for_size<Opcode256,
652 X86VectorVTInfo< 8, EltVT64, VR512>,
653 X86VectorVTInfo< 4, EltVT64, VR256X>,
654 vextract256_extract>,
655 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>;
656 let Predicates = [HasVLX] in
657 defm NAME # "32x4Z256" : vextract_for_size<Opcode128,
658 X86VectorVTInfo< 8, EltVT32, VR256X>,
659 X86VectorVTInfo< 4, EltVT32, VR128X>,
660 vextract128_extract>,
661 EVEX_V256, EVEX_CD8<32, CD8VT4>;
662 let Predicates = [HasVLX, HasDQI] in
663 defm NAME # "64x2Z256" : vextract_for_size<Opcode128,
664 X86VectorVTInfo< 4, EltVT64, VR256X>,
665 X86VectorVTInfo< 2, EltVT64, VR128X>,
666 vextract128_extract>,
667 VEX_W, EVEX_V256, EVEX_CD8<64, CD8VT2>;
668 let Predicates = [HasDQI] in {
669 defm NAME # "64x2Z" : vextract_for_size<Opcode128,
670 X86VectorVTInfo< 8, EltVT64, VR512>,
671 X86VectorVTInfo< 2, EltVT64, VR128X>,
672 vextract128_extract>,
673 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>;
674 defm NAME # "32x8Z" : vextract_for_size<Opcode256,
675 X86VectorVTInfo<16, EltVT32, VR512>,
676 X86VectorVTInfo< 8, EltVT32, VR256X>,
677 vextract256_extract>,
678 EVEX_V512, EVEX_CD8<32, CD8VT8>;
682 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
683 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
685 // extract_subvector codegen patterns with the alternative types.
686 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
687 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z", v8f64_info, v2f64x_info,
688 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
689 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v8i64_info, v2i64x_info,
690 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
692 defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v16f32_info, v8f32x_info,
693 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
694 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v16i32_info, v8i32x_info,
695 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
697 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z256", v4f64x_info, v2f64x_info,
698 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
699 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v4i64x_info, v2i64x_info,
700 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
702 // Codegen pattern with the alternative types extract VEC128 from VEC256
703 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v16i16x_info, v8i16x_info,
704 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>;
705 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v32i8x_info, v16i8x_info,
706 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>;
708 // Codegen pattern with the alternative types extract VEC128 from VEC512
709 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v32i16_info, v8i16x_info,
710 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
711 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v64i8_info, v16i8x_info,
712 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
713 // Codegen pattern with the alternative types extract VEC256 from VEC512
714 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v32i16_info, v16i16x_info,
715 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
716 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info,
717 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
719 // A 128-bit subvector extract from the first 256-bit vector position
720 // is a subregister copy that needs no instruction.
721 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
722 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
723 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
724 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
725 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
726 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
727 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
728 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
729 def : Pat<(v8i16 (extract_subvector (v32i16 VR512:$src), (iPTR 0))),
730 (v8i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_xmm))>;
731 def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 0))),
732 (v16i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_xmm))>;
734 // A 256-bit subvector extract from the first 256-bit vector position
735 // is a subregister copy that needs no instruction.
736 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
737 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
738 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
739 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
740 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
741 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
742 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
743 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
744 def : Pat<(v16i16 (extract_subvector (v32i16 VR512:$src), (iPTR 0))),
745 (v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm))>;
746 def : Pat<(v32i8 (extract_subvector (v64i8 VR512:$src), (iPTR 0))),
747 (v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm))>;
749 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
750 // A 128-bit subvector insert to the first 512-bit vector position
751 // is a subregister copy that needs no instruction.
752 def : Pat<(v8i64 (insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0))),
753 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm)>;
754 def : Pat<(v8f64 (insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0))),
755 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm)>;
756 def : Pat<(v16i32 (insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0))),
757 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm)>;
758 def : Pat<(v16f32 (insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0))),
759 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm)>;
760 def : Pat<(v32i16 (insert_subvector undef, (v8i16 VR128X:$src), (iPTR 0))),
761 (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR128X:$src, sub_xmm)>;
762 def : Pat<(v64i8 (insert_subvector undef, (v16i8 VR128X:$src), (iPTR 0))),
763 (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR128X:$src, sub_xmm)>;
765 // A 256-bit subvector insert to the first 512-bit vector position
766 // is a subregister copy that needs no instruction.
767 def : Pat<(v8i64 (insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0))),
768 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
769 def : Pat<(v8f64 (insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0))),
770 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
771 def : Pat<(v16i32 (insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0))),
772 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
773 def : Pat<(v16f32 (insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0))),
774 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
775 def : Pat<(v32i16 (insert_subvector undef, (v16i16 VR256X:$src), (iPTR 0))),
776 (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
777 def : Pat<(v64i8 (insert_subvector undef, (v32i8 VR256X:$src), (iPTR 0))),
778 (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
781 // vextractps - extract 32 bits from XMM
782 def VEXTRACTPSZrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
783 (ins VR128X:$src1, u8imm:$src2),
784 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
785 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
788 def VEXTRACTPSZmr : AVX512AIi8<0x17, MRMDestMem, (outs),
789 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
790 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
791 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
792 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
794 //===---------------------------------------------------------------------===//
797 // broadcast with a scalar argument.
798 multiclass avx512_broadcast_scalar<bits<8> opc, string OpcodeStr,
799 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo> {
801 let isCodeGenOnly = 1 in {
802 def r_s : I< opc, MRMSrcReg, (outs DestInfo.RC:$dst),
803 (ins SrcInfo.FRC:$src), OpcodeStr#"\t{$src, $dst|$dst, $src}",
804 [(set DestInfo.RC:$dst, (DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)))]>,
805 Requires<[HasAVX512]>, T8PD, EVEX;
807 let Constraints = "$src0 = $dst" in
808 def rk_s : I< opc, MRMSrcReg, (outs DestInfo.RC:$dst),
809 (ins DestInfo.RC:$src0, DestInfo.KRCWM:$mask, SrcInfo.FRC:$src),
810 OpcodeStr#"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
811 [(set DestInfo.RC:$dst,
812 (vselect DestInfo.KRCWM:$mask,
813 (DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)),
814 DestInfo.RC:$src0))]>,
815 Requires<[HasAVX512]>, T8PD, EVEX, EVEX_K;
817 def rkz_s : I< opc, MRMSrcReg, (outs DestInfo.RC:$dst),
818 (ins DestInfo.KRCWM:$mask, SrcInfo.FRC:$src),
819 OpcodeStr#"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
820 [(set DestInfo.RC:$dst,
821 (vselect DestInfo.KRCWM:$mask,
822 (DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)),
823 DestInfo.ImmAllZerosV))]>,
824 Requires<[HasAVX512]>, T8PD, EVEX, EVEX_KZ;
825 } // let isCodeGenOnly = 1 in
828 multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr,
829 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo> {
830 let ExeDomain = DestInfo.ExeDomain in {
831 defm r : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
832 (ins SrcInfo.RC:$src), OpcodeStr, "$src", "$src",
833 (DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src)))>,
835 defm m : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
836 (ins SrcInfo.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
837 (DestInfo.VT (X86VBroadcast
838 (SrcInfo.ScalarLdFrag addr:$src)))>,
839 T8PD, EVEX, EVEX_CD8<SrcInfo.EltSize, CD8VT1>;
842 def : Pat<(DestInfo.VT (X86VBroadcast
843 (SrcInfo.VT (scalar_to_vector
844 (SrcInfo.ScalarLdFrag addr:$src))))),
845 (!cast<Instruction>(NAME#DestInfo.ZSuffix#m) addr:$src)>;
846 let AddedComplexity = 20 in
847 def : Pat<(DestInfo.VT (vselect DestInfo.KRCWM:$mask,
849 (SrcInfo.VT (scalar_to_vector
850 (SrcInfo.ScalarLdFrag addr:$src)))),
852 (!cast<Instruction>(NAME#DestInfo.ZSuffix#mk)
853 DestInfo.RC:$src0, DestInfo.KRCWM:$mask, addr:$src)>;
854 let AddedComplexity = 30 in
855 def : Pat<(DestInfo.VT (vselect DestInfo.KRCWM:$mask,
857 (SrcInfo.VT (scalar_to_vector
858 (SrcInfo.ScalarLdFrag addr:$src)))),
859 DestInfo.ImmAllZerosV)),
860 (!cast<Instruction>(NAME#DestInfo.ZSuffix#mkz)
861 DestInfo.KRCWM:$mask, addr:$src)>;
864 multiclass avx512_fp_broadcast_sd<bits<8> opc, string OpcodeStr,
865 AVX512VLVectorVTInfo _> {
866 let Predicates = [HasAVX512] in
867 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
868 avx512_broadcast_scalar<opc, OpcodeStr, _.info512, _.info128>,
871 let Predicates = [HasVLX] in {
872 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
873 avx512_broadcast_scalar<opc, OpcodeStr, _.info256, _.info128>,
878 multiclass avx512_fp_broadcast_ss<bits<8> opc, string OpcodeStr,
879 AVX512VLVectorVTInfo _> {
880 let Predicates = [HasAVX512] in
881 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
882 avx512_broadcast_scalar<opc, OpcodeStr, _.info512, _.info128>,
885 let Predicates = [HasVLX] in {
886 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
887 avx512_broadcast_scalar<opc, OpcodeStr, _.info256, _.info128>,
889 defm Z128 : avx512_broadcast_rm<opc, OpcodeStr, _.info128, _.info128>,
890 avx512_broadcast_scalar<opc, OpcodeStr, _.info128, _.info128>,
894 defm VBROADCASTSS : avx512_fp_broadcast_ss<0x18, "vbroadcastss",
896 defm VBROADCASTSD : avx512_fp_broadcast_sd<0x19, "vbroadcastsd",
897 avx512vl_f64_info>, VEX_W;
899 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
900 (VBROADCASTSSZm addr:$src)>;
901 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
902 (VBROADCASTSDZm addr:$src)>;
904 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
905 RegisterClass SrcRC> {
906 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
908 "vpbroadcast"##_.Suffix, "$src", "$src",
909 (_.VT (X86VBroadcast SrcRC:$src))>, T8PD, EVEX;
912 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
913 RegisterClass SrcRC, Predicate prd> {
914 let Predicates = [prd] in
915 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
916 let Predicates = [prd, HasVLX] in {
917 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
918 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
922 let isCodeGenOnly = 1 in {
923 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR8,
925 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR16,
928 let isAsmParserOnly = 1 in {
929 defm VPBROADCASTBr_Alt : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info,
931 defm VPBROADCASTWr_Alt : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info,
934 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
936 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
939 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
940 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
941 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
942 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
944 // Provide aliases for broadcast from the same register class that
945 // automatically does the extract.
946 multiclass avx512_int_broadcast_rm_lowering<X86VectorVTInfo DestInfo,
947 X86VectorVTInfo SrcInfo> {
948 def : Pat<(DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))),
949 (!cast<Instruction>(NAME#DestInfo.ZSuffix#"r")
950 (EXTRACT_SUBREG (SrcInfo.VT SrcInfo.RC:$src), sub_xmm))>;
953 multiclass avx512_int_broadcast_rm_vl<bits<8> opc, string OpcodeStr,
954 AVX512VLVectorVTInfo _, Predicate prd> {
955 let Predicates = [prd] in {
956 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
957 avx512_int_broadcast_rm_lowering<_.info512, _.info256>,
959 // Defined separately to avoid redefinition.
960 defm Z_Alt : avx512_int_broadcast_rm_lowering<_.info512, _.info512>;
962 let Predicates = [prd, HasVLX] in {
963 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
964 avx512_int_broadcast_rm_lowering<_.info256, _.info256>,
966 defm Z128 : avx512_broadcast_rm<opc, OpcodeStr, _.info128, _.info128>,
971 defm VPBROADCASTB : avx512_int_broadcast_rm_vl<0x78, "vpbroadcastb",
972 avx512vl_i8_info, HasBWI>;
973 defm VPBROADCASTW : avx512_int_broadcast_rm_vl<0x79, "vpbroadcastw",
974 avx512vl_i16_info, HasBWI>;
975 defm VPBROADCASTD : avx512_int_broadcast_rm_vl<0x58, "vpbroadcastd",
976 avx512vl_i32_info, HasAVX512>;
977 defm VPBROADCASTQ : avx512_int_broadcast_rm_vl<0x59, "vpbroadcastq",
978 avx512vl_i64_info, HasAVX512>, VEX_W;
980 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
981 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
982 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
983 (ins _Src.MemOp:$src), OpcodeStr, "$src", "$src",
984 (_Dst.VT (X86SubVBroadcast
985 (_Src.VT (bitconvert (_Src.LdFrag addr:$src)))))>,
989 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
990 v16i32_info, v4i32x_info>,
991 EVEX_V512, EVEX_CD8<32, CD8VT4>;
992 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
993 v16f32_info, v4f32x_info>,
994 EVEX_V512, EVEX_CD8<32, CD8VT4>;
995 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
996 v8i64_info, v4i64x_info>, VEX_W,
997 EVEX_V512, EVEX_CD8<64, CD8VT4>;
998 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
999 v8f64_info, v4f64x_info>, VEX_W,
1000 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1002 let Predicates = [HasVLX] in {
1003 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1004 v8i32x_info, v4i32x_info>,
1005 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1006 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1007 v8f32x_info, v4f32x_info>,
1008 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1010 let Predicates = [HasVLX, HasDQI] in {
1011 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1012 v4i64x_info, v2i64x_info>, VEX_W,
1013 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1014 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1015 v4f64x_info, v2f64x_info>, VEX_W,
1016 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1018 let Predicates = [HasDQI] in {
1019 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1020 v8i64_info, v2i64x_info>, VEX_W,
1021 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1022 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
1023 v16i32_info, v8i32x_info>,
1024 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1025 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1026 v8f64_info, v2f64x_info>, VEX_W,
1027 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1028 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
1029 v16f32_info, v8f32x_info>,
1030 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1033 multiclass avx512_common_broadcast_32x2<bits<8> opc, string OpcodeStr,
1034 AVX512VLVectorVTInfo _Dst, AVX512VLVectorVTInfo _Src> {
1035 let Predicates = [HasDQI] in
1036 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _Dst.info512, _Src.info128>,
1038 let Predicates = [HasDQI, HasVLX] in
1039 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _Dst.info256, _Src.info128>,
1043 multiclass avx512_common_broadcast_i32x2<bits<8> opc, string OpcodeStr,
1044 AVX512VLVectorVTInfo _Dst, AVX512VLVectorVTInfo _Src> :
1045 avx512_common_broadcast_32x2<opc, OpcodeStr, _Dst, _Src> {
1047 let Predicates = [HasDQI, HasVLX] in
1048 defm Z128 : avx512_broadcast_rm<opc, OpcodeStr, _Dst.info128, _Src.info128>,
1052 defm VPBROADCASTI32X2 : avx512_common_broadcast_i32x2<0x59, "vbroadcasti32x2",
1053 avx512vl_i32_info, avx512vl_i64_info>;
1054 defm VPBROADCASTF32X2 : avx512_common_broadcast_32x2<0x19, "vbroadcastf32x2",
1055 avx512vl_f32_info, avx512vl_f64_info>;
1057 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
1058 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
1059 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
1060 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
1062 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
1063 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
1064 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
1065 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
1067 //===----------------------------------------------------------------------===//
1068 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
1070 multiclass avx512_mask_broadcastm<bits<8> opc, string OpcodeStr,
1071 X86VectorVTInfo _, RegisterClass KRC> {
1072 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.RC:$dst), (ins KRC:$src),
1073 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1074 [(set _.RC:$dst, (_.VT (X86VBroadcastm KRC:$src)))]>, EVEX;
1077 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
1078 AVX512VLVectorVTInfo VTInfo, RegisterClass KRC> {
1079 let Predicates = [HasCDI] in
1080 defm Z : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info512, KRC>, EVEX_V512;
1081 let Predicates = [HasCDI, HasVLX] in {
1082 defm Z256 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info256, KRC>, EVEX_V256;
1083 defm Z128 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info128, KRC>, EVEX_V128;
1087 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
1088 avx512vl_i32_info, VK16>;
1089 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1090 avx512vl_i64_info, VK8>, VEX_W;
1092 //===----------------------------------------------------------------------===//
1093 // -- VPERMI2 - 3 source operands form --
1094 multiclass avx512_perm_i<bits<8> opc, string OpcodeStr,
1095 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1096 let Constraints = "$src1 = $dst" in {
1097 defm rr: AVX512_maskable_3src_cast<opc, MRMSrcReg, _, IdxVT, (outs _.RC:$dst),
1098 (ins _.RC:$src2, _.RC:$src3),
1099 OpcodeStr, "$src3, $src2", "$src2, $src3",
1100 (_.VT (X86VPermi2X IdxVT.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
1103 defm rm: AVX512_maskable_3src_cast<opc, MRMSrcMem, _, IdxVT, (outs _.RC:$dst),
1104 (ins _.RC:$src2, _.MemOp:$src3),
1105 OpcodeStr, "$src3, $src2", "$src2, $src3",
1106 (_.VT (X86VPermi2X IdxVT.RC:$src1, _.RC:$src2,
1107 (_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
1108 EVEX_4V, AVX5128IBase;
1111 multiclass avx512_perm_i_mb<bits<8> opc, string OpcodeStr,
1112 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1113 let Constraints = "$src1 = $dst" in
1114 defm rmb: AVX512_maskable_3src_cast<opc, MRMSrcMem, _, IdxVT, (outs _.RC:$dst),
1115 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1116 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1117 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1118 (_.VT (X86VPermi2X IdxVT.RC:$src1,
1119 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1120 AVX5128IBase, EVEX_4V, EVEX_B;
1123 multiclass avx512_perm_i_sizes<bits<8> opc, string OpcodeStr,
1124 AVX512VLVectorVTInfo VTInfo,
1125 AVX512VLVectorVTInfo ShuffleMask> {
1126 defm NAME: avx512_perm_i<opc, OpcodeStr, VTInfo.info512,
1127 ShuffleMask.info512>,
1128 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info512,
1129 ShuffleMask.info512>, EVEX_V512;
1130 let Predicates = [HasVLX] in {
1131 defm NAME#128: avx512_perm_i<opc, OpcodeStr, VTInfo.info128,
1132 ShuffleMask.info128>,
1133 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info128,
1134 ShuffleMask.info128>, EVEX_V128;
1135 defm NAME#256: avx512_perm_i<opc, OpcodeStr, VTInfo.info256,
1136 ShuffleMask.info256>,
1137 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info256,
1138 ShuffleMask.info256>, EVEX_V256;
1142 multiclass avx512_perm_i_sizes_bw<bits<8> opc, string OpcodeStr,
1143 AVX512VLVectorVTInfo VTInfo,
1144 AVX512VLVectorVTInfo Idx,
1146 let Predicates = [Prd] in
1147 defm NAME: avx512_perm_i<opc, OpcodeStr, VTInfo.info512,
1148 Idx.info512>, EVEX_V512;
1149 let Predicates = [Prd, HasVLX] in {
1150 defm NAME#128: avx512_perm_i<opc, OpcodeStr, VTInfo.info128,
1151 Idx.info128>, EVEX_V128;
1152 defm NAME#256: avx512_perm_i<opc, OpcodeStr, VTInfo.info256,
1153 Idx.info256>, EVEX_V256;
1157 defm VPERMI2D : avx512_perm_i_sizes<0x76, "vpermi2d",
1158 avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1159 defm VPERMI2Q : avx512_perm_i_sizes<0x76, "vpermi2q",
1160 avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1161 defm VPERMI2W : avx512_perm_i_sizes_bw<0x75, "vpermi2w",
1162 avx512vl_i16_info, avx512vl_i16_info, HasBWI>,
1163 VEX_W, EVEX_CD8<16, CD8VF>;
1164 defm VPERMI2B : avx512_perm_i_sizes_bw<0x75, "vpermi2b",
1165 avx512vl_i8_info, avx512vl_i8_info, HasVBMI>,
1167 defm VPERMI2PS : avx512_perm_i_sizes<0x77, "vpermi2ps",
1168 avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1169 defm VPERMI2PD : avx512_perm_i_sizes<0x77, "vpermi2pd",
1170 avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1173 multiclass avx512_perm_t<bits<8> opc, string OpcodeStr,
1174 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1175 let Constraints = "$src1 = $dst" in {
1176 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1177 (ins IdxVT.RC:$src2, _.RC:$src3),
1178 OpcodeStr, "$src3, $src2", "$src2, $src3",
1179 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2, _.RC:$src3))>, EVEX_4V,
1182 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1183 (ins IdxVT.RC:$src2, _.MemOp:$src3),
1184 OpcodeStr, "$src3, $src2", "$src2, $src3",
1185 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2,
1186 (bitconvert (_.LdFrag addr:$src3))))>,
1187 EVEX_4V, AVX5128IBase;
1190 multiclass avx512_perm_t_mb<bits<8> opc, string OpcodeStr,
1191 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1192 let Constraints = "$src1 = $dst" in
1193 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1194 (ins IdxVT.RC:$src2, _.ScalarMemOp:$src3),
1195 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1196 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1197 (_.VT (X86VPermt2 _.RC:$src1,
1198 IdxVT.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1199 AVX5128IBase, EVEX_4V, EVEX_B;
1202 multiclass avx512_perm_t_sizes<bits<8> opc, string OpcodeStr,
1203 AVX512VLVectorVTInfo VTInfo,
1204 AVX512VLVectorVTInfo ShuffleMask> {
1205 defm NAME: avx512_perm_t<opc, OpcodeStr, VTInfo.info512,
1206 ShuffleMask.info512>,
1207 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info512,
1208 ShuffleMask.info512>, EVEX_V512;
1209 let Predicates = [HasVLX] in {
1210 defm NAME#128: avx512_perm_t<opc, OpcodeStr, VTInfo.info128,
1211 ShuffleMask.info128>,
1212 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info128,
1213 ShuffleMask.info128>, EVEX_V128;
1214 defm NAME#256: avx512_perm_t<opc, OpcodeStr, VTInfo.info256,
1215 ShuffleMask.info256>,
1216 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info256,
1217 ShuffleMask.info256>, EVEX_V256;
1221 multiclass avx512_perm_t_sizes_bw<bits<8> opc, string OpcodeStr,
1222 AVX512VLVectorVTInfo VTInfo,
1223 AVX512VLVectorVTInfo Idx,
1225 let Predicates = [Prd] in
1226 defm NAME: avx512_perm_t<opc, OpcodeStr, VTInfo.info512,
1227 Idx.info512>, EVEX_V512;
1228 let Predicates = [Prd, HasVLX] in {
1229 defm NAME#128: avx512_perm_t<opc, OpcodeStr, VTInfo.info128,
1230 Idx.info128>, EVEX_V128;
1231 defm NAME#256: avx512_perm_t<opc, OpcodeStr, VTInfo.info256,
1232 Idx.info256>, EVEX_V256;
1236 defm VPERMT2D : avx512_perm_t_sizes<0x7E, "vpermt2d",
1237 avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1238 defm VPERMT2Q : avx512_perm_t_sizes<0x7E, "vpermt2q",
1239 avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1240 defm VPERMT2W : avx512_perm_t_sizes_bw<0x7D, "vpermt2w",
1241 avx512vl_i16_info, avx512vl_i16_info, HasBWI>,
1242 VEX_W, EVEX_CD8<16, CD8VF>;
1243 defm VPERMT2B : avx512_perm_t_sizes_bw<0x7D, "vpermt2b",
1244 avx512vl_i8_info, avx512vl_i8_info, HasVBMI>,
1246 defm VPERMT2PS : avx512_perm_t_sizes<0x7F, "vpermt2ps",
1247 avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1248 defm VPERMT2PD : avx512_perm_t_sizes<0x7F, "vpermt2pd",
1249 avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1251 //===----------------------------------------------------------------------===//
1252 // AVX-512 - BLEND using mask
1254 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1255 let ExeDomain = _.ExeDomain in {
1256 let hasSideEffects = 0 in
1257 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1258 (ins _.RC:$src1, _.RC:$src2),
1259 !strconcat(OpcodeStr,
1260 "\t{$src2, $src1, ${dst}|${dst}, $src1, $src2}"),
1262 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1263 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1264 !strconcat(OpcodeStr,
1265 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1266 [(set _.RC:$dst, (vselect _.KRCWM:$mask,
1268 (_.VT _.RC:$src1)))]>, EVEX_4V, EVEX_K;
1269 let hasSideEffects = 0 in
1270 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1271 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1272 !strconcat(OpcodeStr,
1273 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1274 []>, EVEX_4V, EVEX_KZ;
1275 let mayLoad = 1, hasSideEffects = 0 in
1276 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1277 (ins _.RC:$src1, _.MemOp:$src2),
1278 !strconcat(OpcodeStr,
1279 "\t{$src2, $src1, ${dst}|${dst}, $src1, $src2}"),
1280 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1281 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1282 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1283 !strconcat(OpcodeStr,
1284 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1285 [(set _.RC:$dst, (vselect _.KRCWM:$mask,
1286 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1287 (_.VT _.RC:$src1)))]>,
1288 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1289 let mayLoad = 1, hasSideEffects = 0 in
1290 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1291 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1292 !strconcat(OpcodeStr,
1293 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1294 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1297 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1299 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1300 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1301 !strconcat(OpcodeStr,
1302 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1303 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1304 [(set _.RC:$dst,(vselect _.KRCWM:$mask,
1305 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1306 (_.VT _.RC:$src1)))]>,
1307 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1309 let mayLoad = 1, hasSideEffects = 0 in
1310 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1311 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1312 !strconcat(OpcodeStr,
1313 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1314 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1315 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1319 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1320 AVX512VLVectorVTInfo VTInfo> {
1321 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1322 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1324 let Predicates = [HasVLX] in {
1325 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1326 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1327 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1328 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1332 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1333 AVX512VLVectorVTInfo VTInfo> {
1334 let Predicates = [HasBWI] in
1335 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1337 let Predicates = [HasBWI, HasVLX] in {
1338 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1339 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1344 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1345 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1346 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1347 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1348 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1349 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1352 let Predicates = [HasAVX512, NoVLX] in {
1353 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1354 (v8f32 VR256X:$src2))),
1356 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1357 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1358 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1360 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1361 (v8i32 VR256X:$src2))),
1363 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1364 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1365 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1367 //===----------------------------------------------------------------------===//
1368 // Compare Instructions
1369 //===----------------------------------------------------------------------===//
1371 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1373 multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>{
1375 defm rr_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1377 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1378 "vcmp${cc}"#_.Suffix,
1379 "$src2, $src1", "$src1, $src2",
1380 (OpNode (_.VT _.RC:$src1),
1383 defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1385 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1386 "vcmp${cc}"#_.Suffix,
1387 "$src2, $src1", "$src1, $src2",
1388 (OpNode (_.VT _.RC:$src1),
1389 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
1390 imm:$cc)>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1392 defm rrb_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1394 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1395 "vcmp${cc}"#_.Suffix,
1396 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
1397 (OpNodeRnd (_.VT _.RC:$src1),
1400 (i32 FROUND_NO_EXC))>, EVEX_4V, EVEX_B;
1401 // Accept explicit immediate argument form instead of comparison code.
1402 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1403 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1405 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1407 "$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V;
1408 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1410 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1412 "$cc, $src2, $src1", "$src1, $src2, $cc">,
1413 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1415 defm rrb_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1417 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1419 "$cc, {sae}, $src2, $src1","$src1, $src2, {sae}, $cc">,
1421 }// let isAsmParserOnly = 1, hasSideEffects = 0
1423 let isCodeGenOnly = 1 in {
1424 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1425 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc),
1426 !strconcat("vcmp${cc}", _.Suffix,
1427 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1428 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1431 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1432 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1434 (ins _.FRC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1435 !strconcat("vcmp${cc}", _.Suffix,
1436 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1437 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1438 (_.ScalarLdFrag addr:$src2),
1440 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1444 let Predicates = [HasAVX512] in {
1445 defm VCMPSSZ : avx512_cmp_scalar<f32x_info, X86cmpms, X86cmpmsRnd>,
1447 defm VCMPSDZ : avx512_cmp_scalar<f64x_info, X86cmpms, X86cmpmsRnd>,
1448 AVX512XDIi8Base, VEX_W;
1451 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1452 X86VectorVTInfo _> {
1453 def rr : AVX512BI<opc, MRMSrcReg,
1454 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1455 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1456 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1457 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1458 def rm : AVX512BI<opc, MRMSrcMem,
1459 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1460 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1461 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1462 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1463 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1464 def rrk : AVX512BI<opc, MRMSrcReg,
1465 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1466 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1467 "$dst {${mask}}, $src1, $src2}"),
1468 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1469 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1470 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1471 def rmk : AVX512BI<opc, MRMSrcMem,
1472 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1473 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1474 "$dst {${mask}}, $src1, $src2}"),
1475 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1476 (OpNode (_.VT _.RC:$src1),
1478 (_.LdFrag addr:$src2))))))],
1479 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1482 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1483 X86VectorVTInfo _> :
1484 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1485 def rmb : AVX512BI<opc, MRMSrcMem,
1486 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1487 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1488 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1489 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1490 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1491 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1492 def rmbk : AVX512BI<opc, MRMSrcMem,
1493 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1494 _.ScalarMemOp:$src2),
1495 !strconcat(OpcodeStr,
1496 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1497 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1498 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1499 (OpNode (_.VT _.RC:$src1),
1501 (_.ScalarLdFrag addr:$src2)))))],
1502 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1505 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1506 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1507 let Predicates = [prd] in
1508 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1511 let Predicates = [prd, HasVLX] in {
1512 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1514 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1519 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1520 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1522 let Predicates = [prd] in
1523 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1526 let Predicates = [prd, HasVLX] in {
1527 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1529 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1534 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1535 avx512vl_i8_info, HasBWI>,
1538 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1539 avx512vl_i16_info, HasBWI>,
1540 EVEX_CD8<16, CD8VF>;
1542 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1543 avx512vl_i32_info, HasAVX512>,
1544 EVEX_CD8<32, CD8VF>;
1546 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1547 avx512vl_i64_info, HasAVX512>,
1548 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1550 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1551 avx512vl_i8_info, HasBWI>,
1554 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1555 avx512vl_i16_info, HasBWI>,
1556 EVEX_CD8<16, CD8VF>;
1558 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1559 avx512vl_i32_info, HasAVX512>,
1560 EVEX_CD8<32, CD8VF>;
1562 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1563 avx512vl_i64_info, HasAVX512>,
1564 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1566 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1567 (COPY_TO_REGCLASS (VPCMPGTDZrr
1568 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1569 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1571 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1572 (COPY_TO_REGCLASS (VPCMPEQDZrr
1573 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1574 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1576 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1577 X86VectorVTInfo _> {
1578 def rri : AVX512AIi8<opc, MRMSrcReg,
1579 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1580 !strconcat("vpcmp${cc}", Suffix,
1581 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1582 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1584 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1585 def rmi : AVX512AIi8<opc, MRMSrcMem,
1586 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1587 !strconcat("vpcmp${cc}", Suffix,
1588 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1589 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1590 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1592 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1593 def rrik : AVX512AIi8<opc, MRMSrcReg,
1594 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1596 !strconcat("vpcmp${cc}", Suffix,
1597 "\t{$src2, $src1, $dst {${mask}}|",
1598 "$dst {${mask}}, $src1, $src2}"),
1599 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1600 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1602 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1603 def rmik : AVX512AIi8<opc, MRMSrcMem,
1604 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1606 !strconcat("vpcmp${cc}", Suffix,
1607 "\t{$src2, $src1, $dst {${mask}}|",
1608 "$dst {${mask}}, $src1, $src2}"),
1609 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1610 (OpNode (_.VT _.RC:$src1),
1611 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1613 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1615 // Accept explicit immediate argument form instead of comparison code.
1616 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1617 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1618 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1619 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1620 "$dst, $src1, $src2, $cc}"),
1621 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1623 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1624 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1625 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1626 "$dst, $src1, $src2, $cc}"),
1627 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1628 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1629 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1631 !strconcat("vpcmp", Suffix,
1632 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1633 "$dst {${mask}}, $src1, $src2, $cc}"),
1634 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1636 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1637 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1639 !strconcat("vpcmp", Suffix,
1640 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1641 "$dst {${mask}}, $src1, $src2, $cc}"),
1642 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1646 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1647 X86VectorVTInfo _> :
1648 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1649 def rmib : AVX512AIi8<opc, MRMSrcMem,
1650 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1652 !strconcat("vpcmp${cc}", Suffix,
1653 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1654 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1655 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1656 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1658 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1659 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1660 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1661 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1662 !strconcat("vpcmp${cc}", Suffix,
1663 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1664 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1665 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1666 (OpNode (_.VT _.RC:$src1),
1667 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1669 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1671 // Accept explicit immediate argument form instead of comparison code.
1672 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1673 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1674 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1676 !strconcat("vpcmp", Suffix,
1677 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1678 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1679 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1680 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1681 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1682 _.ScalarMemOp:$src2, u8imm:$cc),
1683 !strconcat("vpcmp", Suffix,
1684 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1685 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1686 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1690 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1691 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1692 let Predicates = [prd] in
1693 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1695 let Predicates = [prd, HasVLX] in {
1696 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1697 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1701 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1702 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1703 let Predicates = [prd] in
1704 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1707 let Predicates = [prd, HasVLX] in {
1708 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1710 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1715 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1716 HasBWI>, EVEX_CD8<8, CD8VF>;
1717 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1718 HasBWI>, EVEX_CD8<8, CD8VF>;
1720 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1721 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1722 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1723 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1725 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1726 HasAVX512>, EVEX_CD8<32, CD8VF>;
1727 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1728 HasAVX512>, EVEX_CD8<32, CD8VF>;
1730 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1731 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1732 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1733 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1735 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1737 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1738 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1739 "vcmp${cc}"#_.Suffix,
1740 "$src2, $src1", "$src1, $src2",
1741 (X86cmpm (_.VT _.RC:$src1),
1745 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1746 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1747 "vcmp${cc}"#_.Suffix,
1748 "$src2, $src1", "$src1, $src2",
1749 (X86cmpm (_.VT _.RC:$src1),
1750 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1753 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1755 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1756 "vcmp${cc}"#_.Suffix,
1757 "${src2}"##_.BroadcastStr##", $src1",
1758 "$src1, ${src2}"##_.BroadcastStr,
1759 (X86cmpm (_.VT _.RC:$src1),
1760 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1762 // Accept explicit immediate argument form instead of comparison code.
1763 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1764 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1766 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1768 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1770 let mayLoad = 1 in {
1771 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1773 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1775 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1777 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1779 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1781 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1782 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1787 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1788 // comparison code form (VCMP[EQ/LT/LE/...]
1789 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1790 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1791 "vcmp${cc}"#_.Suffix,
1792 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
1793 (X86cmpmRnd (_.VT _.RC:$src1),
1796 (i32 FROUND_NO_EXC))>, EVEX_B;
1798 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1799 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1801 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1803 "$cc, {sae}, $src2, $src1",
1804 "$src1, $src2, {sae}, $cc">, EVEX_B;
1808 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1809 let Predicates = [HasAVX512] in {
1810 defm Z : avx512_vcmp_common<_.info512>,
1811 avx512_vcmp_sae<_.info512>, EVEX_V512;
1814 let Predicates = [HasAVX512,HasVLX] in {
1815 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1816 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1820 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1821 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1822 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1823 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1825 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1826 (COPY_TO_REGCLASS (VCMPPSZrri
1827 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1828 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1830 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1831 (COPY_TO_REGCLASS (VPCMPDZrri
1832 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1833 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1835 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1836 (COPY_TO_REGCLASS (VPCMPUDZrri
1837 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1838 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1841 // ----------------------------------------------------------------
1843 //handle fpclass instruction mask = op(reg_scalar,imm)
1844 // op(mem_scalar,imm)
1845 multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1846 X86VectorVTInfo _, Predicate prd> {
1847 let Predicates = [prd] in {
1848 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),//_.KRC:$dst),
1849 (ins _.RC:$src1, i32u8imm:$src2),
1850 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1851 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1852 (i32 imm:$src2)))], NoItinerary>;
1853 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1854 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1855 OpcodeStr##_.Suffix#
1856 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
1857 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1858 (OpNode (_.VT _.RC:$src1),
1859 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1860 let AddedComplexity = 20 in {
1861 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1862 (ins _.MemOp:$src1, i32u8imm:$src2),
1863 OpcodeStr##_.Suffix##
1864 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1866 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1867 (i32 imm:$src2)))], NoItinerary>;
1868 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1869 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1870 OpcodeStr##_.Suffix##
1871 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
1872 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1873 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1874 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1879 //handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm)
1880 // fpclass(reg_vec, mem_vec, imm)
1881 // fpclass(reg_vec, broadcast(eltVt), imm)
1882 multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1883 X86VectorVTInfo _, string mem, string broadcast>{
1884 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1885 (ins _.RC:$src1, i32u8imm:$src2),
1886 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1887 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1888 (i32 imm:$src2)))], NoItinerary>;
1889 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1890 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1891 OpcodeStr##_.Suffix#
1892 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
1893 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1894 (OpNode (_.VT _.RC:$src1),
1895 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1896 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1897 (ins _.MemOp:$src1, i32u8imm:$src2),
1898 OpcodeStr##_.Suffix##mem#
1899 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1900 [(set _.KRC:$dst,(OpNode
1901 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1902 (i32 imm:$src2)))], NoItinerary>;
1903 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1904 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1905 OpcodeStr##_.Suffix##mem#
1906 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
1907 [(set _.KRC:$dst, (or _.KRCWM:$mask, (OpNode
1908 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1909 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1910 def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1911 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
1912 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1913 _.BroadcastStr##", $dst|$dst, ${src1}"
1914 ##_.BroadcastStr##", $src2}",
1915 [(set _.KRC:$dst,(OpNode
1916 (_.VT (X86VBroadcast
1917 (_.ScalarLdFrag addr:$src1))),
1918 (i32 imm:$src2)))], NoItinerary>,EVEX_B;
1919 def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1920 (ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
1921 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1922 _.BroadcastStr##", $dst {${mask}}|$dst {${mask}}, ${src1}"##
1923 _.BroadcastStr##", $src2}",
1924 [(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode
1925 (_.VT (X86VBroadcast
1926 (_.ScalarLdFrag addr:$src1))),
1927 (i32 imm:$src2))))], NoItinerary>,
1931 multiclass avx512_vector_fpclass_all<string OpcodeStr,
1932 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd,
1934 let Predicates = [prd] in {
1935 defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info512, "{z}",
1936 broadcast>, EVEX_V512;
1938 let Predicates = [prd, HasVLX] in {
1939 defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info128, "{x}",
1940 broadcast>, EVEX_V128;
1941 defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info256, "{y}",
1942 broadcast>, EVEX_V256;
1946 multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
1947 bits<8> opcScalar, SDNode VecOpNode, SDNode ScalarOpNode, Predicate prd>{
1948 defm PS : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f32_info, opcVec,
1949 VecOpNode, prd, "{l}">, EVEX_CD8<32, CD8VF>;
1950 defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec,
1951 VecOpNode, prd, "{q}">,EVEX_CD8<64, CD8VF> , VEX_W;
1952 defm SS : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
1953 f32x_info, prd>, EVEX_CD8<32, CD8VT1>;
1954 defm SD : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
1955 f64x_info, prd>, EVEX_CD8<64, CD8VT1>, VEX_W;
1958 defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass,
1959 X86Vfpclasss, HasDQI>, AVX512AIi8Base,EVEX;
1961 //-----------------------------------------------------------------
1962 // Mask register copy, including
1963 // - copy between mask registers
1964 // - load/store mask registers
1965 // - copy from GPR to mask register and vice versa
1967 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1968 string OpcodeStr, RegisterClass KRC,
1969 ValueType vvt, X86MemOperand x86memop> {
1970 let hasSideEffects = 0 in
1971 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1972 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1973 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1974 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1975 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1976 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1977 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1978 [(store KRC:$src, addr:$dst)]>;
1981 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1983 RegisterClass KRC, RegisterClass GRC> {
1984 let hasSideEffects = 0 in {
1985 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1986 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1987 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1988 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1992 let Predicates = [HasDQI] in
1993 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1994 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1997 let Predicates = [HasAVX512] in
1998 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1999 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
2002 let Predicates = [HasBWI] in {
2003 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
2005 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
2007 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
2009 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
2013 // GR from/to mask register
2014 let Predicates = [HasDQI] in {
2015 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2016 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
2017 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2018 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
2019 def : Pat<(i32 (zext (i8 (bitconvert (v8i1 VK8:$src))))),
2020 (KMOVBrk VK8:$src)>;
2021 def : Pat<(i32 (anyext (i8 (bitconvert (v8i1 VK8:$src))))),
2022 (KMOVBrk VK8:$src)>;
2024 let Predicates = [HasAVX512] in {
2025 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
2026 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
2027 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
2028 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
2029 def : Pat<(i32 (zext (i16 (bitconvert (v16i1 VK16:$src))))),
2030 (KMOVWrk VK16:$src)>;
2031 def : Pat<(i32 (anyext (i16 (bitconvert (v16i1 VK16:$src))))),
2032 (KMOVWrk VK16:$src)>;
2034 let Predicates = [HasBWI] in {
2035 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
2036 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
2038 let Predicates = [HasBWI] in {
2039 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
2040 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
2044 let Predicates = [HasDQI] in {
2045 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2046 (KMOVBmk addr:$dst, VK8:$src)>;
2047 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2048 (KMOVBkm addr:$src)>;
2050 def : Pat<(store VK4:$src, addr:$dst),
2051 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
2052 def : Pat<(store VK2:$src, addr:$dst),
2053 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK2:$src, VK8))>;
2054 def : Pat<(store VK1:$src, addr:$dst),
2055 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK8))>;
2057 def : Pat<(v2i1 (load addr:$src)),
2058 (COPY_TO_REGCLASS (KMOVBkm addr:$src), VK2)>;
2059 def : Pat<(v4i1 (load addr:$src)),
2060 (COPY_TO_REGCLASS (KMOVBkm addr:$src), VK4)>;
2062 let Predicates = [HasAVX512, NoDQI] in {
2063 def : Pat<(store VK1:$src, addr:$dst),
2065 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
2067 def : Pat<(store VK2:$src, addr:$dst),
2069 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK2:$src, VK16)),
2071 def : Pat<(store VK4:$src, addr:$dst),
2073 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK4:$src, VK16)),
2075 def : Pat<(store VK8:$src, addr:$dst),
2077 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
2080 def : Pat<(v8i1 (load addr:$src)),
2081 (COPY_TO_REGCLASS (MOVZX32rm8 addr:$src), VK8)>;
2082 def : Pat<(v2i1 (load addr:$src)),
2083 (COPY_TO_REGCLASS (MOVZX32rm8 addr:$src), VK2)>;
2084 def : Pat<(v4i1 (load addr:$src)),
2085 (COPY_TO_REGCLASS (MOVZX32rm8 addr:$src), VK4)>;
2088 let Predicates = [HasAVX512] in {
2089 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
2090 (KMOVWmk addr:$dst, VK16:$src)>;
2091 def : Pat<(i1 (load addr:$src)),
2092 (COPY_TO_REGCLASS (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1)), VK1)>;
2093 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
2094 (KMOVWkm addr:$src)>;
2096 let Predicates = [HasBWI] in {
2097 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
2098 (KMOVDmk addr:$dst, VK32:$src)>;
2099 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
2100 (KMOVDkm addr:$src)>;
2101 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
2102 (KMOVQmk addr:$dst, VK64:$src)>;
2103 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
2104 (KMOVQkm addr:$src)>;
2107 def assertzext_i1 : PatFrag<(ops node:$src), (assertzext node:$src), [{
2108 return cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i1;
2111 let Predicates = [HasAVX512] in {
2112 def : Pat<(i1 (trunc (i64 GR64:$src))),
2113 (COPY_TO_REGCLASS (i16 (EXTRACT_SUBREG (AND64ri8 $src, (i64 1)),
2116 def : Pat<(i1 (trunc (i64 (assertzext_i1 GR64:$src)))),
2117 (COPY_TO_REGCLASS (i16 (EXTRACT_SUBREG $src, sub_16bit)), VK1)>;
2119 def : Pat<(i1 (trunc (i32 GR32:$src))),
2120 (COPY_TO_REGCLASS (i16 (EXTRACT_SUBREG (AND32ri8 $src, (i32 1)),
2123 def : Pat<(i1 (trunc (i32 (assertzext_i1 GR32:$src)))),
2124 (COPY_TO_REGCLASS (i16 (EXTRACT_SUBREG $src, sub_16bit)), VK1)>;
2126 def : Pat<(i1 (trunc (i8 GR8:$src))),
2127 (COPY_TO_REGCLASS (i16 (SUBREG_TO_REG (i64 0), (AND8ri $src, (i8 1)),
2130 def : Pat<(i1 (trunc (i8 (assertzext_i1 GR8:$src)))),
2131 (COPY_TO_REGCLASS (i16 (SUBREG_TO_REG (i64 0), $src, sub_8bit)), VK1)>;
2133 def : Pat<(i1 (trunc (i16 GR16:$src))),
2134 (COPY_TO_REGCLASS (AND16ri GR16:$src, (i16 1)), VK1)>;
2136 def : Pat<(i1 (trunc (i16 (assertzext_i1 GR16:$src)))),
2137 (COPY_TO_REGCLASS $src, VK1)>;
2139 def : Pat<(i32 (zext VK1:$src)),
2140 (i32 (SUBREG_TO_REG (i64 0), (i16 (COPY_TO_REGCLASS $src, GR16)),
2143 def : Pat<(i32 (anyext VK1:$src)),
2144 (i32 (SUBREG_TO_REG (i64 0), (i16 (COPY_TO_REGCLASS $src, GR16)),
2147 def : Pat<(i8 (zext VK1:$src)),
2148 (i8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS VK1:$src, GR16)), sub_8bit))>;
2150 def : Pat<(i8 (anyext VK1:$src)),
2151 (i8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS $src, GR16)), sub_8bit))>;
2153 def : Pat<(i64 (zext VK1:$src)),
2154 (i64 (SUBREG_TO_REG (i64 0), (i16 (COPY_TO_REGCLASS $src, GR16)),
2157 def : Pat<(i64 (anyext VK1:$src)),
2158 (i64 (SUBREG_TO_REG (i64 0), (i16 (COPY_TO_REGCLASS $src, GR16)),
2161 def : Pat<(i16 (zext VK1:$src)),
2162 (COPY_TO_REGCLASS $src, GR16)>;
2164 def : Pat<(i16 (anyext VK1:$src)),
2165 (i16 (COPY_TO_REGCLASS $src, GR16))>;
2167 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
2168 (COPY_TO_REGCLASS VK1:$src, VK16)>;
2169 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
2170 (COPY_TO_REGCLASS VK1:$src, VK8)>;
2171 def : Pat<(v4i1 (scalar_to_vector VK1:$src)),
2172 (COPY_TO_REGCLASS VK1:$src, VK4)>;
2173 def : Pat<(v2i1 (scalar_to_vector VK1:$src)),
2174 (COPY_TO_REGCLASS VK1:$src, VK2)>;
2175 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
2176 (COPY_TO_REGCLASS VK1:$src, VK32)>;
2177 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
2178 (COPY_TO_REGCLASS VK1:$src, VK64)>;
2180 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
2181 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
2182 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
2184 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2185 let Predicates = [HasAVX512, NoDQI] in {
2186 // GR from/to 8-bit mask without native support
2187 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2189 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)), VK8)>;
2190 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2192 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
2194 def : Pat<(i32 (zext (i8 (bitconvert (v8i1 VK8:$src))))),
2195 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16))>;
2196 def : Pat<(i32 (anyext (i8 (bitconvert (v8i1 VK8:$src))))),
2197 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16))>;
2200 let Predicates = [HasAVX512] in {
2201 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
2202 (COPY_TO_REGCLASS VK16:$src, VK1)>;
2203 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
2204 (COPY_TO_REGCLASS VK8:$src, VK1)>;
2206 let Predicates = [HasBWI] in {
2207 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
2208 (COPY_TO_REGCLASS VK32:$src, VK1)>;
2209 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
2210 (COPY_TO_REGCLASS VK64:$src, VK1)>;
2213 // Mask unary operation
2215 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
2216 RegisterClass KRC, SDPatternOperator OpNode,
2218 let Predicates = [prd] in
2219 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2220 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2221 [(set KRC:$dst, (OpNode KRC:$src))]>;
2224 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
2225 SDPatternOperator OpNode> {
2226 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2228 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2229 HasAVX512>, VEX, PS;
2230 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2231 HasBWI>, VEX, PD, VEX_W;
2232 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2233 HasBWI>, VEX, PS, VEX_W;
2236 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
2238 multiclass avx512_mask_unop_int<string IntName, string InstName> {
2239 let Predicates = [HasAVX512] in
2240 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2242 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2243 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
2245 defm : avx512_mask_unop_int<"knot", "KNOT">;
2247 let Predicates = [HasDQI] in
2248 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
2249 let Predicates = [HasAVX512] in
2250 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
2251 let Predicates = [HasBWI] in
2252 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
2253 let Predicates = [HasBWI] in
2254 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
2256 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
2257 let Predicates = [HasAVX512, NoDQI] in {
2258 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
2259 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
2260 def : Pat<(not VK8:$src),
2262 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
2264 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
2265 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
2266 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
2267 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
2269 // Mask binary operation
2270 // - KAND, KANDN, KOR, KXNOR, KXOR
2271 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
2272 RegisterClass KRC, SDPatternOperator OpNode,
2273 Predicate prd, bit IsCommutable> {
2274 let Predicates = [prd], isCommutable = IsCommutable in
2275 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2276 !strconcat(OpcodeStr,
2277 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2278 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
2281 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
2282 SDPatternOperator OpNode, bit IsCommutable,
2283 Predicate prdW = HasAVX512> {
2284 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2285 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2286 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2287 prdW, IsCommutable>, VEX_4V, VEX_L, PS;
2288 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2289 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2290 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2291 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2294 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
2295 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
2297 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
2298 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
2299 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
2300 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
2301 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
2302 defm KADD : avx512_mask_binop_all<0x4A, "kadd", add, 1, HasDQI>;
2304 multiclass avx512_mask_binop_int<string IntName, string InstName> {
2305 let Predicates = [HasAVX512] in
2306 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2307 (i16 GR16:$src1), (i16 GR16:$src2)),
2308 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2309 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2310 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2313 defm : avx512_mask_binop_int<"kand", "KAND">;
2314 defm : avx512_mask_binop_int<"kandn", "KANDN">;
2315 defm : avx512_mask_binop_int<"kor", "KOR">;
2316 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
2317 defm : avx512_mask_binop_int<"kxor", "KXOR">;
2319 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
2320 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
2321 // for the DQI set, this type is legal and KxxxB instruction is used
2322 let Predicates = [NoDQI] in
2323 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2325 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2326 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2328 // All types smaller than 8 bits require conversion anyway
2329 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2330 (COPY_TO_REGCLASS (Inst
2331 (COPY_TO_REGCLASS VK1:$src1, VK16),
2332 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2333 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2334 (COPY_TO_REGCLASS (Inst
2335 (COPY_TO_REGCLASS VK2:$src1, VK16),
2336 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2337 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2338 (COPY_TO_REGCLASS (Inst
2339 (COPY_TO_REGCLASS VK4:$src1, VK16),
2340 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2343 defm : avx512_binop_pat<and, KANDWrr>;
2344 defm : avx512_binop_pat<andn, KANDNWrr>;
2345 defm : avx512_binop_pat<or, KORWrr>;
2346 defm : avx512_binop_pat<xnor, KXNORWrr>;
2347 defm : avx512_binop_pat<xor, KXORWrr>;
2349 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2350 (KXNORWrr VK16:$src1, VK16:$src2)>;
2351 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2352 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2353 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2354 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2355 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2356 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2358 let Predicates = [NoDQI] in
2359 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2360 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2361 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2363 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2364 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2365 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2367 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2368 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2369 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2371 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2372 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2373 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2376 multiclass avx512_mask_unpck<string Suffix,RegisterClass KRC, ValueType VT,
2377 RegisterClass KRCSrc, Predicate prd> {
2378 let Predicates = [prd] in {
2379 let hasSideEffects = 0 in
2380 def rr : I<0x4b, MRMSrcReg, (outs KRC:$dst),
2381 (ins KRC:$src1, KRC:$src2),
2382 "kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2385 def : Pat<(VT (concat_vectors KRCSrc:$src1, KRCSrc:$src2)),
2386 (!cast<Instruction>(NAME##rr)
2387 (COPY_TO_REGCLASS KRCSrc:$src2, KRC),
2388 (COPY_TO_REGCLASS KRCSrc:$src1, KRC))>;
2392 defm KUNPCKBW : avx512_mask_unpck<"bw", VK16, v16i1, VK8, HasAVX512>, PD;
2393 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, HasBWI>, PS;
2394 defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, HasBWI>, PS, VEX_W;
2397 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2398 SDNode OpNode, Predicate prd> {
2399 let Predicates = [prd], Defs = [EFLAGS] in
2400 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2401 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2402 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2405 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2406 Predicate prdW = HasAVX512> {
2407 defm B : avx512_mask_testop<opc, OpcodeStr#"b", VK8, OpNode, HasDQI>,
2409 defm W : avx512_mask_testop<opc, OpcodeStr#"w", VK16, OpNode, prdW>,
2411 defm Q : avx512_mask_testop<opc, OpcodeStr#"q", VK64, OpNode, HasBWI>,
2413 defm D : avx512_mask_testop<opc, OpcodeStr#"d", VK32, OpNode, HasBWI>,
2417 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2418 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest, HasDQI>;
2421 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2423 let Predicates = [HasAVX512] in
2424 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2425 !strconcat(OpcodeStr,
2426 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2427 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2430 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2432 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2434 let Predicates = [HasDQI] in
2435 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2437 let Predicates = [HasBWI] in {
2438 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2440 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2445 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2446 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2448 // Mask setting all 0s or 1s
2449 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2450 let Predicates = [HasAVX512] in
2451 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2452 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2453 [(set KRC:$dst, (VT Val))]>;
2456 multiclass avx512_mask_setop_w<PatFrag Val> {
2457 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2458 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2459 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2460 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2463 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2464 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2466 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2467 let Predicates = [HasAVX512] in {
2468 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2469 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2470 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2471 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2472 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2473 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2474 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2477 // Patterns for kmask insert_subvector/extract_subvector to/from index=0
2478 multiclass operation_subvector_mask_lowering<RegisterClass subRC, ValueType subVT,
2479 RegisterClass RC, ValueType VT> {
2480 def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))),
2481 (subVT (COPY_TO_REGCLASS RC:$src, subRC))>;
2483 def : Pat<(VT (insert_subvector undef, subRC:$src, (iPTR 0))),
2484 (VT (COPY_TO_REGCLASS subRC:$src, RC))>;
2487 defm : operation_subvector_mask_lowering<VK2, v2i1, VK4, v4i1>;
2488 defm : operation_subvector_mask_lowering<VK2, v2i1, VK8, v8i1>;
2489 defm : operation_subvector_mask_lowering<VK2, v2i1, VK16, v16i1>;
2490 defm : operation_subvector_mask_lowering<VK2, v2i1, VK32, v32i1>;
2491 defm : operation_subvector_mask_lowering<VK2, v2i1, VK64, v64i1>;
2493 defm : operation_subvector_mask_lowering<VK4, v4i1, VK8, v8i1>;
2494 defm : operation_subvector_mask_lowering<VK4, v4i1, VK16, v16i1>;
2495 defm : operation_subvector_mask_lowering<VK4, v4i1, VK32, v32i1>;
2496 defm : operation_subvector_mask_lowering<VK4, v4i1, VK64, v64i1>;
2498 defm : operation_subvector_mask_lowering<VK8, v8i1, VK16, v16i1>;
2499 defm : operation_subvector_mask_lowering<VK8, v8i1, VK32, v32i1>;
2500 defm : operation_subvector_mask_lowering<VK8, v8i1, VK64, v64i1>;
2502 defm : operation_subvector_mask_lowering<VK16, v16i1, VK32, v32i1>;
2503 defm : operation_subvector_mask_lowering<VK16, v16i1, VK64, v64i1>;
2505 defm : operation_subvector_mask_lowering<VK32, v32i1, VK64, v64i1>;
2507 def : Pat<(v2i1 (extract_subvector (v4i1 VK4:$src), (iPTR 2))),
2508 (v2i1 (COPY_TO_REGCLASS
2509 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16), (i8 2)),
2511 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 4))),
2512 (v4i1 (COPY_TO_REGCLASS
2513 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (i8 4)),
2515 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2516 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2517 def : Pat<(v16i1 (extract_subvector (v32i1 VK32:$src), (iPTR 16))),
2518 (v16i1 (COPY_TO_REGCLASS (KSHIFTRDri VK32:$src, (i8 16)), VK16))>;
2519 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2520 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2522 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2523 (v8i1 (COPY_TO_REGCLASS
2524 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2525 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2527 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2528 (v4i1 (COPY_TO_REGCLASS
2529 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2530 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2531 //===----------------------------------------------------------------------===//
2532 // AVX-512 - Aligned and unaligned load and store
2536 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2537 PatFrag ld_frag, PatFrag mload,
2538 bit IsReMaterializable = 1,
2539 SDPatternOperator SelectOprr = vselect> {
2540 let hasSideEffects = 0 in {
2541 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2542 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2544 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2545 (ins _.KRCWM:$mask, _.RC:$src),
2546 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2547 "${dst} {${mask}} {z}, $src}"),
2548 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2550 _.ImmAllZerosV)))], _.ExeDomain>,
2553 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2554 SchedRW = [WriteLoad] in
2555 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2556 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2557 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2560 let Constraints = "$src0 = $dst" in {
2561 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2562 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2563 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2564 "${dst} {${mask}}, $src1}"),
2565 [(set _.RC:$dst, (_.VT (SelectOprr _.KRCWM:$mask,
2567 (_.VT _.RC:$src0))))], _.ExeDomain>,
2569 let SchedRW = [WriteLoad] in
2570 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2571 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2572 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2573 "${dst} {${mask}}, $src1}"),
2574 [(set _.RC:$dst, (_.VT
2575 (vselect _.KRCWM:$mask,
2576 (_.VT (bitconvert (ld_frag addr:$src1))),
2577 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2579 let SchedRW = [WriteLoad] in
2580 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2581 (ins _.KRCWM:$mask, _.MemOp:$src),
2582 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2583 "${dst} {${mask}} {z}, $src}",
2584 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2585 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2586 _.ExeDomain>, EVEX, EVEX_KZ;
2588 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2589 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2591 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2592 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2594 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2595 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2596 _.KRCWM:$mask, addr:$ptr)>;
2599 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2600 AVX512VLVectorVTInfo _,
2602 bit IsReMaterializable = 1> {
2603 let Predicates = [prd] in
2604 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2605 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2607 let Predicates = [prd, HasVLX] in {
2608 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2609 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2610 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2611 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2615 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2616 AVX512VLVectorVTInfo _,
2618 bit IsReMaterializable = 1,
2619 SDPatternOperator SelectOprr = vselect> {
2620 let Predicates = [prd] in
2621 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2622 masked_load_unaligned, IsReMaterializable,
2623 SelectOprr>, EVEX_V512;
2625 let Predicates = [prd, HasVLX] in {
2626 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2627 masked_load_unaligned, IsReMaterializable,
2628 SelectOprr>, EVEX_V256;
2629 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2630 masked_load_unaligned, IsReMaterializable,
2631 SelectOprr>, EVEX_V128;
2635 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2636 PatFrag st_frag, PatFrag mstore> {
2638 let hasSideEffects = 0 in {
2639 def rr_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2640 OpcodeStr # ".s\t{$src, $dst|$dst, $src}",
2641 [], _.ExeDomain>, EVEX;
2642 def rrk_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2643 (ins _.KRCWM:$mask, _.RC:$src),
2644 OpcodeStr # ".s\t{$src, ${dst} {${mask}}|"#
2645 "${dst} {${mask}}, $src}",
2646 [], _.ExeDomain>, EVEX, EVEX_K;
2647 def rrkz_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2648 (ins _.KRCWM:$mask, _.RC:$src),
2649 OpcodeStr # ".s\t{$src, ${dst} {${mask}} {z}|" #
2650 "${dst} {${mask}} {z}, $src}",
2651 [], _.ExeDomain>, EVEX, EVEX_KZ;
2654 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2655 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2656 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2657 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2658 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2659 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2660 [], _.ExeDomain>, EVEX, EVEX_K;
2662 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2663 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2664 _.KRCWM:$mask, _.RC:$src)>;
2668 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2669 AVX512VLVectorVTInfo _, Predicate prd> {
2670 let Predicates = [prd] in
2671 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2672 masked_store_unaligned>, EVEX_V512;
2674 let Predicates = [prd, HasVLX] in {
2675 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2676 masked_store_unaligned>, EVEX_V256;
2677 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2678 masked_store_unaligned>, EVEX_V128;
2682 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2683 AVX512VLVectorVTInfo _, Predicate prd> {
2684 let Predicates = [prd] in
2685 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2686 masked_store_aligned512>, EVEX_V512;
2688 let Predicates = [prd, HasVLX] in {
2689 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2690 masked_store_aligned256>, EVEX_V256;
2691 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2692 masked_store_aligned128>, EVEX_V128;
2696 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2698 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2699 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2701 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2703 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2704 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2706 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512,
2708 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2709 PS, EVEX_CD8<32, CD8VF>;
2711 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0,
2713 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2714 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2716 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2718 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2719 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2721 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2723 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2724 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2726 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2727 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2728 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2730 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2731 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2732 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2734 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512,
2736 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2737 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2739 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512,
2741 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2742 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2744 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2745 (v8i64 VR512:$src))),
2746 (VMOVDQA64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2749 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2750 (v16i32 VR512:$src))),
2751 (VMOVDQA32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2753 // These patterns exist to prevent the above patterns from introducing a second
2754 // mask inversion when one already exists.
2755 def : Pat<(v8i64 (vselect (xor VK8:$mask, (v8i1 immAllOnesV)),
2756 (bc_v8i64 (v16i32 immAllZerosV)),
2757 (v8i64 VR512:$src))),
2758 (VMOVDQA64Zrrkz VK8:$mask, VR512:$src)>;
2759 def : Pat<(v16i32 (vselect (xor VK16:$mask, (v16i1 immAllOnesV)),
2760 (v16i32 immAllZerosV),
2761 (v16i32 VR512:$src))),
2762 (VMOVDQA32Zrrkz VK16WM:$mask, VR512:$src)>;
2764 let Predicates = [HasVLX] in {
2765 // Special patterns for storing subvector extracts of lower 128-bits of 256.
2766 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
2767 def : Pat<(alignedstore (v2f64 (extract_subvector
2768 (v4f64 VR256X:$src), (iPTR 0))), addr:$dst),
2769 (VMOVAPDZ128mr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2770 def : Pat<(alignedstore (v4f32 (extract_subvector
2771 (v8f32 VR256X:$src), (iPTR 0))), addr:$dst),
2772 (VMOVAPSZ128mr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2773 def : Pat<(alignedstore (v2i64 (extract_subvector
2774 (v4i64 VR256X:$src), (iPTR 0))), addr:$dst),
2775 (VMOVDQA64Z128mr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2776 def : Pat<(alignedstore (v4i32 (extract_subvector
2777 (v8i32 VR256X:$src), (iPTR 0))), addr:$dst),
2778 (VMOVDQA32Z128mr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2779 def : Pat<(alignedstore (v8i16 (extract_subvector
2780 (v16i16 VR256X:$src), (iPTR 0))), addr:$dst),
2781 (VMOVDQA32Z128mr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2782 def : Pat<(alignedstore (v16i8 (extract_subvector
2783 (v32i8 VR256X:$src), (iPTR 0))), addr:$dst),
2784 (VMOVDQA32Z128mr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2786 def : Pat<(store (v2f64 (extract_subvector
2787 (v4f64 VR256X:$src), (iPTR 0))), addr:$dst),
2788 (VMOVUPDZ128mr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2789 def : Pat<(store (v4f32 (extract_subvector
2790 (v8f32 VR256X:$src), (iPTR 0))), addr:$dst),
2791 (VMOVUPSZ128mr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2792 def : Pat<(store (v2i64 (extract_subvector
2793 (v4i64 VR256X:$src), (iPTR 0))), addr:$dst),
2794 (VMOVDQU64Z128mr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2795 def : Pat<(store (v4i32 (extract_subvector
2796 (v8i32 VR256X:$src), (iPTR 0))), addr:$dst),
2797 (VMOVDQU32Z128mr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2798 def : Pat<(store (v8i16 (extract_subvector
2799 (v16i16 VR256X:$src), (iPTR 0))), addr:$dst),
2800 (VMOVDQU32Z128mr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2801 def : Pat<(store (v16i8 (extract_subvector
2802 (v32i8 VR256X:$src), (iPTR 0))), addr:$dst),
2803 (VMOVDQU32Z128mr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256X:$src,sub_xmm)))>;
2805 // Special patterns for storing subvector extracts of lower 128-bits of 512.
2806 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
2807 def : Pat<(alignedstore (v2f64 (extract_subvector
2808 (v8f64 VR512:$src), (iPTR 0))), addr:$dst),
2809 (VMOVAPDZ128mr addr:$dst, (v2f64 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2810 def : Pat<(alignedstore (v4f32 (extract_subvector
2811 (v16f32 VR512:$src), (iPTR 0))), addr:$dst),
2812 (VMOVAPSZ128mr addr:$dst, (v4f32 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2813 def : Pat<(alignedstore (v2i64 (extract_subvector
2814 (v8i64 VR512:$src), (iPTR 0))), addr:$dst),
2815 (VMOVDQA64Z128mr addr:$dst, (v2i64 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2816 def : Pat<(alignedstore (v4i32 (extract_subvector
2817 (v16i32 VR512:$src), (iPTR 0))), addr:$dst),
2818 (VMOVDQA32Z128mr addr:$dst, (v4i32 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2819 def : Pat<(alignedstore (v8i16 (extract_subvector
2820 (v32i16 VR512:$src), (iPTR 0))), addr:$dst),
2821 (VMOVDQA32Z128mr addr:$dst, (v8i16 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2822 def : Pat<(alignedstore (v16i8 (extract_subvector
2823 (v64i8 VR512:$src), (iPTR 0))), addr:$dst),
2824 (VMOVDQA32Z128mr addr:$dst, (v16i8 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2826 def : Pat<(store (v2f64 (extract_subvector
2827 (v8f64 VR512:$src), (iPTR 0))), addr:$dst),
2828 (VMOVUPDZ128mr addr:$dst, (v2f64 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2829 def : Pat<(store (v4f32 (extract_subvector
2830 (v16f32 VR512:$src), (iPTR 0))), addr:$dst),
2831 (VMOVUPSZ128mr addr:$dst, (v4f32 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2832 def : Pat<(store (v2i64 (extract_subvector
2833 (v8i64 VR512:$src), (iPTR 0))), addr:$dst),
2834 (VMOVDQU64Z128mr addr:$dst, (v2i64 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2835 def : Pat<(store (v4i32 (extract_subvector
2836 (v16i32 VR512:$src), (iPTR 0))), addr:$dst),
2837 (VMOVDQU32Z128mr addr:$dst, (v4i32 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2838 def : Pat<(store (v8i16 (extract_subvector
2839 (v32i16 VR512:$src), (iPTR 0))), addr:$dst),
2840 (VMOVDQU32Z128mr addr:$dst, (v8i16 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2841 def : Pat<(store (v16i8 (extract_subvector
2842 (v64i8 VR512:$src), (iPTR 0))), addr:$dst),
2843 (VMOVDQU32Z128mr addr:$dst, (v16i8 (EXTRACT_SUBREG VR512:$src,sub_xmm)))>;
2845 // Special patterns for storing subvector extracts of lower 256-bits of 512.
2846 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
2847 def : Pat<(alignedstore (v4f64 (extract_subvector
2848 (v8f64 VR512:$src), (iPTR 0))), addr:$dst),
2849 (VMOVAPDZ256mr addr:$dst, (v4f64 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
2850 def : Pat<(alignedstore (v8f32 (extract_subvector
2851 (v16f32 VR512:$src), (iPTR 0))), addr:$dst),
2852 (VMOVAPSZ256mr addr:$dst, (v8f32 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
2853 def : Pat<(alignedstore (v4i64 (extract_subvector
2854 (v8i64 VR512:$src), (iPTR 0))), addr:$dst),
2855 (VMOVDQA64Z256mr addr:$dst, (v4i64 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
2856 def : Pat<(alignedstore (v8i32 (extract_subvector
2857 (v16i32 VR512:$src), (iPTR 0))), addr:$dst),
2858 (VMOVDQA32Z256mr addr:$dst, (v8i32 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
2859 def : Pat<(alignedstore (v16i16 (extract_subvector
2860 (v32i16 VR512:$src), (iPTR 0))), addr:$dst),
2861 (VMOVDQA32Z256mr addr:$dst, (v16i16 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
2862 def : Pat<(alignedstore (v32i8 (extract_subvector
2863 (v64i8 VR512:$src), (iPTR 0))), addr:$dst),
2864 (VMOVDQA32Z256mr addr:$dst, (v32i8 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
2866 def : Pat<(store (v4f64 (extract_subvector
2867 (v8f64 VR512:$src), (iPTR 0))), addr:$dst),
2868 (VMOVUPDZ256mr addr:$dst, (v4f64 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
2869 def : Pat<(store (v8f32 (extract_subvector
2870 (v16f32 VR512:$src), (iPTR 0))), addr:$dst),
2871 (VMOVUPSZ256mr addr:$dst, (v8f32 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
2872 def : Pat<(store (v4i64 (extract_subvector
2873 (v8i64 VR512:$src), (iPTR 0))), addr:$dst),
2874 (VMOVDQU64Z256mr addr:$dst, (v4i64 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
2875 def : Pat<(store (v8i32 (extract_subvector
2876 (v16i32 VR512:$src), (iPTR 0))), addr:$dst),
2877 (VMOVDQU32Z256mr addr:$dst, (v8i32 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
2878 def : Pat<(store (v16i16 (extract_subvector
2879 (v32i16 VR512:$src), (iPTR 0))), addr:$dst),
2880 (VMOVDQU32Z256mr addr:$dst, (v16i16 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
2881 def : Pat<(store (v32i8 (extract_subvector
2882 (v64i8 VR512:$src), (iPTR 0))), addr:$dst),
2883 (VMOVDQU32Z256mr addr:$dst, (v32i8 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
2887 // Move Int Doubleword to Packed Double Int
2889 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2890 "vmovd\t{$src, $dst|$dst, $src}",
2892 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2894 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2895 "vmovd\t{$src, $dst|$dst, $src}",
2897 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2898 IIC_SSE_MOVDQ>, EVEX, EVEX_CD8<32, CD8VT1>;
2899 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2900 "vmovq\t{$src, $dst|$dst, $src}",
2902 (v2i64 (scalar_to_vector GR64:$src)))],
2903 IIC_SSE_MOVDQ>, EVEX, VEX_W;
2904 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
2905 def VMOV64toPQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2907 "vmovq\t{$src, $dst|$dst, $src}", []>,
2908 EVEX, VEX_W, EVEX_CD8<64, CD8VT1>;
2909 let isCodeGenOnly = 1 in {
2910 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64X:$dst), (ins GR64:$src),
2911 "vmovq\t{$src, $dst|$dst, $src}",
2912 [(set FR64X:$dst, (bitconvert GR64:$src))],
2913 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2914 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64X:$src),
2915 "vmovq\t{$src, $dst|$dst, $src}",
2916 [(set GR64:$dst, (bitconvert FR64X:$src))],
2917 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2918 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64X:$src),
2919 "vmovq\t{$src, $dst|$dst, $src}",
2920 [(store (i64 (bitconvert FR64X:$src)), addr:$dst)],
2921 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2922 EVEX_CD8<64, CD8VT1>;
2925 // Move Int Doubleword to Single Scalar
2927 let isCodeGenOnly = 1 in {
2928 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2929 "vmovd\t{$src, $dst|$dst, $src}",
2930 [(set FR32X:$dst, (bitconvert GR32:$src))],
2931 IIC_SSE_MOVDQ>, EVEX;
2933 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2934 "vmovd\t{$src, $dst|$dst, $src}",
2935 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2936 IIC_SSE_MOVDQ>, EVEX, EVEX_CD8<32, CD8VT1>;
2939 // Move doubleword from xmm register to r/m32
2941 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2942 "vmovd\t{$src, $dst|$dst, $src}",
2943 [(set GR32:$dst, (extractelt (v4i32 VR128X:$src),
2944 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2946 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2947 (ins i32mem:$dst, VR128X:$src),
2948 "vmovd\t{$src, $dst|$dst, $src}",
2949 [(store (i32 (extractelt (v4i32 VR128X:$src),
2950 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2951 EVEX, EVEX_CD8<32, CD8VT1>;
2953 // Move quadword from xmm1 register to r/m64
2955 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2956 "vmovq\t{$src, $dst|$dst, $src}",
2957 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2959 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_W,
2960 Requires<[HasAVX512, In64BitMode]>;
2962 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
2963 def VMOVPQIto64Zmr : I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128X:$src),
2964 "vmovq\t{$src, $dst|$dst, $src}",
2965 [], IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_W,
2966 Requires<[HasAVX512, In64BitMode]>;
2968 def VMOVPQI2QIZmr : I<0xD6, MRMDestMem, (outs),
2969 (ins i64mem:$dst, VR128X:$src),
2970 "vmovq\t{$src, $dst|$dst, $src}",
2971 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2972 addr:$dst)], IIC_SSE_MOVDQ>,
2973 EVEX, PD, VEX_W, EVEX_CD8<64, CD8VT1>,
2974 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2976 let hasSideEffects = 0 in
2977 def VMOVPQI2QIZrr : AVX512BI<0xD6, MRMDestReg, (outs VR128X:$dst),
2979 "vmovq.s\t{$src, $dst|$dst, $src}",[]>,
2982 // Move Scalar Single to Double Int
2984 let isCodeGenOnly = 1 in {
2985 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2987 "vmovd\t{$src, $dst|$dst, $src}",
2988 [(set GR32:$dst, (bitconvert FR32X:$src))],
2989 IIC_SSE_MOVD_ToGP>, EVEX;
2990 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2991 (ins i32mem:$dst, FR32X:$src),
2992 "vmovd\t{$src, $dst|$dst, $src}",
2993 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2994 IIC_SSE_MOVDQ>, EVEX, EVEX_CD8<32, CD8VT1>;
2997 // Move Quadword Int to Packed Quadword Int
2999 def VMOVQI2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
3001 "vmovq\t{$src, $dst|$dst, $src}",
3003 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
3004 EVEX, VEX_W, EVEX_CD8<8, CD8VT8>;
3006 //===----------------------------------------------------------------------===//
3007 // AVX-512 MOVSS, MOVSD
3008 //===----------------------------------------------------------------------===//
3010 multiclass avx512_move_scalar <string asm, SDNode OpNode,
3011 X86VectorVTInfo _> {
3012 defm rr_Int : AVX512_maskable_scalar<0x10, MRMSrcReg, _, (outs _.RC:$dst),
3013 (ins _.RC:$src1, _.RC:$src2),
3014 asm, "$src2, $src1","$src1, $src2",
3015 (_.VT (OpNode (_.VT _.RC:$src1),
3016 (_.VT _.RC:$src2))),
3017 IIC_SSE_MOV_S_RR>, EVEX_4V;
3018 let Constraints = "$src1 = $dst" in
3019 defm rm_Int : AVX512_maskable_3src_scalar<0x10, MRMSrcMem, _,
3021 (ins _.ScalarMemOp:$src),
3023 (_.VT (OpNode (_.VT _.RC:$src1),
3024 (_.VT (scalar_to_vector
3025 (_.ScalarLdFrag addr:$src)))))>, EVEX;
3026 let isCodeGenOnly = 1 in {
3027 def rr : AVX512PI<0x10, MRMSrcReg, (outs _.RC:$dst),
3028 (ins _.RC:$src1, _.FRC:$src2),
3029 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3030 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1,
3031 (scalar_to_vector _.FRC:$src2))))],
3032 _.ExeDomain,IIC_SSE_MOV_S_RR>, EVEX_4V;
3033 def rm : AVX512PI<0x10, MRMSrcMem, (outs _.FRC:$dst), (ins _.ScalarMemOp:$src),
3034 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
3035 [(set _.FRC:$dst, (_.ScalarLdFrag addr:$src))],
3036 _.ExeDomain, IIC_SSE_MOV_S_RM>, EVEX;
3038 def mr: AVX512PI<0x11, MRMDestMem, (outs), (ins _.ScalarMemOp:$dst, _.FRC:$src),
3039 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
3040 [(store _.FRC:$src, addr:$dst)], _.ExeDomain, IIC_SSE_MOV_S_MR>,
3043 def mrk: AVX512PI<0x11, MRMDestMem, (outs),
3044 (ins _.ScalarMemOp:$dst, VK1WM:$mask, _.FRC:$src),
3045 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
3046 [], _.ExeDomain, IIC_SSE_MOV_S_MR>, EVEX, EVEX_K;
3049 defm VMOVSSZ : avx512_move_scalar<"vmovss", X86Movss, f32x_info>,
3050 VEX_LIG, XS, EVEX_CD8<32, CD8VT1>;
3052 defm VMOVSDZ : avx512_move_scalar<"vmovsd", X86Movsd, f64x_info>,
3053 VEX_LIG, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3055 def : Pat<(f32 (X86selects VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
3056 (COPY_TO_REGCLASS (VMOVSSZrr_Intk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
3057 VK1WM:$mask, (v4f32 (IMPLICIT_DEF)),(COPY_TO_REGCLASS FR32X:$src1, VR128X)), FR32X)>;
3059 def : Pat<(f64 (X86selects VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
3060 (COPY_TO_REGCLASS (VMOVSDZrr_Intk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
3061 VK1WM:$mask, (v2f64 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR64X:$src1, VR128X)), FR64X)>;
3063 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
3064 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
3065 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3067 let hasSideEffects = 0 in
3068 defm VMOVSSZrr_REV : AVX512_maskable_in_asm<0x11, MRMDestReg, f32x_info,
3069 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2),
3070 "vmovss.s", "$src2, $src1", "$src1, $src2", []>,
3071 XS, EVEX_4V, VEX_LIG;
3073 let hasSideEffects = 0 in
3074 defm VMOVSSDrr_REV : AVX512_maskable_in_asm<0x11, MRMDestReg, f64x_info,
3075 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2),
3076 "vmovsd.s", "$src2, $src1", "$src1, $src2", []>,
3077 XD, EVEX_4V, VEX_LIG, VEX_W;
3079 let Predicates = [HasAVX512] in {
3080 let AddedComplexity = 15 in {
3081 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
3082 // MOVS{S,D} to the lower bits.
3083 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
3084 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
3085 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
3086 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3087 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
3088 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3089 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
3090 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
3092 // Move low f32 and clear high bits.
3093 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
3094 (SUBREG_TO_REG (i32 0),
3095 (VMOVSSZrr (v4f32 (V_SET0)),
3096 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
3097 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
3098 (SUBREG_TO_REG (i32 0),
3099 (VMOVSSZrr (v4i32 (V_SET0)),
3100 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
3103 let AddedComplexity = 20 in {
3104 // MOVSSrm zeros the high parts of the register; represent this
3105 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
3106 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
3107 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3108 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
3109 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3110 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
3111 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3113 // MOVSDrm zeros the high parts of the register; represent this
3114 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
3115 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
3116 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3117 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
3118 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3119 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
3120 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3121 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
3122 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3123 def : Pat<(v2f64 (X86vzload addr:$src)),
3124 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3126 // Represent the same patterns above but in the form they appear for
3128 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3129 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
3130 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
3131 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
3132 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
3133 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
3134 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
3135 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
3136 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
3137 def : Pat<(v4f64 (X86vzload addr:$src)),
3138 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
3140 // Represent the same patterns above but in the form they appear for
3142 def : Pat<(v16i32 (X86vzmovl (insert_subvector undef,
3143 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
3144 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
3145 def : Pat<(v16f32 (X86vzmovl (insert_subvector undef,
3146 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
3147 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
3148 def : Pat<(v8f64 (X86vzmovl (insert_subvector undef,
3149 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
3150 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
3151 def : Pat<(v8f64 (X86vzload addr:$src)),
3152 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
3154 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
3155 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
3156 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
3157 FR32X:$src)), sub_xmm)>;
3158 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
3159 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
3160 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
3161 FR64X:$src)), sub_xmm)>;
3162 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3163 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
3164 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
3166 // Move low f64 and clear high bits.
3167 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
3168 (SUBREG_TO_REG (i32 0),
3169 (VMOVSDZrr (v2f64 (V_SET0)),
3170 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
3172 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
3173 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
3174 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
3176 // Extract and store.
3177 def : Pat<(store (f32 (extractelt (v4f32 VR128X:$src), (iPTR 0))),
3179 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
3181 // Shuffle with VMOVSS
3182 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
3183 (VMOVSSZrr (v4i32 VR128X:$src1),
3184 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
3185 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
3186 (VMOVSSZrr (v4f32 VR128X:$src1),
3187 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
3190 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
3191 (SUBREG_TO_REG (i32 0),
3192 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
3193 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
3195 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
3196 (SUBREG_TO_REG (i32 0),
3197 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
3198 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
3201 // Shuffle with VMOVSD
3202 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3203 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3204 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3205 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3206 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3207 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3208 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3209 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3212 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3213 (SUBREG_TO_REG (i32 0),
3214 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
3215 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
3217 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3218 (SUBREG_TO_REG (i32 0),
3219 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
3220 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
3223 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3224 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3225 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3226 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3227 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3228 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3229 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3230 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3233 let AddedComplexity = 15 in
3234 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
3236 "vmovq\t{$src, $dst|$dst, $src}",
3237 [(set VR128X:$dst, (v2i64 (X86vzmovl
3238 (v2i64 VR128X:$src))))],
3239 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
3241 let AddedComplexity = 20 , isCodeGenOnly = 1 in
3242 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
3244 "vmovq\t{$src, $dst|$dst, $src}",
3245 [(set VR128X:$dst, (v2i64 (X86vzmovl
3246 (loadv2i64 addr:$src))))],
3247 IIC_SSE_MOVDQ>, EVEX, VEX_W,
3248 EVEX_CD8<8, CD8VT8>;
3250 let Predicates = [HasAVX512] in {
3251 let AddedComplexity = 15 in {
3252 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
3253 (VMOVDI2PDIZrr GR32:$src)>;
3255 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
3256 (VMOV64toPQIZrr GR64:$src)>;
3258 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3259 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
3260 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
3262 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3263 let AddedComplexity = 20 in {
3264 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
3265 (VMOVDI2PDIZrm addr:$src)>;
3267 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3268 (VMOVDI2PDIZrm addr:$src)>;
3269 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3270 (VMOVDI2PDIZrm addr:$src)>;
3271 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3272 (VMOVZPQILo2PQIZrm addr:$src)>;
3273 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
3274 (VMOVZPQILo2PQIZrr VR128X:$src)>;
3275 def : Pat<(v2i64 (X86vzload addr:$src)),
3276 (VMOVZPQILo2PQIZrm addr:$src)>;
3277 def : Pat<(v4i64 (X86vzload addr:$src)),
3278 (SUBREG_TO_REG (i64 0), (VMOVZPQILo2PQIZrm addr:$src), sub_xmm)>;
3281 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3282 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3283 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
3284 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
3286 // Use regular 128-bit instructions to match 512-bit scalar_to_vec+zext.
3287 def : Pat<(v8i64 (X86vzload addr:$src)),
3288 (SUBREG_TO_REG (i64 0), (VMOVZPQILo2PQIZrm addr:$src), sub_xmm)>;
3291 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
3292 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3294 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
3295 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3297 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
3298 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3300 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
3301 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3303 //===----------------------------------------------------------------------===//
3304 // AVX-512 - Non-temporals
3305 //===----------------------------------------------------------------------===//
3306 let SchedRW = [WriteLoad] in {
3307 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
3308 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
3309 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
3310 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
3311 EVEX_CD8<64, CD8VF>;
3313 let Predicates = [HasVLX] in {
3314 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
3316 "vmovntdqa\t{$src, $dst|$dst, $src}",
3317 [(set VR256X:$dst, (int_x86_avx2_movntdqa addr:$src))],
3318 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
3319 EVEX_CD8<64, CD8VF>;
3321 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
3323 "vmovntdqa\t{$src, $dst|$dst, $src}",
3324 [(set VR128X:$dst, (int_x86_sse41_movntdqa addr:$src))],
3325 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
3326 EVEX_CD8<64, CD8VF>;
3330 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3331 PatFrag st_frag = alignednontemporalstore,
3332 InstrItinClass itin = IIC_SSE_MOVNT> {
3333 let SchedRW = [WriteStore], AddedComplexity = 400 in
3334 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
3335 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3336 [(st_frag (_.VT _.RC:$src), addr:$dst)],
3337 _.ExeDomain, itin>, EVEX, EVEX_CD8<_.EltSize, CD8VF>;
3340 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr,
3341 AVX512VLVectorVTInfo VTInfo> {
3342 let Predicates = [HasAVX512] in
3343 defm Z : avx512_movnt<opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
3345 let Predicates = [HasAVX512, HasVLX] in {
3346 defm Z256 : avx512_movnt<opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
3347 defm Z128 : avx512_movnt<opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
3351 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", avx512vl_i64_info>, PD;
3352 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", avx512vl_f64_info>, PD, VEX_W;
3353 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", avx512vl_f32_info>, PS;
3355 let Predicates = [HasAVX512], AddedComplexity = 400 in {
3356 def : Pat<(alignednontemporalstore (v16i32 VR512:$src), addr:$dst),
3357 (VMOVNTDQZmr addr:$dst, VR512:$src)>;
3358 def : Pat<(alignednontemporalstore (v32i16 VR512:$src), addr:$dst),
3359 (VMOVNTDQZmr addr:$dst, VR512:$src)>;
3360 def : Pat<(alignednontemporalstore (v64i8 VR512:$src), addr:$dst),
3361 (VMOVNTDQZmr addr:$dst, VR512:$src)>;
3363 def : Pat<(v8f64 (alignednontemporalload addr:$src)),
3364 (VMOVNTDQAZrm addr:$src)>;
3365 def : Pat<(v16f32 (alignednontemporalload addr:$src)),
3366 (VMOVNTDQAZrm addr:$src)>;
3367 def : Pat<(v8i64 (alignednontemporalload addr:$src)),
3368 (VMOVNTDQAZrm addr:$src)>;
3369 def : Pat<(v16i32 (alignednontemporalload addr:$src)),
3370 (VMOVNTDQAZrm addr:$src)>;
3371 def : Pat<(v32i16 (alignednontemporalload addr:$src)),
3372 (VMOVNTDQAZrm addr:$src)>;
3373 def : Pat<(v64i8 (alignednontemporalload addr:$src)),
3374 (VMOVNTDQAZrm addr:$src)>;
3377 let Predicates = [HasVLX], AddedComplexity = 400 in {
3378 def : Pat<(alignednontemporalstore (v8i32 VR256X:$src), addr:$dst),
3379 (VMOVNTDQZ256mr addr:$dst, VR256X:$src)>;
3380 def : Pat<(alignednontemporalstore (v16i16 VR256X:$src), addr:$dst),
3381 (VMOVNTDQZ256mr addr:$dst, VR256X:$src)>;
3382 def : Pat<(alignednontemporalstore (v32i8 VR256X:$src), addr:$dst),
3383 (VMOVNTDQZ256mr addr:$dst, VR256X:$src)>;
3385 def : Pat<(v4f64 (alignednontemporalload addr:$src)),
3386 (VMOVNTDQAZ256rm addr:$src)>;
3387 def : Pat<(v8f32 (alignednontemporalload addr:$src)),
3388 (VMOVNTDQAZ256rm addr:$src)>;
3389 def : Pat<(v4i64 (alignednontemporalload addr:$src)),
3390 (VMOVNTDQAZ256rm addr:$src)>;
3391 def : Pat<(v8i32 (alignednontemporalload addr:$src)),
3392 (VMOVNTDQAZ256rm addr:$src)>;
3393 def : Pat<(v16i16 (alignednontemporalload addr:$src)),
3394 (VMOVNTDQAZ256rm addr:$src)>;
3395 def : Pat<(v32i8 (alignednontemporalload addr:$src)),
3396 (VMOVNTDQAZ256rm addr:$src)>;
3398 def : Pat<(alignednontemporalstore (v4i32 VR128X:$src), addr:$dst),
3399 (VMOVNTDQZ128mr addr:$dst, VR128X:$src)>;
3400 def : Pat<(alignednontemporalstore (v8i16 VR128X:$src), addr:$dst),
3401 (VMOVNTDQZ128mr addr:$dst, VR128X:$src)>;
3402 def : Pat<(alignednontemporalstore (v16i8 VR128X:$src), addr:$dst),
3403 (VMOVNTDQZ128mr addr:$dst, VR128X:$src)>;
3405 def : Pat<(v2f64 (alignednontemporalload addr:$src)),
3406 (VMOVNTDQAZ128rm addr:$src)>;
3407 def : Pat<(v4f32 (alignednontemporalload addr:$src)),
3408 (VMOVNTDQAZ128rm addr:$src)>;
3409 def : Pat<(v2i64 (alignednontemporalload addr:$src)),
3410 (VMOVNTDQAZ128rm addr:$src)>;
3411 def : Pat<(v4i32 (alignednontemporalload addr:$src)),
3412 (VMOVNTDQAZ128rm addr:$src)>;
3413 def : Pat<(v8i16 (alignednontemporalload addr:$src)),
3414 (VMOVNTDQAZ128rm addr:$src)>;
3415 def : Pat<(v16i8 (alignednontemporalload addr:$src)),
3416 (VMOVNTDQAZ128rm addr:$src)>;
3419 //===----------------------------------------------------------------------===//
3420 // AVX-512 - Integer arithmetic
3422 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3423 X86VectorVTInfo _, OpndItins itins,
3424 bit IsCommutable = 0> {
3425 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3426 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3427 "$src2, $src1", "$src1, $src2",
3428 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3429 itins.rr, IsCommutable>,
3430 AVX512BIBase, EVEX_4V;
3432 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3433 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3434 "$src2, $src1", "$src1, $src2",
3435 (_.VT (OpNode _.RC:$src1,
3436 (bitconvert (_.LdFrag addr:$src2)))),
3438 AVX512BIBase, EVEX_4V;
3441 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3442 X86VectorVTInfo _, OpndItins itins,
3443 bit IsCommutable = 0> :
3444 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
3445 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3446 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3447 "${src2}"##_.BroadcastStr##", $src1",
3448 "$src1, ${src2}"##_.BroadcastStr,
3449 (_.VT (OpNode _.RC:$src1,
3451 (_.ScalarLdFrag addr:$src2)))),
3453 AVX512BIBase, EVEX_4V, EVEX_B;
3456 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3457 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3458 Predicate prd, bit IsCommutable = 0> {
3459 let Predicates = [prd] in
3460 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3461 IsCommutable>, EVEX_V512;
3463 let Predicates = [prd, HasVLX] in {
3464 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3465 IsCommutable>, EVEX_V256;
3466 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3467 IsCommutable>, EVEX_V128;
3471 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3472 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3473 Predicate prd, bit IsCommutable = 0> {
3474 let Predicates = [prd] in
3475 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3476 IsCommutable>, EVEX_V512;
3478 let Predicates = [prd, HasVLX] in {
3479 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3480 IsCommutable>, EVEX_V256;
3481 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3482 IsCommutable>, EVEX_V128;
3486 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3487 OpndItins itins, Predicate prd,
3488 bit IsCommutable = 0> {
3489 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3490 itins, prd, IsCommutable>,
3491 VEX_W, EVEX_CD8<64, CD8VF>;
3494 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3495 OpndItins itins, Predicate prd,
3496 bit IsCommutable = 0> {
3497 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3498 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3501 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3502 OpndItins itins, Predicate prd,
3503 bit IsCommutable = 0> {
3504 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3505 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3508 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3509 OpndItins itins, Predicate prd,
3510 bit IsCommutable = 0> {
3511 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3512 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3515 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3516 SDNode OpNode, OpndItins itins, Predicate prd,
3517 bit IsCommutable = 0> {
3518 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, itins, prd,
3521 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, itins, prd,
3525 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3526 SDNode OpNode, OpndItins itins, Predicate prd,
3527 bit IsCommutable = 0> {
3528 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr#"w", OpNode, itins, prd,
3531 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr#"b", OpNode, itins, prd,
3535 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3536 bits<8> opc_d, bits<8> opc_q,
3537 string OpcodeStr, SDNode OpNode,
3538 OpndItins itins, bit IsCommutable = 0> {
3539 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3540 itins, HasAVX512, IsCommutable>,
3541 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3542 itins, HasBWI, IsCommutable>;
3545 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3546 SDNode OpNode,X86VectorVTInfo _Src,
3547 X86VectorVTInfo _Dst, X86VectorVTInfo _Brdct,
3548 bit IsCommutable = 0> {
3549 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3550 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3551 "$src2, $src1","$src1, $src2",
3553 (_Src.VT _Src.RC:$src1),
3554 (_Src.VT _Src.RC:$src2))),
3555 itins.rr, IsCommutable>,
3556 AVX512BIBase, EVEX_4V;
3557 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3558 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3559 "$src2, $src1", "$src1, $src2",
3560 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3561 (bitconvert (_Src.LdFrag addr:$src2)))),
3563 AVX512BIBase, EVEX_4V;
3565 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3566 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3568 "${src2}"##_Brdct.BroadcastStr##", $src1",
3569 "$src1, ${src2}"##_Dst.BroadcastStr,
3570 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3571 (_Brdct.VT (X86VBroadcast
3572 (_Brdct.ScalarLdFrag addr:$src2)))))),
3574 AVX512BIBase, EVEX_4V, EVEX_B;
3577 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3578 SSE_INTALU_ITINS_P, 1>;
3579 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3580 SSE_INTALU_ITINS_P, 0>;
3581 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3582 SSE_INTALU_ITINS_P, HasBWI, 1>;
3583 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3584 SSE_INTALU_ITINS_P, HasBWI, 0>;
3585 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3586 SSE_INTALU_ITINS_P, HasBWI, 1>;
3587 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3588 SSE_INTALU_ITINS_P, HasBWI, 0>;
3589 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul,
3590 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3591 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul,
3592 SSE_INTALU_ITINS_P, HasBWI, 1>;
3593 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul,
3594 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3595 defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SSE_INTALU_ITINS_P,
3597 defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SSE_INTMUL_ITINS_P,
3599 defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, SSE_INTMUL_ITINS_P,
3601 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
3602 SSE_INTALU_ITINS_P, HasBWI, 1>;
3604 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3605 AVX512VLVectorVTInfo _SrcVTInfo, AVX512VLVectorVTInfo _DstVTInfo,
3606 SDNode OpNode, Predicate prd, bit IsCommutable = 0> {
3607 let Predicates = [prd] in
3608 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3609 _SrcVTInfo.info512, _DstVTInfo.info512,
3610 v8i64_info, IsCommutable>,
3611 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3612 let Predicates = [HasVLX, prd] in {
3613 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3614 _SrcVTInfo.info256, _DstVTInfo.info256,
3615 v4i64x_info, IsCommutable>,
3616 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3617 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3618 _SrcVTInfo.info128, _DstVTInfo.info128,
3619 v2i64x_info, IsCommutable>,
3620 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3624 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3625 avx512vl_i32_info, avx512vl_i64_info,
3626 X86pmuldq, HasAVX512, 1>,T8PD;
3627 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3628 avx512vl_i32_info, avx512vl_i64_info,
3629 X86pmuludq, HasAVX512, 1>;
3630 defm VPMULTISHIFTQB : avx512_binop_all<0x83, "vpmultishiftqb", SSE_INTALU_ITINS_P,
3631 avx512vl_i8_info, avx512vl_i8_info,
3632 X86multishift, HasVBMI, 0>, T8PD;
3634 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3635 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3636 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3637 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3639 "${src2}"##_Src.BroadcastStr##", $src1",
3640 "$src1, ${src2}"##_Src.BroadcastStr,
3641 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3642 (_Src.VT (X86VBroadcast
3643 (_Src.ScalarLdFrag addr:$src2))))))>,
3644 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3647 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3648 SDNode OpNode,X86VectorVTInfo _Src,
3649 X86VectorVTInfo _Dst> {
3650 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3651 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3652 "$src2, $src1","$src1, $src2",
3654 (_Src.VT _Src.RC:$src1),
3655 (_Src.VT _Src.RC:$src2)))>,
3656 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3657 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3658 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3659 "$src2, $src1", "$src1, $src2",
3660 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3661 (bitconvert (_Src.LdFrag addr:$src2))))>,
3662 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3665 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3667 let Predicates = [HasBWI] in
3668 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3670 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3671 v32i16_info>, EVEX_V512;
3672 let Predicates = [HasBWI, HasVLX] in {
3673 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3675 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3676 v16i16x_info>, EVEX_V256;
3677 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3679 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3680 v8i16x_info>, EVEX_V128;
3683 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3685 let Predicates = [HasBWI] in
3686 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3687 v64i8_info>, EVEX_V512;
3688 let Predicates = [HasBWI, HasVLX] in {
3689 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3690 v32i8x_info>, EVEX_V256;
3691 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3692 v16i8x_info>, EVEX_V128;
3696 multiclass avx512_vpmadd<bits<8> opc, string OpcodeStr,
3697 SDNode OpNode, AVX512VLVectorVTInfo _Src,
3698 AVX512VLVectorVTInfo _Dst> {
3699 let Predicates = [HasBWI] in
3700 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info512,
3701 _Dst.info512>, EVEX_V512;
3702 let Predicates = [HasBWI, HasVLX] in {
3703 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info256,
3704 _Dst.info256>, EVEX_V256;
3705 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info128,
3706 _Dst.info128>, EVEX_V128;
3710 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, AVX512BIBase;
3711 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, AVX5128IBase;
3712 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase;
3713 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase;
3715 defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw,
3716 avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD;
3717 defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd,
3718 avx512vl_i16_info, avx512vl_i32_info>, AVX512BIBase;
3720 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax,
3721 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3722 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax,
3723 SSE_INTALU_ITINS_P, HasBWI, 1>;
3724 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", smax,
3725 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3727 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax,
3728 SSE_INTALU_ITINS_P, HasBWI, 1>;
3729 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax,
3730 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3731 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", umax,
3732 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3734 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin,
3735 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3736 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin,
3737 SSE_INTALU_ITINS_P, HasBWI, 1>;
3738 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", smin,
3739 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3741 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin,
3742 SSE_INTALU_ITINS_P, HasBWI, 1>;
3743 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
3744 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3745 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
3746 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3747 //===----------------------------------------------------------------------===//
3748 // AVX-512 Logical Instructions
3749 //===----------------------------------------------------------------------===//
3751 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3752 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3753 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3754 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3755 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3756 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3757 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3758 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3760 //===----------------------------------------------------------------------===//
3761 // AVX-512 FP arithmetic
3762 //===----------------------------------------------------------------------===//
3763 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3764 SDNode OpNode, SDNode VecNode, OpndItins itins,
3767 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3768 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3769 "$src2, $src1", "$src1, $src2",
3770 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3771 (i32 FROUND_CURRENT)),
3772 itins.rr, IsCommutable>;
3774 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3775 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3776 "$src2, $src1", "$src1, $src2",
3777 (VecNode (_.VT _.RC:$src1),
3778 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3779 (i32 FROUND_CURRENT)),
3780 itins.rm, IsCommutable>;
3781 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3782 Predicates = [HasAVX512] in {
3783 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3784 (ins _.FRC:$src1, _.FRC:$src2),
3785 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3786 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3788 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3789 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3790 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3791 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3792 (_.ScalarLdFrag addr:$src2)))], itins.rm>;
3796 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3797 SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
3799 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3800 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3801 "$rc, $src2, $src1", "$src1, $src2, $rc",
3802 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3803 (i32 imm:$rc)), itins.rr, IsCommutable>,
3806 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3807 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3809 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3810 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3811 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3812 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3813 (i32 FROUND_NO_EXC))>, EVEX_B;
3816 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3818 SizeItins itins, bit IsCommutable> {
3819 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3820 itins.s, IsCommutable>,
3821 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3822 itins.s, IsCommutable>,
3823 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3824 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3825 itins.d, IsCommutable>,
3826 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3827 itins.d, IsCommutable>,
3828 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3831 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3833 SizeItins itins, bit IsCommutable> {
3834 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3835 itins.s, IsCommutable>,
3836 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3837 itins.s, IsCommutable>,
3838 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3839 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3840 itins.d, IsCommutable>,
3841 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3842 itins.d, IsCommutable>,
3843 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3845 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3846 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3847 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3848 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3849 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 0>;
3850 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 0>;
3852 // MIN/MAX nodes are commutable under "unsafe-fp-math". In this case we use
3853 // X86fminc and X86fmaxc instead of X86fmin and X86fmax
3854 multiclass avx512_comutable_binop_s<bits<8> opc, string OpcodeStr,
3855 X86VectorVTInfo _, SDNode OpNode, OpndItins itins> {
3856 let isCodeGenOnly = 1, isCommutable =1, Predicates = [HasAVX512] in {
3857 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3858 (ins _.FRC:$src1, _.FRC:$src2),
3859 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3860 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3862 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3863 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3864 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3865 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3866 (_.ScalarLdFrag addr:$src2)))], itins.rm>;
3869 defm VMINCSSZ : avx512_comutable_binop_s<0x5D, "vminss", f32x_info, X86fminc,
3870 SSE_ALU_ITINS_S.s>, XS, EVEX_4V, VEX_LIG,
3871 EVEX_CD8<32, CD8VT1>;
3873 defm VMINCSDZ : avx512_comutable_binop_s<0x5D, "vminsd", f64x_info, X86fminc,
3874 SSE_ALU_ITINS_S.d>, XD, VEX_W, EVEX_4V, VEX_LIG,
3875 EVEX_CD8<64, CD8VT1>;
3877 defm VMAXCSSZ : avx512_comutable_binop_s<0x5F, "vmaxss", f32x_info, X86fmaxc,
3878 SSE_ALU_ITINS_S.s>, XS, EVEX_4V, VEX_LIG,
3879 EVEX_CD8<32, CD8VT1>;
3881 defm VMAXCSDZ : avx512_comutable_binop_s<0x5F, "vmaxsd", f64x_info, X86fmaxc,
3882 SSE_ALU_ITINS_S.d>, XD, VEX_W, EVEX_4V, VEX_LIG,
3883 EVEX_CD8<64, CD8VT1>;
3885 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3886 X86VectorVTInfo _, bit IsCommutable> {
3887 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3888 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3889 "$src2, $src1", "$src1, $src2",
3890 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3891 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3892 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3893 "$src2, $src1", "$src1, $src2",
3894 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3895 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3896 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3897 "${src2}"##_.BroadcastStr##", $src1",
3898 "$src1, ${src2}"##_.BroadcastStr,
3899 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3900 (_.ScalarLdFrag addr:$src2))))>,
3904 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3905 X86VectorVTInfo _> {
3906 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3907 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3908 "$rc, $src2, $src1", "$src1, $src2, $rc",
3909 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3910 EVEX_4V, EVEX_B, EVEX_RC;
3914 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3915 X86VectorVTInfo _> {
3916 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3917 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3918 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3919 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3923 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3924 Predicate prd, bit IsCommutable = 0> {
3925 let Predicates = [prd] in {
3926 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3927 IsCommutable>, EVEX_V512, PS,
3928 EVEX_CD8<32, CD8VF>;
3929 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3930 IsCommutable>, EVEX_V512, PD, VEX_W,
3931 EVEX_CD8<64, CD8VF>;
3934 // Define only if AVX512VL feature is present.
3935 let Predicates = [prd, HasVLX] in {
3936 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3937 IsCommutable>, EVEX_V128, PS,
3938 EVEX_CD8<32, CD8VF>;
3939 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3940 IsCommutable>, EVEX_V256, PS,
3941 EVEX_CD8<32, CD8VF>;
3942 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3943 IsCommutable>, EVEX_V128, PD, VEX_W,
3944 EVEX_CD8<64, CD8VF>;
3945 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3946 IsCommutable>, EVEX_V256, PD, VEX_W,
3947 EVEX_CD8<64, CD8VF>;
3951 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3952 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3953 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3954 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3955 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3958 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3959 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3960 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3961 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3962 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3965 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, HasAVX512, 1>,
3966 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3967 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, HasAVX512, 1>,
3968 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3969 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub, HasAVX512>,
3970 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3971 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv, HasAVX512>,
3972 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3973 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, HasAVX512, 0>,
3974 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3975 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, HasAVX512, 0>,
3976 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3977 let isCodeGenOnly = 1 in {
3978 defm VMINC : avx512_fp_binop_p<0x5D, "vmin", X86fminc, HasAVX512, 1>;
3979 defm VMAXC : avx512_fp_binop_p<0x5F, "vmax", X86fmaxc, HasAVX512, 1>;
3981 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, HasDQI, 1>;
3982 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, HasDQI, 0>;
3983 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, HasDQI, 1>;
3984 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, HasDQI, 1>;
3986 multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3987 X86VectorVTInfo _> {
3988 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3989 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3990 "$src2, $src1", "$src1, $src2",
3991 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>, EVEX_4V;
3992 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3993 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3994 "$src2, $src1", "$src1, $src2",
3995 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>, EVEX_4V;
3996 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3997 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3998 "${src2}"##_.BroadcastStr##", $src1",
3999 "$src1, ${src2}"##_.BroadcastStr,
4000 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4001 (_.ScalarLdFrag addr:$src2))), (i32 FROUND_CURRENT))>,
4005 multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
4006 X86VectorVTInfo _> {
4007 defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4008 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
4009 "$src2, $src1", "$src1, $src2",
4010 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
4011 defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4012 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
4013 "$src2, $src1", "$src1, $src2",
4015 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4016 (i32 FROUND_CURRENT))>;
4019 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode, SDNode OpNodeScal> {
4020 defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
4021 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
4022 EVEX_V512, EVEX_CD8<32, CD8VF>;
4023 defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
4024 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
4025 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4026 defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNodeScal, f32x_info>,
4027 avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNodeScal, SSE_ALU_ITINS_S.s>,
4028 EVEX_4V,EVEX_CD8<32, CD8VT1>;
4029 defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNodeScal, f64x_info>,
4030 avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNodeScal, SSE_ALU_ITINS_S.d>,
4031 EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
4033 // Define only if AVX512VL feature is present.
4034 let Predicates = [HasVLX] in {
4035 defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f32x_info>,
4036 EVEX_V128, EVEX_CD8<32, CD8VF>;
4037 defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f32x_info>,
4038 EVEX_V256, EVEX_CD8<32, CD8VF>;
4039 defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v2f64x_info>,
4040 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4041 defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f64x_info>,
4042 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4045 defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef, X86scalefs>, T8PD;
4047 //===----------------------------------------------------------------------===//
4048 // AVX-512 VPTESTM instructions
4049 //===----------------------------------------------------------------------===//
4051 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
4052 X86VectorVTInfo _> {
4053 let isCommutable = 1 in
4054 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
4055 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4056 "$src2, $src1", "$src1, $src2",
4057 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
4059 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
4060 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4061 "$src2, $src1", "$src1, $src2",
4062 (OpNode (_.VT _.RC:$src1),
4063 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
4065 EVEX_CD8<_.EltSize, CD8VF>;
4068 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
4069 X86VectorVTInfo _> {
4070 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
4071 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4072 "${src2}"##_.BroadcastStr##", $src1",
4073 "$src1, ${src2}"##_.BroadcastStr,
4074 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
4075 (_.ScalarLdFrag addr:$src2))))>,
4076 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4079 // Use 512bit version to implement 128/256 bit in case NoVLX.
4080 multiclass avx512_vptest_lowering<SDNode OpNode, X86VectorVTInfo ExtendInfo,
4081 X86VectorVTInfo _, string Suffix> {
4082 def : Pat<(_.KVT (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))),
4083 (_.KVT (COPY_TO_REGCLASS
4084 (!cast<Instruction>(NAME # Suffix # "Zrr")
4085 (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)),
4086 _.RC:$src1, _.SubRegIdx),
4087 (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)),
4088 _.RC:$src2, _.SubRegIdx)),
4092 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4093 AVX512VLVectorVTInfo _, string Suffix> {
4094 let Predicates = [HasAVX512] in
4095 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
4096 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4098 let Predicates = [HasAVX512, HasVLX] in {
4099 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
4100 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4101 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
4102 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
4104 let Predicates = [HasAVX512, NoVLX] in {
4105 defm Z256_Alt : avx512_vptest_lowering< OpNode, _.info512, _.info256, Suffix>;
4106 defm Z128_Alt : avx512_vptest_lowering< OpNode, _.info512, _.info128, Suffix>;
4110 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4111 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
4112 avx512vl_i32_info, "D">;
4113 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
4114 avx512vl_i64_info, "Q">, VEX_W;
4117 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
4119 let Predicates = [HasBWI] in {
4120 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
4122 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
4125 let Predicates = [HasVLX, HasBWI] in {
4127 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
4129 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
4131 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
4133 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
4137 let Predicates = [HasAVX512, NoVLX] in {
4138 defm BZ256_Alt : avx512_vptest_lowering< OpNode, v64i8_info, v32i8x_info, "B">;
4139 defm BZ128_Alt : avx512_vptest_lowering< OpNode, v64i8_info, v16i8x_info, "B">;
4140 defm WZ256_Alt : avx512_vptest_lowering< OpNode, v32i16_info, v16i16x_info, "W">;
4141 defm WZ128_Alt : avx512_vptest_lowering< OpNode, v32i16_info, v8i16x_info, "W">;
4146 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
4148 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
4149 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
4151 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
4152 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
4155 //===----------------------------------------------------------------------===//
4156 // AVX-512 Shift instructions
4157 //===----------------------------------------------------------------------===//
4158 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
4159 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
4160 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
4161 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
4162 "$src2, $src1", "$src1, $src2",
4163 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
4164 SSE_INTSHIFT_ITINS_P.rr>;
4165 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
4166 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
4167 "$src2, $src1", "$src1, $src2",
4168 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
4170 SSE_INTSHIFT_ITINS_P.rm>;
4173 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
4174 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
4175 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
4176 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
4177 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
4178 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
4179 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
4182 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4183 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
4184 // src2 is always 128-bit
4185 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4186 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
4187 "$src2, $src1", "$src1, $src2",
4188 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
4189 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
4190 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4191 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
4192 "$src2, $src1", "$src1, $src2",
4193 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
4194 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
4198 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4199 ValueType SrcVT, PatFrag bc_frag,
4200 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
4201 let Predicates = [prd] in
4202 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4203 VTInfo.info512>, EVEX_V512,
4204 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
4205 let Predicates = [prd, HasVLX] in {
4206 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4207 VTInfo.info256>, EVEX_V256,
4208 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
4209 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4210 VTInfo.info128>, EVEX_V128,
4211 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
4215 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
4216 string OpcodeStr, SDNode OpNode> {
4217 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
4218 avx512vl_i32_info, HasAVX512>;
4219 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
4220 avx512vl_i64_info, HasAVX512>, VEX_W;
4221 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
4222 avx512vl_i16_info, HasBWI>;
4225 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4226 string OpcodeStr, SDNode OpNode,
4227 AVX512VLVectorVTInfo VTInfo> {
4228 let Predicates = [HasAVX512] in
4229 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4231 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4232 VTInfo.info512>, EVEX_V512;
4233 let Predicates = [HasAVX512, HasVLX] in {
4234 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4236 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4237 VTInfo.info256>, EVEX_V256;
4238 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4240 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4241 VTInfo.info128>, EVEX_V128;
4245 multiclass avx512_shift_rmi_w<bits<8> opcw,
4246 Format ImmFormR, Format ImmFormM,
4247 string OpcodeStr, SDNode OpNode> {
4248 let Predicates = [HasBWI] in
4249 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4250 v32i16_info>, EVEX_V512;
4251 let Predicates = [HasVLX, HasBWI] in {
4252 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4253 v16i16x_info>, EVEX_V256;
4254 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4255 v8i16x_info>, EVEX_V128;
4259 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
4260 Format ImmFormR, Format ImmFormM,
4261 string OpcodeStr, SDNode OpNode> {
4262 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
4263 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
4264 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
4265 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
4268 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
4269 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
4271 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
4272 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
4274 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
4275 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
4277 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", X86vrotri>, AVX512BIi8Base, EVEX_4V;
4278 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", X86vrotli>, AVX512BIi8Base, EVEX_4V;
4280 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
4281 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
4282 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
4284 //===-------------------------------------------------------------------===//
4285 // Variable Bit Shifts
4286 //===-------------------------------------------------------------------===//
4287 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
4288 X86VectorVTInfo _> {
4289 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4290 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4291 "$src2, $src1", "$src1, $src2",
4292 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
4293 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
4294 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4295 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4296 "$src2, $src1", "$src1, $src2",
4297 (_.VT (OpNode _.RC:$src1,
4298 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
4299 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
4300 EVEX_CD8<_.EltSize, CD8VF>;
4303 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
4304 X86VectorVTInfo _> {
4305 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4306 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4307 "${src2}"##_.BroadcastStr##", $src1",
4308 "$src1, ${src2}"##_.BroadcastStr,
4309 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4310 (_.ScalarLdFrag addr:$src2))))),
4311 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
4312 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4314 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4315 AVX512VLVectorVTInfo _> {
4316 let Predicates = [HasAVX512] in
4317 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4318 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4320 let Predicates = [HasAVX512, HasVLX] in {
4321 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4322 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4323 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
4324 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
4328 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
4330 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
4332 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
4333 avx512vl_i64_info>, VEX_W;
4336 // Use 512bit version to implement 128/256 bit in case NoVLX.
4337 multiclass avx512_var_shift_w_lowering<AVX512VLVectorVTInfo _, SDNode OpNode> {
4338 let Predicates = [HasBWI, NoVLX] in {
4339 def : Pat<(_.info256.VT (OpNode (_.info256.VT _.info256.RC:$src1),
4340 (_.info256.VT _.info256.RC:$src2))),
4342 (!cast<Instruction>(NAME#"WZrr")
4343 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR256X:$src1, sub_ymm),
4344 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR256X:$src2, sub_ymm)),
4347 def : Pat<(_.info128.VT (OpNode (_.info128.VT _.info128.RC:$src1),
4348 (_.info128.VT _.info128.RC:$src2))),
4350 (!cast<Instruction>(NAME#"WZrr")
4351 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR128X:$src1, sub_xmm),
4352 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR128X:$src2, sub_xmm)),
4357 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
4359 let Predicates = [HasBWI] in
4360 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
4362 let Predicates = [HasVLX, HasBWI] in {
4364 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
4366 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
4371 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
4372 avx512_var_shift_w<0x12, "vpsllvw", shl>,
4373 avx512_var_shift_w_lowering<avx512vl_i16_info, shl>;
4375 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
4376 avx512_var_shift_w<0x11, "vpsravw", sra>,
4377 avx512_var_shift_w_lowering<avx512vl_i16_info, sra>;
4378 let isCodeGenOnly = 1 in
4379 defm VPSRAV_Int : avx512_var_shift_types<0x46, "vpsrav", X86vsrav>,
4380 avx512_var_shift_w<0x11, "vpsravw", X86vsrav>;
4382 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
4383 avx512_var_shift_w<0x10, "vpsrlvw", srl>,
4384 avx512_var_shift_w_lowering<avx512vl_i16_info, srl>;
4385 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
4386 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
4388 //===-------------------------------------------------------------------===//
4389 // 1-src variable permutation VPERMW/D/Q
4390 //===-------------------------------------------------------------------===//
4391 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4392 AVX512VLVectorVTInfo _> {
4393 let Predicates = [HasAVX512] in
4394 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4395 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4397 let Predicates = [HasAVX512, HasVLX] in
4398 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4399 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4402 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4403 string OpcodeStr, SDNode OpNode,
4404 AVX512VLVectorVTInfo VTInfo> {
4405 let Predicates = [HasAVX512] in
4406 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4408 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4409 VTInfo.info512>, EVEX_V512;
4410 let Predicates = [HasAVX512, HasVLX] in
4411 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4413 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4414 VTInfo.info256>, EVEX_V256;
4417 multiclass avx512_vperm_bw<bits<8> opc, string OpcodeStr,
4418 Predicate prd, SDNode OpNode,
4419 AVX512VLVectorVTInfo _> {
4420 let Predicates = [prd] in
4421 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4423 let Predicates = [HasVLX, prd] in {
4424 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4426 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
4431 defm VPERMW : avx512_vperm_bw<0x8D, "vpermw", HasBWI, X86VPermv,
4432 avx512vl_i16_info>, VEX_W;
4433 defm VPERMB : avx512_vperm_bw<0x8D, "vpermb", HasVBMI, X86VPermv,
4436 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
4438 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
4439 avx512vl_i64_info>, VEX_W;
4440 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
4442 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
4443 avx512vl_f64_info>, VEX_W;
4445 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
4446 X86VPermi, avx512vl_i64_info>,
4447 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4448 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
4449 X86VPermi, avx512vl_f64_info>,
4450 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4451 //===----------------------------------------------------------------------===//
4452 // AVX-512 - VPERMIL
4453 //===----------------------------------------------------------------------===//
4455 multiclass avx512_permil_vec<bits<8> OpcVar, string OpcodeStr, SDNode OpNode,
4456 X86VectorVTInfo _, X86VectorVTInfo Ctrl> {
4457 defm rr: AVX512_maskable<OpcVar, MRMSrcReg, _, (outs _.RC:$dst),
4458 (ins _.RC:$src1, Ctrl.RC:$src2), OpcodeStr,
4459 "$src2, $src1", "$src1, $src2",
4460 (_.VT (OpNode _.RC:$src1,
4461 (Ctrl.VT Ctrl.RC:$src2)))>,
4463 defm rm: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4464 (ins _.RC:$src1, Ctrl.MemOp:$src2), OpcodeStr,
4465 "$src2, $src1", "$src1, $src2",
4468 (Ctrl.VT (bitconvert(Ctrl.LdFrag addr:$src2)))))>,
4469 T8PD, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4470 defm rmb: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4471 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4472 "${src2}"##_.BroadcastStr##", $src1",
4473 "$src1, ${src2}"##_.BroadcastStr,
4476 (Ctrl.VT (X86VBroadcast
4477 (Ctrl.ScalarLdFrag addr:$src2)))))>,
4478 T8PD, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
4481 multiclass avx512_permil_vec_common<string OpcodeStr, bits<8> OpcVar,
4482 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4483 let Predicates = [HasAVX512] in {
4484 defm Z : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info512,
4485 Ctrl.info512>, EVEX_V512;
4487 let Predicates = [HasAVX512, HasVLX] in {
4488 defm Z128 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info128,
4489 Ctrl.info128>, EVEX_V128;
4490 defm Z256 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info256,
4491 Ctrl.info256>, EVEX_V256;
4495 multiclass avx512_permil<string OpcodeStr, bits<8> OpcImm, bits<8> OpcVar,
4496 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4498 defm NAME: avx512_permil_vec_common<OpcodeStr, OpcVar, _, Ctrl>;
4499 defm NAME: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem, OpcodeStr,
4501 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4504 defm VPERMILPS : avx512_permil<"vpermilps", 0x04, 0x0C, avx512vl_f32_info,
4506 defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info,
4507 avx512vl_i64_info>, VEX_W;
4508 //===----------------------------------------------------------------------===//
4509 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
4510 //===----------------------------------------------------------------------===//
4512 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
4513 X86PShufd, avx512vl_i32_info>,
4514 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
4515 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
4516 X86PShufhw>, EVEX, AVX512XSIi8Base;
4517 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
4518 X86PShuflw>, EVEX, AVX512XDIi8Base;
4520 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4521 let Predicates = [HasBWI] in
4522 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, v64i8_info>, EVEX_V512;
4524 let Predicates = [HasVLX, HasBWI] in {
4525 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, v32i8x_info>, EVEX_V256;
4526 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, v16i8x_info>, EVEX_V128;
4530 defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>;
4532 //===----------------------------------------------------------------------===//
4533 // Move Low to High and High to Low packed FP Instructions
4534 //===----------------------------------------------------------------------===//
4535 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
4536 (ins VR128X:$src1, VR128X:$src2),
4537 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4538 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
4539 IIC_SSE_MOV_LH>, EVEX_4V;
4540 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
4541 (ins VR128X:$src1, VR128X:$src2),
4542 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4543 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
4544 IIC_SSE_MOV_LH>, EVEX_4V;
4546 let Predicates = [HasAVX512] in {
4548 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4549 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
4550 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4551 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
4554 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
4555 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
4558 //===----------------------------------------------------------------------===//
4559 // VMOVHPS/PD VMOVLPS Instructions
4560 // All patterns was taken from SSS implementation.
4561 //===----------------------------------------------------------------------===//
4562 multiclass avx512_mov_hilo_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
4563 X86VectorVTInfo _> {
4564 def rm : AVX512<opc, MRMSrcMem, (outs _.RC:$dst),
4565 (ins _.RC:$src1, f64mem:$src2),
4566 !strconcat(OpcodeStr,
4567 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4571 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))))))],
4572 IIC_SSE_MOV_LH>, EVEX_4V;
4575 defm VMOVHPSZ128 : avx512_mov_hilo_packed<0x16, "vmovhps", X86Movlhps,
4576 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
4577 defm VMOVHPDZ128 : avx512_mov_hilo_packed<0x16, "vmovhpd", X86Movlhpd,
4578 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
4579 defm VMOVLPSZ128 : avx512_mov_hilo_packed<0x12, "vmovlps", X86Movlps,
4580 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
4581 defm VMOVLPDZ128 : avx512_mov_hilo_packed<0x12, "vmovlpd", X86Movlpd,
4582 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
4584 let Predicates = [HasAVX512] in {
4586 def : Pat<(X86Movlhps VR128X:$src1,
4587 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
4588 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
4589 def : Pat<(X86Movlhps VR128X:$src1,
4590 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
4591 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
4593 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
4594 (scalar_to_vector (loadf64 addr:$src2)))),
4595 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
4596 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
4597 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
4598 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
4600 def : Pat<(v4f32 (X86Movlps VR128X:$src1, (load addr:$src2))),
4601 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
4602 def : Pat<(v4i32 (X86Movlps VR128X:$src1, (load addr:$src2))),
4603 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
4605 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
4606 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4607 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
4608 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4609 def : Pat<(v2f64 (X86Movsd VR128X:$src1,
4610 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
4611 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4614 def VMOVHPSZ128mr : AVX512PSI<0x17, MRMDestMem, (outs),
4615 (ins f64mem:$dst, VR128X:$src),
4616 "vmovhps\t{$src, $dst|$dst, $src}",
4617 [(store (f64 (extractelt
4618 (X86Unpckh (bc_v2f64 (v4f32 VR128X:$src)),
4619 (bc_v2f64 (v4f32 VR128X:$src))),
4620 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
4621 EVEX, EVEX_CD8<32, CD8VT2>;
4622 def VMOVHPDZ128mr : AVX512PDI<0x17, MRMDestMem, (outs),
4623 (ins f64mem:$dst, VR128X:$src),
4624 "vmovhpd\t{$src, $dst|$dst, $src}",
4625 [(store (f64 (extractelt
4626 (v2f64 (X86Unpckh VR128X:$src, VR128X:$src)),
4627 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
4628 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
4629 def VMOVLPSZ128mr : AVX512PSI<0x13, MRMDestMem, (outs),
4630 (ins f64mem:$dst, VR128X:$src),
4631 "vmovlps\t{$src, $dst|$dst, $src}",
4632 [(store (f64 (extractelt (bc_v2f64 (v4f32 VR128X:$src)),
4633 (iPTR 0))), addr:$dst)],
4635 EVEX, EVEX_CD8<32, CD8VT2>;
4636 def VMOVLPDZ128mr : AVX512PDI<0x13, MRMDestMem, (outs),
4637 (ins f64mem:$dst, VR128X:$src),
4638 "vmovlpd\t{$src, $dst|$dst, $src}",
4639 [(store (f64 (extractelt (v2f64 VR128X:$src),
4640 (iPTR 0))), addr:$dst)],
4642 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
4644 let Predicates = [HasAVX512] in {
4646 def : Pat<(store (f64 (extractelt
4647 (v2f64 (X86VPermilpi VR128X:$src, (i8 1))),
4648 (iPTR 0))), addr:$dst),
4649 (VMOVHPDZ128mr addr:$dst, VR128X:$src)>;
4651 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128X:$src2)),
4653 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
4654 def : Pat<(store (v4i32 (X86Movlps
4655 (bc_v4i32 (loadv2i64 addr:$src1)), VR128X:$src2)), addr:$src1),
4656 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
4658 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
4660 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
4661 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
4663 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
4665 //===----------------------------------------------------------------------===//
4666 // FMA - Fused Multiply Operations
4669 let Constraints = "$src1 = $dst" in {
4670 multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4671 X86VectorVTInfo _> {
4672 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4673 (ins _.RC:$src2, _.RC:$src3),
4674 OpcodeStr, "$src3, $src2", "$src2, $src3",
4675 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4678 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4679 (ins _.RC:$src2, _.MemOp:$src3),
4680 OpcodeStr, "$src3, $src2", "$src2, $src3",
4681 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4684 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4685 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4686 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4687 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4689 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4690 AVX512FMA3Base, EVEX_B;
4693 multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4694 X86VectorVTInfo _> {
4695 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4696 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4697 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4698 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4699 AVX512FMA3Base, EVEX_B, EVEX_RC;
4701 } // Constraints = "$src1 = $dst"
4703 multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4704 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4705 let Predicates = [HasAVX512] in {
4706 defm Z : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info512>,
4707 avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4708 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4710 let Predicates = [HasVLX, HasAVX512] in {
4711 defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info256>,
4712 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4713 defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info128>,
4714 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4718 multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4719 SDNode OpNodeRnd > {
4720 defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4722 defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4723 avx512vl_f64_info>, VEX_W;
4726 defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>;
4727 defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>;
4728 defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>;
4729 defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>;
4730 defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>;
4731 defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>;
4734 let Constraints = "$src1 = $dst" in {
4735 multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4736 X86VectorVTInfo _> {
4737 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4738 (ins _.RC:$src2, _.RC:$src3),
4739 OpcodeStr, "$src3, $src2", "$src2, $src3",
4740 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1))>,
4743 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4744 (ins _.RC:$src2, _.MemOp:$src3),
4745 OpcodeStr, "$src3, $src2", "$src2, $src3",
4746 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>,
4749 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4750 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4751 OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
4752 "$src2, ${src3}"##_.BroadcastStr,
4753 (_.VT (OpNode _.RC:$src2,
4754 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
4755 _.RC:$src1))>, AVX512FMA3Base, EVEX_B;
4758 multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4759 X86VectorVTInfo _> {
4760 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4761 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4762 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4763 (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc)))>,
4764 AVX512FMA3Base, EVEX_B, EVEX_RC;
4766 } // Constraints = "$src1 = $dst"
4768 multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4769 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4770 let Predicates = [HasAVX512] in {
4771 defm Z : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info512>,
4772 avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4773 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4775 let Predicates = [HasVLX, HasAVX512] in {
4776 defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info256>,
4777 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4778 defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info128>,
4779 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4783 multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4784 SDNode OpNodeRnd > {
4785 defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4787 defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4788 avx512vl_f64_info>, VEX_W;
4791 defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>;
4792 defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>;
4793 defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>;
4794 defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>;
4795 defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>;
4796 defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>;
4798 let Constraints = "$src1 = $dst" in {
4799 multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4800 X86VectorVTInfo _> {
4801 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4802 (ins _.RC:$src3, _.RC:$src2),
4803 OpcodeStr, "$src2, $src3", "$src3, $src2",
4804 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4807 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4808 (ins _.RC:$src3, _.MemOp:$src2),
4809 OpcodeStr, "$src2, $src3", "$src3, $src2",
4810 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2), _.RC:$src3))>,
4813 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4814 (ins _.RC:$src3, _.ScalarMemOp:$src2),
4815 OpcodeStr, "${src2}"##_.BroadcastStr##", $src3",
4816 "$src3, ${src2}"##_.BroadcastStr,
4817 (_.VT (OpNode _.RC:$src1,
4818 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
4819 _.RC:$src3))>, AVX512FMA3Base, EVEX_B;
4822 multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4823 X86VectorVTInfo _> {
4824 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4825 (ins _.RC:$src3, _.RC:$src2, AVX512RC:$rc),
4826 OpcodeStr, "$rc, $src2, $src3", "$src3, $src2, $rc",
4827 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4828 AVX512FMA3Base, EVEX_B, EVEX_RC;
4830 } // Constraints = "$src1 = $dst"
4832 multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4833 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4834 let Predicates = [HasAVX512] in {
4835 defm Z : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info512>,
4836 avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4837 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4839 let Predicates = [HasVLX, HasAVX512] in {
4840 defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info256>,
4841 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4842 defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info128>,
4843 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4847 multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4848 SDNode OpNodeRnd > {
4849 defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4851 defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4852 avx512vl_f64_info>, VEX_W;
4855 defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>;
4856 defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>;
4857 defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>;
4858 defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>;
4859 defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>;
4860 defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>;
4863 let Constraints = "$src1 = $dst" in {
4864 multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4865 dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
4866 dag RHS_r, dag RHS_m > {
4867 defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4868 (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
4869 "$src3, $src2", "$src2, $src3", RHS_VEC_r>, AVX512FMA3Base;
4871 defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4872 (ins _.RC:$src2, _.ScalarMemOp:$src3), OpcodeStr,
4873 "$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
4875 defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4876 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4877 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb>,
4878 AVX512FMA3Base, EVEX_B, EVEX_RC;
4880 let isCodeGenOnly = 1 in {
4881 def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
4882 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
4883 !strconcat(OpcodeStr,
4884 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4886 def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
4887 (ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
4888 !strconcat(OpcodeStr,
4889 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4891 }// isCodeGenOnly = 1
4893 }// Constraints = "$src1 = $dst"
4895 multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4896 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, X86VectorVTInfo _ ,
4899 defm NAME#213#SUFF: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
4900 (_.VT (OpNodeRnd _.RC:$src2, _.RC:$src1, _.RC:$src3, (i32 FROUND_CURRENT))),
4901 (_.VT (OpNodeRnd _.RC:$src2, _.RC:$src1,
4902 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))), (i32 FROUND_CURRENT))),
4903 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src1, _.RC:$src3,
4905 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4907 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4908 (_.ScalarLdFrag addr:$src3))))>;
4910 defm NAME#231#SUFF: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
4911 (_.VT (OpNodeRnd _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 FROUND_CURRENT))),
4912 (_.VT (OpNodeRnd _.RC:$src2,
4913 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4914 _.RC:$src1, (i32 FROUND_CURRENT))),
4915 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src3, _.RC:$src1,
4917 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
4919 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
4920 (_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
4922 defm NAME#132#SUFF: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
4923 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src3, _.RC:$src2, (i32 FROUND_CURRENT))),
4924 (_.VT (OpNodeRnd _.RC:$src1,
4925 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4926 _.RC:$src2, (i32 FROUND_CURRENT))),
4927 (_.VT ( OpNodeRnd _.RC:$src1, _.RC:$src3, _.RC:$src2,
4929 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
4931 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
4932 (_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
4935 multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4936 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd>{
4937 let Predicates = [HasAVX512] in {
4938 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4939 OpNodeRnd, f32x_info, "SS">,
4940 EVEX_CD8<32, CD8VT1>, VEX_LIG;
4941 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4942 OpNodeRnd, f64x_info, "SD">,
4943 EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
4947 defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
4948 defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
4949 defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4950 defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4952 //===----------------------------------------------------------------------===//
4953 // AVX-512 Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit IFMA
4954 //===----------------------------------------------------------------------===//
4955 let Constraints = "$src1 = $dst" in {
4956 multiclass avx512_pmadd52_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4957 X86VectorVTInfo _> {
4958 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4959 (ins _.RC:$src2, _.RC:$src3),
4960 OpcodeStr, "$src3, $src2", "$src2, $src3",
4961 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4964 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4965 (ins _.RC:$src2, _.MemOp:$src3),
4966 OpcodeStr, "$src3, $src2", "$src2, $src3",
4967 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4970 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4971 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4972 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4973 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4975 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4976 AVX512FMA3Base, EVEX_B;
4978 } // Constraints = "$src1 = $dst"
4980 multiclass avx512_pmadd52_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4981 AVX512VLVectorVTInfo _> {
4982 let Predicates = [HasIFMA] in {
4983 defm Z : avx512_pmadd52_rm<opc, OpcodeStr, OpNode, _.info512>,
4984 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4986 let Predicates = [HasVLX, HasIFMA] in {
4987 defm Z256 : avx512_pmadd52_rm<opc, OpcodeStr, OpNode, _.info256>,
4988 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4989 defm Z128 : avx512_pmadd52_rm<opc, OpcodeStr, OpNode, _.info128>,
4990 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4994 defm VPMADD52LUQ : avx512_pmadd52_common<0xb4, "vpmadd52luq", x86vpmadd52l,
4995 avx512vl_i64_info>, VEX_W;
4996 defm VPMADD52HUQ : avx512_pmadd52_common<0xb5, "vpmadd52huq", x86vpmadd52h,
4997 avx512vl_i64_info>, VEX_W;
4999 //===----------------------------------------------------------------------===//
5000 // AVX-512 Scalar convert from sign integer to float/double
5001 //===----------------------------------------------------------------------===//
5003 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
5004 X86VectorVTInfo DstVT, X86MemOperand x86memop,
5005 PatFrag ld_frag, string asm> {
5006 let hasSideEffects = 0 in {
5007 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
5008 (ins DstVT.FRC:$src1, SrcRC:$src),
5009 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
5012 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
5013 (ins DstVT.FRC:$src1, x86memop:$src),
5014 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
5016 } // hasSideEffects = 0
5017 let isCodeGenOnly = 1 in {
5018 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
5019 (ins DstVT.RC:$src1, SrcRC:$src2),
5020 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5021 [(set DstVT.RC:$dst,
5022 (OpNode (DstVT.VT DstVT.RC:$src1),
5024 (i32 FROUND_CURRENT)))]>, EVEX_4V;
5026 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
5027 (ins DstVT.RC:$src1, x86memop:$src2),
5028 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5029 [(set DstVT.RC:$dst,
5030 (OpNode (DstVT.VT DstVT.RC:$src1),
5031 (ld_frag addr:$src2),
5032 (i32 FROUND_CURRENT)))]>, EVEX_4V;
5033 }//isCodeGenOnly = 1
5036 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
5037 X86VectorVTInfo DstVT, string asm> {
5038 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
5039 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
5041 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
5042 [(set DstVT.RC:$dst,
5043 (OpNode (DstVT.VT DstVT.RC:$src1),
5045 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
5048 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
5049 X86VectorVTInfo DstVT, X86MemOperand x86memop,
5050 PatFrag ld_frag, string asm> {
5051 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
5052 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
5056 let Predicates = [HasAVX512] in {
5057 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
5058 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
5059 XS, EVEX_CD8<32, CD8VT1>;
5060 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
5061 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
5062 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
5063 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
5064 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
5065 XD, EVEX_CD8<32, CD8VT1>;
5066 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
5067 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
5068 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
5070 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
5071 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
5072 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
5073 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
5074 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
5075 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
5076 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
5077 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
5079 def : Pat<(f32 (sint_to_fp GR32:$src)),
5080 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
5081 def : Pat<(f32 (sint_to_fp GR64:$src)),
5082 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
5083 def : Pat<(f64 (sint_to_fp GR32:$src)),
5084 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
5085 def : Pat<(f64 (sint_to_fp GR64:$src)),
5086 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
5088 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR32,
5089 v4f32x_info, i32mem, loadi32,
5090 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
5091 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
5092 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
5093 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
5094 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, GR32, v2f64x_info,
5095 i32mem, loadi32, "cvtusi2sd{l}">,
5096 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
5097 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
5098 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
5099 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
5101 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
5102 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
5103 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
5104 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
5105 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
5106 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
5107 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
5108 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
5110 def : Pat<(f32 (uint_to_fp GR32:$src)),
5111 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
5112 def : Pat<(f32 (uint_to_fp GR64:$src)),
5113 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
5114 def : Pat<(f64 (uint_to_fp GR32:$src)),
5115 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
5116 def : Pat<(f64 (uint_to_fp GR64:$src)),
5117 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
5120 //===----------------------------------------------------------------------===//
5121 // AVX-512 Scalar convert from float/double to integer
5122 //===----------------------------------------------------------------------===//
5123 multiclass avx512_cvt_s_int_round<bits<8> opc, X86VectorVTInfo SrcVT ,
5124 X86VectorVTInfo DstVT, SDNode OpNode, string asm> {
5125 let Predicates = [HasAVX512] in {
5126 def rr : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst), (ins SrcVT.RC:$src),
5127 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
5128 [(set DstVT.RC:$dst, (OpNode (SrcVT.VT SrcVT.RC:$src),(i32 FROUND_CURRENT)))]>,
5130 def rb : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst), (ins SrcVT.RC:$src, AVX512RC:$rc),
5131 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
5132 [(set DstVT.RC:$dst, (OpNode (SrcVT.VT SrcVT.RC:$src),(i32 imm:$rc)))]>,
5133 EVEX, VEX_LIG, EVEX_B, EVEX_RC;
5134 def rm : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst), (ins SrcVT.ScalarMemOp:$src),
5135 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
5136 [(set DstVT.RC:$dst, (OpNode
5137 (SrcVT.VT (scalar_to_vector (SrcVT.ScalarLdFrag addr:$src))),
5138 (i32 FROUND_CURRENT)))]>,
5140 } // Predicates = [HasAVX512]
5143 // Convert float/double to signed/unsigned int 32/64
5144 defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, f32x_info, i32x_info,
5145 X86cvts2si, "cvtss2si">,
5146 XS, EVEX_CD8<32, CD8VT1>;
5147 defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, f32x_info, i64x_info,
5148 X86cvts2si, "cvtss2si">,
5149 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
5150 defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, f32x_info, i32x_info,
5151 X86cvts2usi, "cvtss2usi">,
5152 XS, EVEX_CD8<32, CD8VT1>;
5153 defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, f32x_info, i64x_info,
5154 X86cvts2usi, "cvtss2usi">, XS, VEX_W,
5155 EVEX_CD8<32, CD8VT1>;
5156 defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, f64x_info, i32x_info,
5157 X86cvts2si, "cvtsd2si">,
5158 XD, EVEX_CD8<64, CD8VT1>;
5159 defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, f64x_info, i64x_info,
5160 X86cvts2si, "cvtsd2si">,
5161 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
5162 defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, f64x_info, i32x_info,
5163 X86cvts2usi, "cvtsd2usi">,
5164 XD, EVEX_CD8<64, CD8VT1>;
5165 defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, f64x_info, i64x_info,
5166 X86cvts2usi, "cvtsd2usi">, XD, VEX_W,
5167 EVEX_CD8<64, CD8VT1>;
5169 // The SSE version of these instructions are disabled for AVX512.
5170 // Therefore, the SSE intrinsics are mapped to the AVX512 instructions.
5171 let Predicates = [HasAVX512] in {
5172 def : Pat<(i32 (int_x86_sse_cvtss2si (v4f32 VR128X:$src))),
5173 (VCVTSS2SIZrr (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
5174 def : Pat<(i64 (int_x86_sse_cvtss2si64 (v4f32 VR128X:$src))),
5175 (VCVTSS2SI64Zrr (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
5176 def : Pat<(i32 (int_x86_sse2_cvtsd2si (v2f64 VR128X:$src))),
5177 (VCVTSD2SIZrr (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
5178 def : Pat<(i64 (int_x86_sse2_cvtsd2si64 (v2f64 VR128X:$src))),
5179 (VCVTSD2SI64Zrr (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
5182 let isCodeGenOnly = 1 , Predicates = [HasAVX512] in {
5183 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
5184 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
5185 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
5186 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
5187 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
5188 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
5189 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
5190 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
5191 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
5192 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
5193 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
5194 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
5196 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x7B, GR32, VR128X,
5197 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
5198 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
5199 } // isCodeGenOnly = 1, Predicates = [HasAVX512]
5201 // Convert float/double to signed/unsigned int 32/64 with truncation
5202 multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC,
5203 X86VectorVTInfo _DstRC, SDNode OpNode,
5205 let Predicates = [HasAVX512] in {
5206 def rr : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
5207 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
5208 [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX;
5209 def rb : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
5210 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
5212 def rm : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.ScalarMemOp:$src),
5213 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
5214 [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>,
5217 let isCodeGenOnly = 1 in {
5218 def rr_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
5219 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
5220 [(set _DstRC.RC:$dst, (OpNodeRnd (_SrcRC.VT _SrcRC.RC:$src),
5221 (i32 FROUND_CURRENT)))]>, EVEX, VEX_LIG;
5222 def rb_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
5223 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
5224 [(set _DstRC.RC:$dst, (OpNodeRnd (_SrcRC.VT _SrcRC.RC:$src),
5225 (i32 FROUND_NO_EXC)))]>,
5226 EVEX,VEX_LIG , EVEX_B;
5227 let mayLoad = 1, hasSideEffects = 0 in
5228 def rm_Int : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst),
5229 (ins _SrcRC.MemOp:$src),
5230 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
5233 } // isCodeGenOnly = 1
5238 defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i32x_info,
5239 fp_to_sint,X86cvtts2IntRnd>,
5240 XS, EVEX_CD8<32, CD8VT1>;
5241 defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i64x_info,
5242 fp_to_sint,X86cvtts2IntRnd>,
5243 VEX_W, XS, EVEX_CD8<32, CD8VT1>;
5244 defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i32x_info,
5245 fp_to_sint,X86cvtts2IntRnd>,
5246 XD, EVEX_CD8<64, CD8VT1>;
5247 defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i64x_info,
5248 fp_to_sint,X86cvtts2IntRnd>,
5249 VEX_W, XD, EVEX_CD8<64, CD8VT1>;
5251 defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i32x_info,
5252 fp_to_uint,X86cvtts2UIntRnd>,
5253 XS, EVEX_CD8<32, CD8VT1>;
5254 defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i64x_info,
5255 fp_to_uint,X86cvtts2UIntRnd>,
5256 XS,VEX_W, EVEX_CD8<32, CD8VT1>;
5257 defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i32x_info,
5258 fp_to_uint,X86cvtts2UIntRnd>,
5259 XD, EVEX_CD8<64, CD8VT1>;
5260 defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i64x_info,
5261 fp_to_uint,X86cvtts2UIntRnd>,
5262 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
5263 let Predicates = [HasAVX512] in {
5264 def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))),
5265 (VCVTTSS2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
5266 def : Pat<(i64 (int_x86_sse_cvttss2si64 (v4f32 VR128X:$src))),
5267 (VCVTTSS2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
5268 def : Pat<(i32 (int_x86_sse2_cvttsd2si (v2f64 VR128X:$src))),
5269 (VCVTTSD2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
5270 def : Pat<(i64 (int_x86_sse2_cvttsd2si64 (v2f64 VR128X:$src))),
5271 (VCVTTSD2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
5274 //===----------------------------------------------------------------------===//
5275 // AVX-512 Convert form float to double and back
5276 //===----------------------------------------------------------------------===//
5277 multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5278 X86VectorVTInfo _Src, SDNode OpNode> {
5279 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5280 (ins _.RC:$src1, _Src.RC:$src2), OpcodeStr,
5281 "$src2, $src1", "$src1, $src2",
5282 (_.VT (OpNode (_.VT _.RC:$src1),
5283 (_Src.VT _Src.RC:$src2)))>,
5284 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
5285 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5286 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2), OpcodeStr,
5287 "$src2, $src1", "$src1, $src2",
5288 (_.VT (OpNode (_.VT _.RC:$src1),
5289 (_Src.VT (scalar_to_vector
5290 (_Src.ScalarLdFrag addr:$src2)))))>,
5291 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
5294 // Scalar Coversion with SAE - suppress all exceptions
5295 multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5296 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5297 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5298 (ins _.RC:$src1, _Src.RC:$src2), OpcodeStr,
5299 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5300 (_.VT (OpNodeRnd (_.VT _.RC:$src1),
5301 (_Src.VT _Src.RC:$src2),
5302 (i32 FROUND_NO_EXC)))>,
5303 EVEX_4V, VEX_LIG, EVEX_B;
5306 // Scalar Conversion with rounding control (RC)
5307 multiclass avx512_cvt_fp_rc_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5308 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5309 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5310 (ins _.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,
5311 "$rc, $src2, $src1", "$src1, $src2, $rc",
5312 (_.VT (OpNodeRnd (_.VT _.RC:$src1),
5313 (_Src.VT _Src.RC:$src2), (i32 imm:$rc)))>,
5314 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
5317 multiclass avx512_cvt_fp_scalar_sd2ss<bits<8> opc, string OpcodeStr, SDNode OpNode,
5318 SDNode OpNodeRnd, X86VectorVTInfo _src,
5319 X86VectorVTInfo _dst> {
5320 let Predicates = [HasAVX512] in {
5321 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
5322 avx512_cvt_fp_rc_scalar<opc, OpcodeStr, _dst, _src,
5323 OpNodeRnd>, VEX_W, EVEX_CD8<64, CD8VT1>,
5328 multiclass avx512_cvt_fp_scalar_ss2sd<bits<8> opc, string OpcodeStr, SDNode OpNode,
5329 SDNode OpNodeRnd, X86VectorVTInfo _src,
5330 X86VectorVTInfo _dst> {
5331 let Predicates = [HasAVX512] in {
5332 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
5333 avx512_cvt_fp_sae_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
5334 EVEX_CD8<32, CD8VT1>, XS, EVEX_V512;
5337 defm VCVTSD2SS : avx512_cvt_fp_scalar_sd2ss<0x5A, "vcvtsd2ss", X86fround,
5338 X86froundRnd, f64x_info, f32x_info>;
5339 defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd", X86fpext,
5340 X86fpextRnd,f32x_info, f64x_info >;
5342 def : Pat<(f64 (fextend FR32X:$src)),
5343 (COPY_TO_REGCLASS (VCVTSS2SDZrr (COPY_TO_REGCLASS FR32X:$src, VR128X),
5344 (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>,
5345 Requires<[HasAVX512]>;
5346 def : Pat<(f64 (fextend (loadf32 addr:$src))),
5347 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5348 Requires<[HasAVX512]>;
5350 def : Pat<(f64 (extloadf32 addr:$src)),
5351 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5352 Requires<[HasAVX512, OptForSize]>;
5354 def : Pat<(f64 (extloadf32 addr:$src)),
5355 (COPY_TO_REGCLASS (VCVTSS2SDZrr (v4f32 (IMPLICIT_DEF)),
5356 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)), VR128X)>,
5357 Requires<[HasAVX512, OptForSpeed]>;
5359 def : Pat<(f32 (fround FR64X:$src)),
5360 (COPY_TO_REGCLASS (VCVTSD2SSZrr (COPY_TO_REGCLASS FR64X:$src, VR128X),
5361 (COPY_TO_REGCLASS FR64X:$src, VR128X)), VR128X)>,
5362 Requires<[HasAVX512]>;
5363 //===----------------------------------------------------------------------===//
5364 // AVX-512 Vector convert from signed/unsigned integer to float/double
5365 // and from float/double to signed/unsigned integer
5366 //===----------------------------------------------------------------------===//
5368 multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5369 X86VectorVTInfo _Src, SDNode OpNode,
5370 string Broadcast = _.BroadcastStr,
5371 string Alias = ""> {
5373 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5374 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
5375 (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
5377 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5378 (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
5379 (_.VT (OpNode (_Src.VT
5380 (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
5382 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5383 (ins _Src.ScalarMemOp:$src), OpcodeStr,
5384 "${src}"##Broadcast, "${src}"##Broadcast,
5385 (_.VT (OpNode (_Src.VT
5386 (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
5389 // Coversion with SAE - suppress all exceptions
5390 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5391 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5392 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5393 (ins _Src.RC:$src), OpcodeStr,
5394 "{sae}, $src", "$src, {sae}",
5395 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
5396 (i32 FROUND_NO_EXC)))>,
5400 // Conversion with rounding control (RC)
5401 multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5402 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5403 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5404 (ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
5405 "$rc, $src", "$src, $rc",
5406 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
5407 EVEX, EVEX_B, EVEX_RC;
5410 // Extend Float to Double
5411 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
5412 let Predicates = [HasAVX512] in {
5413 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fextend>,
5414 avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
5415 X86vfpextRnd>, EVEX_V512;
5417 let Predicates = [HasVLX] in {
5418 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
5419 X86vfpext, "{1to2}">, EVEX_V128;
5420 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fextend>,
5425 // Truncate Double to Float
5426 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
5427 let Predicates = [HasAVX512] in {
5428 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fround>,
5429 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
5430 X86vfproundRnd>, EVEX_V512;
5432 let Predicates = [HasVLX] in {
5433 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
5434 X86vfpround, "{1to2}", "{x}">, EVEX_V128;
5435 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fround,
5436 "{1to4}", "{y}">, EVEX_V256;
5440 defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
5441 VEX_W, PD, EVEX_CD8<64, CD8VF>;
5442 defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
5443 PS, EVEX_CD8<32, CD8VH>;
5445 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5446 (VCVTPS2PDZrm addr:$src)>;
5448 let Predicates = [HasVLX] in {
5449 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
5450 (VCVTPS2PDZ256rm addr:$src)>;
5453 // Convert Signed/Unsigned Doubleword to Double
5454 multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
5456 // No rounding in this op
5457 let Predicates = [HasAVX512] in
5458 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
5461 let Predicates = [HasVLX] in {
5462 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
5463 OpNode128, "{1to2}">, EVEX_V128;
5464 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
5469 // Convert Signed/Unsigned Doubleword to Float
5470 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
5472 let Predicates = [HasAVX512] in
5473 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
5474 avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
5475 OpNodeRnd>, EVEX_V512;
5477 let Predicates = [HasVLX] in {
5478 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
5480 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
5485 // Convert Float to Signed/Unsigned Doubleword with truncation
5486 multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
5487 SDNode OpNode, SDNode OpNodeRnd> {
5488 let Predicates = [HasAVX512] in {
5489 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5490 avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
5491 OpNodeRnd>, EVEX_V512;
5493 let Predicates = [HasVLX] in {
5494 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5496 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5501 // Convert Float to Signed/Unsigned Doubleword
5502 multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
5503 SDNode OpNode, SDNode OpNodeRnd> {
5504 let Predicates = [HasAVX512] in {
5505 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5506 avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
5507 OpNodeRnd>, EVEX_V512;
5509 let Predicates = [HasVLX] in {
5510 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5512 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5517 // Convert Double to Signed/Unsigned Doubleword with truncation
5518 multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr,
5519 SDNode OpNode, SDNode OpNodeRnd> {
5520 let Predicates = [HasAVX512] in {
5521 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5522 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
5523 OpNodeRnd>, EVEX_V512;
5525 let Predicates = [HasVLX] in {
5526 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5527 // memory forms of these instructions in Asm Parcer. They have the same
5528 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5529 // due to the same reason.
5530 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5531 "{1to2}", "{x}">, EVEX_V128;
5532 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5533 "{1to4}", "{y}">, EVEX_V256;
5537 // Convert Double to Signed/Unsigned Doubleword
5538 multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
5539 SDNode OpNode, SDNode OpNodeRnd> {
5540 let Predicates = [HasAVX512] in {
5541 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5542 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
5543 OpNodeRnd>, EVEX_V512;
5545 let Predicates = [HasVLX] in {
5546 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5547 // memory forms of these instructions in Asm Parcer. They have the same
5548 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5549 // due to the same reason.
5550 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5551 "{1to2}", "{x}">, EVEX_V128;
5552 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5553 "{1to4}", "{y}">, EVEX_V256;
5557 // Convert Double to Signed/Unsigned Quardword
5558 multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
5559 SDNode OpNode, SDNode OpNodeRnd> {
5560 let Predicates = [HasDQI] in {
5561 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5562 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
5563 OpNodeRnd>, EVEX_V512;
5565 let Predicates = [HasDQI, HasVLX] in {
5566 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5568 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5573 // Convert Double to Signed/Unsigned Quardword with truncation
5574 multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
5575 SDNode OpNode, SDNode OpNodeRnd> {
5576 let Predicates = [HasDQI] in {
5577 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5578 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
5579 OpNodeRnd>, EVEX_V512;
5581 let Predicates = [HasDQI, HasVLX] in {
5582 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5584 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5589 // Convert Signed/Unsigned Quardword to Double
5590 multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
5591 SDNode OpNode, SDNode OpNodeRnd> {
5592 let Predicates = [HasDQI] in {
5593 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
5594 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
5595 OpNodeRnd>, EVEX_V512;
5597 let Predicates = [HasDQI, HasVLX] in {
5598 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
5600 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
5605 // Convert Float to Signed/Unsigned Quardword
5606 multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
5607 SDNode OpNode, SDNode OpNodeRnd> {
5608 let Predicates = [HasDQI] in {
5609 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5610 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
5611 OpNodeRnd>, EVEX_V512;
5613 let Predicates = [HasDQI, HasVLX] in {
5614 // Explicitly specified broadcast string, since we take only 2 elements
5615 // from v4f32x_info source
5616 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5617 "{1to2}">, EVEX_V128;
5618 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5623 // Convert Float to Signed/Unsigned Quardword with truncation
5624 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
5625 SDNode OpNode, SDNode OpNodeRnd> {
5626 let Predicates = [HasDQI] in {
5627 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5628 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
5629 OpNodeRnd>, EVEX_V512;
5631 let Predicates = [HasDQI, HasVLX] in {
5632 // Explicitly specified broadcast string, since we take only 2 elements
5633 // from v4f32x_info source
5634 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5635 "{1to2}">, EVEX_V128;
5636 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5641 // Convert Signed/Unsigned Quardword to Float
5642 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
5643 SDNode OpNode, SDNode OpNodeRnd> {
5644 let Predicates = [HasDQI] in {
5645 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
5646 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
5647 OpNodeRnd>, EVEX_V512;
5649 let Predicates = [HasDQI, HasVLX] in {
5650 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5651 // memory forms of these instructions in Asm Parcer. They have the same
5652 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5653 // due to the same reason.
5654 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
5655 "{1to2}", "{x}">, EVEX_V128;
5656 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
5657 "{1to4}", "{y}">, EVEX_V256;
5661 defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
5662 EVEX_CD8<32, CD8VH>;
5664 defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
5666 PS, EVEX_CD8<32, CD8VF>;
5668 defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
5670 XS, EVEX_CD8<32, CD8VF>;
5672 defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint,
5674 PD, VEX_W, EVEX_CD8<64, CD8VF>;
5676 defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
5677 X86VFpToUintRnd>, PS,
5678 EVEX_CD8<32, CD8VF>;
5680 defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
5681 X86VFpToUintRnd>, PS, VEX_W,
5682 EVEX_CD8<64, CD8VF>;
5684 defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86cvtudq2pd>,
5685 XS, EVEX_CD8<32, CD8VH>;
5687 defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
5688 X86VUintToFpRnd>, XD,
5689 EVEX_CD8<32, CD8VF>;
5691 defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtp2Int,
5692 X86cvtp2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
5694 defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtp2Int,
5695 X86cvtp2IntRnd>, XD, VEX_W,
5696 EVEX_CD8<64, CD8VF>;
5698 defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtp2UInt,
5700 PS, EVEX_CD8<32, CD8VF>;
5701 defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtp2UInt,
5702 X86cvtp2UIntRnd>, VEX_W,
5703 PS, EVEX_CD8<64, CD8VF>;
5705 defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtp2Int,
5706 X86cvtp2IntRnd>, VEX_W,
5707 PD, EVEX_CD8<64, CD8VF>;
5709 defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtp2Int,
5710 X86cvtp2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
5712 defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtp2UInt,
5713 X86cvtp2UIntRnd>, VEX_W,
5714 PD, EVEX_CD8<64, CD8VF>;
5716 defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtp2UInt,
5717 X86cvtp2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
5719 defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
5720 X86VFpToSintRnd>, VEX_W,
5721 PD, EVEX_CD8<64, CD8VF>;
5723 defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint,
5724 X86VFpToSintRnd>, PD, EVEX_CD8<32, CD8VH>;
5726 defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
5727 X86VFpToUintRnd>, VEX_W,
5728 PD, EVEX_CD8<64, CD8VF>;
5730 defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint,
5731 X86VFpToUintRnd>, PD, EVEX_CD8<32, CD8VH>;
5733 defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
5734 X86VSintToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5736 defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
5737 X86VUintToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5739 defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
5740 X86VSintToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
5742 defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
5743 X86VUintToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
5745 let Predicates = [HasAVX512, NoVLX] in {
5746 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
5747 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5748 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5750 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
5751 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5752 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5754 def : Pat<(v4i32 (fp_to_uint (v4f64 VR256X:$src1))),
5755 (EXTRACT_SUBREG (v8i32 (VCVTTPD2UDQZrr
5756 (v8f64 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_xmm)>;
5758 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
5759 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5760 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5762 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
5763 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5764 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5766 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
5767 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
5768 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
5771 let Predicates = [HasAVX512] in {
5772 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
5773 (VCVTPD2PSZrm addr:$src)>;
5774 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5775 (VCVTPS2PDZrm addr:$src)>;
5778 //===----------------------------------------------------------------------===//
5779 // Half precision conversion instructions
5780 //===----------------------------------------------------------------------===//
5781 multiclass avx512_cvtph2ps<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5782 X86MemOperand x86memop, PatFrag ld_frag> {
5783 defm rr : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5784 "vcvtph2ps", "$src", "$src",
5785 (X86cvtph2ps (_src.VT _src.RC:$src),
5786 (i32 FROUND_CURRENT))>, T8PD;
5787 defm rm : AVX512_maskable<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst), (ins x86memop:$src),
5788 "vcvtph2ps", "$src", "$src",
5789 (X86cvtph2ps (_src.VT (bitconvert (ld_frag addr:$src))),
5790 (i32 FROUND_CURRENT))>, T8PD;
5793 multiclass avx512_cvtph2ps_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5794 defm rb : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5795 "vcvtph2ps", "{sae}, $src", "$src, {sae}",
5796 (X86cvtph2ps (_src.VT _src.RC:$src),
5797 (i32 FROUND_NO_EXC))>, T8PD, EVEX_B;
5801 let Predicates = [HasAVX512] in {
5802 defm VCVTPH2PSZ : avx512_cvtph2ps<v16f32_info, v16i16x_info, f256mem, loadv4i64>,
5803 avx512_cvtph2ps_sae<v16f32_info, v16i16x_info>,
5804 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5805 let Predicates = [HasVLX] in {
5806 defm VCVTPH2PSZ256 : avx512_cvtph2ps<v8f32x_info, v8i16x_info, f128mem,
5807 loadv2i64>,EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5808 defm VCVTPH2PSZ128 : avx512_cvtph2ps<v4f32x_info, v8i16x_info, f64mem,
5809 loadv2i64>, EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5813 multiclass avx512_cvtps2ph<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5814 X86MemOperand x86memop> {
5815 defm rr : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5816 (ins _src.RC:$src1, i32u8imm:$src2),
5817 "vcvtps2ph", "$src2, $src1", "$src1, $src2",
5818 (X86cvtps2ph (_src.VT _src.RC:$src1),
5820 (i32 FROUND_CURRENT)),
5821 NoItinerary, 0, X86select>, AVX512AIi8Base;
5822 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
5823 (ins x86memop:$dst, _src.RC:$src1, i32u8imm:$src2),
5824 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5825 [(store (_dest.VT (X86cvtps2ph (_src.VT _src.RC:$src1),
5826 (i32 imm:$src2), (i32 FROUND_CURRENT) )),
5828 let hasSideEffects = 0, mayStore = 1 in
5829 def mrk : AVX512AIi8<0x1D, MRMDestMem, (outs),
5830 (ins x86memop:$dst, _dest.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2),
5831 "vcvtps2ph\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
5834 multiclass avx512_cvtps2ph_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5835 defm rb : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5836 (ins _src.RC:$src1, i32u8imm:$src2),
5837 "vcvtps2ph", "$src2, {sae}, $src1", "$src1, {sae}, $src2",
5838 (X86cvtps2ph (_src.VT _src.RC:$src1),
5840 (i32 FROUND_NO_EXC)),
5841 NoItinerary, 0, X86select>, EVEX_B, AVX512AIi8Base;
5843 let Predicates = [HasAVX512] in {
5844 defm VCVTPS2PHZ : avx512_cvtps2ph<v16i16x_info, v16f32_info, f256mem>,
5845 avx512_cvtps2ph_sae<v16i16x_info, v16f32_info>,
5846 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5847 let Predicates = [HasVLX] in {
5848 defm VCVTPS2PHZ256 : avx512_cvtps2ph<v8i16x_info, v8f32x_info, f128mem>,
5849 EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5850 defm VCVTPS2PHZ128 : avx512_cvtps2ph<v8i16x_info, v4f32x_info, f128mem>,
5851 EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5855 // Unordered/Ordered scalar fp compare with Sea and set EFLAGS
5856 multiclass avx512_ord_cmp_sae<bits<8> opc, X86VectorVTInfo _, SDNode OpNode,
5858 def rb: AVX512<opc, MRMSrcReg, (outs), (ins _.RC:$src1, _.RC:$src2),
5859 !strconcat(OpcodeStr, "\t{{sae}, $src2, $src1|$src1, $src2, {sae}}"),
5860 [(set EFLAGS, (OpNode (_.VT _.RC:$src1), _.RC:$src2,
5861 (i32 FROUND_NO_EXC)))],
5862 IIC_SSE_COMIS_RR>, EVEX, EVEX_B, VEX_LIG, EVEX_V128,
5866 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5867 defm VUCOMISSZ : avx512_ord_cmp_sae<0x2E, v4f32x_info, X86ucomiSae, "vucomiss">,
5868 AVX512PSIi8Base, EVEX_CD8<32, CD8VT1>;
5869 defm VUCOMISDZ : avx512_ord_cmp_sae<0x2E, v2f64x_info, X86ucomiSae, "vucomisd">,
5870 AVX512PDIi8Base, VEX_W, EVEX_CD8<64, CD8VT1>;
5871 defm VCOMISSZ : avx512_ord_cmp_sae<0x2F, v4f32x_info, X86comiSae, "vcomiss">,
5872 AVX512PSIi8Base, EVEX_CD8<32, CD8VT1>;
5873 defm VCOMISDZ : avx512_ord_cmp_sae<0x2F, v2f64x_info, X86comiSae, "vcomisd">,
5874 AVX512PDIi8Base, VEX_W, EVEX_CD8<64, CD8VT1>;
5877 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5878 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
5879 "ucomiss">, PS, EVEX, VEX_LIG,
5880 EVEX_CD8<32, CD8VT1>;
5881 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
5882 "ucomisd">, PD, EVEX,
5883 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5884 let Pattern = []<dag> in {
5885 defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
5886 "comiss">, PS, EVEX, VEX_LIG,
5887 EVEX_CD8<32, CD8VT1>;
5888 defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
5889 "comisd">, PD, EVEX,
5890 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5892 let isCodeGenOnly = 1 in {
5893 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
5894 load, "ucomiss">, PS, EVEX, VEX_LIG,
5895 EVEX_CD8<32, CD8VT1>;
5896 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
5897 load, "ucomisd">, PD, EVEX,
5898 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5900 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
5901 load, "comiss">, PS, EVEX, VEX_LIG,
5902 EVEX_CD8<32, CD8VT1>;
5903 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
5904 load, "comisd">, PD, EVEX,
5905 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5909 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
5910 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
5911 X86VectorVTInfo _> {
5912 let AddedComplexity = 20 , Predicates = [HasAVX512] in {
5913 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5914 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5915 "$src2, $src1", "$src1, $src2",
5916 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>, EVEX_4V;
5917 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5918 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
5919 "$src2, $src1", "$src1, $src2",
5920 (OpNode (_.VT _.RC:$src1),
5921 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))))>, EVEX_4V;
5925 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86frcp14s, f32x_info>,
5926 EVEX_CD8<32, CD8VT1>, T8PD;
5927 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86frcp14s, f64x_info>,
5928 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5929 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86frsqrt14s, f32x_info>,
5930 EVEX_CD8<32, CD8VT1>, T8PD;
5931 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86frsqrt14s, f64x_info>,
5932 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5934 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
5935 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
5936 X86VectorVTInfo _> {
5937 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5938 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5939 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
5940 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5941 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5943 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
5944 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5945 (ins _.ScalarMemOp:$src), OpcodeStr,
5946 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5948 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5952 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5953 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
5954 EVEX_V512, EVEX_CD8<32, CD8VF>;
5955 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
5956 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5958 // Define only if AVX512VL feature is present.
5959 let Predicates = [HasVLX] in {
5960 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5961 OpNode, v4f32x_info>,
5962 EVEX_V128, EVEX_CD8<32, CD8VF>;
5963 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5964 OpNode, v8f32x_info>,
5965 EVEX_V256, EVEX_CD8<32, CD8VF>;
5966 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5967 OpNode, v2f64x_info>,
5968 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
5969 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5970 OpNode, v4f64x_info>,
5971 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
5975 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
5976 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
5978 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
5979 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5982 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5983 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5984 "$src2, $src1", "$src1, $src2",
5985 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5986 (i32 FROUND_CURRENT))>;
5988 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5989 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5990 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5991 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5992 (i32 FROUND_NO_EXC))>, EVEX_B;
5994 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5995 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
5996 "$src2, $src1", "$src1, $src2",
5997 (OpNode (_.VT _.RC:$src1),
5998 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5999 (i32 FROUND_CURRENT))>;
6002 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6003 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
6004 EVEX_CD8<32, CD8VT1>;
6005 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
6006 EVEX_CD8<64, CD8VT1>, VEX_W;
6009 let Predicates = [HasERI] in {
6010 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
6011 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
6014 defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds>, T8PD, EVEX_4V;
6015 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
6017 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6020 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6021 (ins _.RC:$src), OpcodeStr, "$src", "$src",
6022 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
6024 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6025 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
6027 (bitconvert (_.LdFrag addr:$src))),
6028 (i32 FROUND_CURRENT))>;
6030 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6031 (ins _.ScalarMemOp:$src), OpcodeStr,
6032 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
6034 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
6035 (i32 FROUND_CURRENT))>, EVEX_B;
6037 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6039 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6040 (ins _.RC:$src), OpcodeStr,
6041 "{sae}, $src", "$src, {sae}",
6042 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
6045 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6046 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
6047 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
6048 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
6049 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
6050 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
6051 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
6054 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
6056 // Define only if AVX512VL feature is present.
6057 let Predicates = [HasVLX] in {
6058 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
6059 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
6060 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
6061 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
6062 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
6063 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
6064 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
6065 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
6068 let Predicates = [HasERI] in {
6070 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
6071 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
6072 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
6074 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
6075 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
6077 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
6078 SDNode OpNodeRnd, X86VectorVTInfo _>{
6079 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6080 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
6081 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
6082 EVEX, EVEX_B, EVEX_RC;
6085 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
6086 SDNode OpNode, X86VectorVTInfo _>{
6087 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6088 (ins _.RC:$src), OpcodeStr, "$src", "$src",
6089 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
6090 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6091 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
6093 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
6095 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6096 (ins _.ScalarMemOp:$src), OpcodeStr,
6097 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
6099 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
6103 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
6105 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
6107 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
6108 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
6110 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
6111 // Define only if AVX512VL feature is present.
6112 let Predicates = [HasVLX] in {
6113 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
6114 OpNode, v4f32x_info>,
6115 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
6116 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
6117 OpNode, v8f32x_info>,
6118 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
6119 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
6120 OpNode, v2f64x_info>,
6121 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
6122 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
6123 OpNode, v4f64x_info>,
6124 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
6128 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
6130 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
6131 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
6132 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
6133 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
6136 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
6137 string SUFF, SDNode OpNode, SDNode OpNodeRnd> {
6139 defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6140 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
6141 "$src2, $src1", "$src1, $src2",
6142 (OpNodeRnd (_.VT _.RC:$src1),
6144 (i32 FROUND_CURRENT))>;
6145 defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6146 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
6147 "$src2, $src1", "$src1, $src2",
6148 (OpNodeRnd (_.VT _.RC:$src1),
6149 (_.VT (scalar_to_vector
6150 (_.ScalarLdFrag addr:$src2))),
6151 (i32 FROUND_CURRENT))>;
6153 defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6154 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
6155 "$rc, $src2, $src1", "$src1, $src2, $rc",
6156 (OpNodeRnd (_.VT _.RC:$src1),
6161 let isCodeGenOnly = 1, hasSideEffects = 0 in {
6162 def r : I<opc, MRMSrcReg, (outs _.FRC:$dst),
6163 (ins _.FRC:$src1, _.FRC:$src2),
6164 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
6167 def m : I<opc, MRMSrcMem, (outs _.FRC:$dst),
6168 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
6169 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
6172 def : Pat<(_.EltVT (OpNode _.FRC:$src)),
6173 (!cast<Instruction>(NAME#SUFF#Zr)
6174 (_.EltVT (IMPLICIT_DEF)), _.FRC:$src)>;
6176 def : Pat<(_.EltVT (OpNode (load addr:$src))),
6177 (!cast<Instruction>(NAME#SUFF#Zm)
6178 (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512, OptForSize]>;
6181 multiclass avx512_sqrt_scalar_all<bits<8> opc, string OpcodeStr> {
6182 defm SSZ : avx512_sqrt_scalar<opc, OpcodeStr#"ss", f32x_info, "SS", fsqrt,
6183 X86fsqrtRnds>, EVEX_CD8<32, CD8VT1>, EVEX_4V, XS;
6184 defm SDZ : avx512_sqrt_scalar<opc, OpcodeStr#"sd", f64x_info, "SD", fsqrt,
6185 X86fsqrtRnds>, EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, VEX_W;
6188 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
6189 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
6191 defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt">, VEX_LIG;
6193 let Predicates = [HasAVX512] in {
6194 def : Pat<(f32 (X86frsqrt FR32X:$src)),
6195 (COPY_TO_REGCLASS (VRSQRT14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>;
6196 def : Pat<(f32 (X86frsqrt (load addr:$src))),
6197 (COPY_TO_REGCLASS (VRSQRT14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
6198 Requires<[OptForSize]>;
6199 def : Pat<(f32 (X86frcp FR32X:$src)),
6200 (COPY_TO_REGCLASS (VRCP14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X )>;
6201 def : Pat<(f32 (X86frcp (load addr:$src))),
6202 (COPY_TO_REGCLASS (VRCP14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
6203 Requires<[OptForSize]>;
6207 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
6209 let ExeDomain = _.ExeDomain in {
6210 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6211 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
6212 "$src3, $src2, $src1", "$src1, $src2, $src3",
6213 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
6214 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
6216 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6217 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
6218 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
6219 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
6220 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
6222 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6223 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
6225 "$src3, $src2, $src1", "$src1, $src2, $src3",
6226 (_.VT (X86RndScales (_.VT _.RC:$src1),
6227 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
6228 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
6230 let Predicates = [HasAVX512] in {
6231 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
6232 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
6233 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
6234 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
6235 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
6236 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
6237 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
6238 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
6239 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
6240 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
6241 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
6242 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
6243 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
6244 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
6245 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
6247 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6248 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6249 addr:$src, (i32 0x1))), _.FRC)>;
6250 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6251 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6252 addr:$src, (i32 0x2))), _.FRC)>;
6253 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6254 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6255 addr:$src, (i32 0x3))), _.FRC)>;
6256 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6257 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6258 addr:$src, (i32 0x4))), _.FRC)>;
6259 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6260 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6261 addr:$src, (i32 0xc))), _.FRC)>;
6265 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
6266 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6268 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
6269 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
6271 //-------------------------------------------------
6272 // Integer truncate and extend operations
6273 //-------------------------------------------------
6275 multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
6276 X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,
6277 X86MemOperand x86memop> {
6279 defm rr : AVX512_maskable<opc, MRMDestReg, DestInfo, (outs DestInfo.RC:$dst),
6280 (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",
6281 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,
6284 // for intrinsic patter match
6285 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6286 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6288 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
6291 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6292 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6293 DestInfo.ImmAllZerosV)),
6294 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
6297 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6298 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6299 DestInfo.RC:$src0)),
6300 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,
6301 DestInfo.KRCWM:$mask ,
6304 let mayStore = 1, mayLoad = 1, hasSideEffects = 0 in {
6305 def mr : AVX512XS8I<opc, MRMDestMem, (outs),
6306 (ins x86memop:$dst, SrcInfo.RC:$src),
6307 OpcodeStr # "\t{$src, $dst|$dst, $src}",
6310 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
6311 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
6312 OpcodeStr # "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
6314 }//mayStore = 1, mayLoad = 1, hasSideEffects = 0
6317 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
6318 X86VectorVTInfo DestInfo,
6319 PatFrag truncFrag, PatFrag mtruncFrag > {
6321 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
6322 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)
6323 addr:$dst, SrcInfo.RC:$src)>;
6325 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
6326 (SrcInfo.VT SrcInfo.RC:$src)),
6327 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)
6328 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
6331 multiclass avx512_trunc_sat_mr_lowering<X86VectorVTInfo SrcInfo,
6332 X86VectorVTInfo DestInfo, string sat > {
6334 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
6335 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
6336 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), SrcInfo.MRC:$mask),
6337 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk) addr:$ptr,
6338 (COPY_TO_REGCLASS SrcInfo.MRC:$mask, SrcInfo.KRCWM),
6339 (SrcInfo.VT SrcInfo.RC:$src))>;
6341 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
6342 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
6343 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), -1),
6344 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr) addr:$ptr,
6345 (SrcInfo.VT SrcInfo.RC:$src))>;
6348 multiclass avx512_trunc<bits<8> opc, string OpcodeStr, SDNode OpNode,
6349 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
6350 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
6351 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
6352 X86MemOperand x86memopZ, PatFrag truncFrag, PatFrag mtruncFrag,
6353 Predicate prd = HasAVX512>{
6355 let Predicates = [HasVLX, prd] in {
6356 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
6357 DestInfoZ128, x86memopZ128>,
6358 avx512_trunc_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
6359 truncFrag, mtruncFrag>, EVEX_V128;
6361 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
6362 DestInfoZ256, x86memopZ256>,
6363 avx512_trunc_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
6364 truncFrag, mtruncFrag>, EVEX_V256;
6366 let Predicates = [prd] in
6367 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
6368 DestInfoZ, x86memopZ>,
6369 avx512_trunc_mr_lowering<VTSrcInfo.info512, DestInfoZ,
6370 truncFrag, mtruncFrag>, EVEX_V512;
6373 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, SDNode OpNode,
6374 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
6375 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
6376 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
6377 X86MemOperand x86memopZ, string sat, Predicate prd = HasAVX512>{
6379 let Predicates = [HasVLX, prd] in {
6380 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
6381 DestInfoZ128, x86memopZ128>,
6382 avx512_trunc_sat_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
6385 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
6386 DestInfoZ256, x86memopZ256>,
6387 avx512_trunc_sat_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
6390 let Predicates = [prd] in
6391 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
6392 DestInfoZ, x86memopZ>,
6393 avx512_trunc_sat_mr_lowering<VTSrcInfo.info512, DestInfoZ,
6397 multiclass avx512_trunc_qb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6398 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6399 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
6400 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VO>;
6402 multiclass avx512_trunc_sat_qb<bits<8> opc, string sat, SDNode OpNode> {
6403 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qb", OpNode, avx512vl_i64_info,
6404 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
6405 sat>, EVEX_CD8<8, CD8VO>;
6408 multiclass avx512_trunc_qw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6409 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6410 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6411 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VQ>;
6413 multiclass avx512_trunc_sat_qw<bits<8> opc, string sat, SDNode OpNode> {
6414 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qw", OpNode, avx512vl_i64_info,
6415 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6416 sat>, EVEX_CD8<16, CD8VQ>;
6419 multiclass avx512_trunc_qd<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6420 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6421 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6422 truncstorevi32, masked_truncstorevi32>, EVEX_CD8<32, CD8VH>;
6424 multiclass avx512_trunc_sat_qd<bits<8> opc, string sat, SDNode OpNode> {
6425 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qd", OpNode, avx512vl_i64_info,
6426 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6427 sat>, EVEX_CD8<32, CD8VH>;
6430 multiclass avx512_trunc_db<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6431 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6432 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6433 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VQ>;
6435 multiclass avx512_trunc_sat_db<bits<8> opc, string sat, SDNode OpNode> {
6436 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"db", OpNode, avx512vl_i32_info,
6437 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6438 sat>, EVEX_CD8<8, CD8VQ>;
6441 multiclass avx512_trunc_dw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6442 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6443 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6444 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VH>;
6446 multiclass avx512_trunc_sat_dw<bits<8> opc, string sat, SDNode OpNode> {
6447 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"dw", OpNode, avx512vl_i32_info,
6448 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6449 sat>, EVEX_CD8<16, CD8VH>;
6452 multiclass avx512_trunc_wb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6453 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i16_info,
6454 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6455 truncstorevi8, masked_truncstorevi8,HasBWI>, EVEX_CD8<16, CD8VH>;
6457 multiclass avx512_trunc_sat_wb<bits<8> opc, string sat, SDNode OpNode> {
6458 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"wb", OpNode, avx512vl_i16_info,
6459 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6460 sat, HasBWI>, EVEX_CD8<16, CD8VH>;
6463 defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", X86vtrunc>;
6464 defm VPMOVSQB : avx512_trunc_sat_qb<0x22, "s", X86vtruncs>;
6465 defm VPMOVUSQB : avx512_trunc_sat_qb<0x12, "us", X86vtruncus>;
6467 defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", X86vtrunc>;
6468 defm VPMOVSQW : avx512_trunc_sat_qw<0x24, "s", X86vtruncs>;
6469 defm VPMOVUSQW : avx512_trunc_sat_qw<0x14, "us", X86vtruncus>;
6471 defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", X86vtrunc>;
6472 defm VPMOVSQD : avx512_trunc_sat_qd<0x25, "s", X86vtruncs>;
6473 defm VPMOVUSQD : avx512_trunc_sat_qd<0x15, "us", X86vtruncus>;
6475 defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", X86vtrunc>;
6476 defm VPMOVSDB : avx512_trunc_sat_db<0x21, "s", X86vtruncs>;
6477 defm VPMOVUSDB : avx512_trunc_sat_db<0x11, "us", X86vtruncus>;
6479 defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", X86vtrunc>;
6480 defm VPMOVSDW : avx512_trunc_sat_dw<0x23, "s", X86vtruncs>;
6481 defm VPMOVUSDW : avx512_trunc_sat_dw<0x13, "us", X86vtruncus>;
6483 defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", X86vtrunc>;
6484 defm VPMOVSWB : avx512_trunc_sat_wb<0x20, "s", X86vtruncs>;
6485 defm VPMOVUSWB : avx512_trunc_sat_wb<0x10, "us", X86vtruncus>;
6487 let Predicates = [HasAVX512, NoVLX] in {
6488 def: Pat<(v8i16 (X86vtrunc (v8i32 VR256X:$src))),
6489 (v8i16 (EXTRACT_SUBREG
6490 (v16i16 (VPMOVDWZrr (v16i32 (SUBREG_TO_REG (i32 0),
6491 VR256X:$src, sub_ymm)))), sub_xmm))>;
6492 def: Pat<(v4i32 (X86vtrunc (v4i64 VR256X:$src))),
6493 (v4i32 (EXTRACT_SUBREG
6494 (v8i32 (VPMOVQDZrr (v8i64 (SUBREG_TO_REG (i32 0),
6495 VR256X:$src, sub_ymm)))), sub_xmm))>;
6498 let Predicates = [HasBWI, NoVLX] in {
6499 def: Pat<(v16i8 (X86vtrunc (v16i16 VR256X:$src))),
6500 (v16i8 (EXTRACT_SUBREG (VPMOVWBZrr (v32i16 (SUBREG_TO_REG (i32 0),
6501 VR256X:$src, sub_ymm))), sub_xmm))>;
6504 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
6505 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
6506 X86MemOperand x86memop, PatFrag LdFrag, SDPatternOperator OpNode>{
6507 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6508 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
6509 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
6512 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6513 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
6514 (DestInfo.VT (LdFrag addr:$src))>,
6518 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr,
6519 SDPatternOperator OpNode,
6520 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6521 let Predicates = [HasVLX, HasBWI] in {
6522 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
6523 v16i8x_info, i64mem, LdFrag, OpNode>,
6524 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
6526 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
6527 v16i8x_info, i128mem, LdFrag, OpNode>,
6528 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
6530 let Predicates = [HasBWI] in {
6531 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
6532 v32i8x_info, i256mem, LdFrag, OpNode>,
6533 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
6537 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr,
6538 SDPatternOperator OpNode,
6539 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6540 let Predicates = [HasVLX, HasAVX512] in {
6541 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6542 v16i8x_info, i32mem, LdFrag, OpNode>,
6543 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
6545 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6546 v16i8x_info, i64mem, LdFrag, OpNode>,
6547 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
6549 let Predicates = [HasAVX512] in {
6550 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6551 v16i8x_info, i128mem, LdFrag, OpNode>,
6552 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
6556 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr,
6557 SDPatternOperator OpNode,
6558 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6559 let Predicates = [HasVLX, HasAVX512] in {
6560 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6561 v16i8x_info, i16mem, LdFrag, OpNode>,
6562 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
6564 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6565 v16i8x_info, i32mem, LdFrag, OpNode>,
6566 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
6568 let Predicates = [HasAVX512] in {
6569 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6570 v16i8x_info, i64mem, LdFrag, OpNode>,
6571 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
6575 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr,
6576 SDPatternOperator OpNode,
6577 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6578 let Predicates = [HasVLX, HasAVX512] in {
6579 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6580 v8i16x_info, i64mem, LdFrag, OpNode>,
6581 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
6583 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6584 v8i16x_info, i128mem, LdFrag, OpNode>,
6585 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
6587 let Predicates = [HasAVX512] in {
6588 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6589 v16i16x_info, i256mem, LdFrag, OpNode>,
6590 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
6594 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr,
6595 SDPatternOperator OpNode,
6596 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6597 let Predicates = [HasVLX, HasAVX512] in {
6598 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6599 v8i16x_info, i32mem, LdFrag, OpNode>,
6600 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
6602 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6603 v8i16x_info, i64mem, LdFrag, OpNode>,
6604 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
6606 let Predicates = [HasAVX512] in {
6607 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6608 v8i16x_info, i128mem, LdFrag, OpNode>,
6609 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
6613 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr,
6614 SDPatternOperator OpNode,
6615 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
6617 let Predicates = [HasVLX, HasAVX512] in {
6618 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6619 v4i32x_info, i64mem, LdFrag, OpNode>,
6620 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
6622 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6623 v4i32x_info, i128mem, LdFrag, OpNode>,
6624 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
6626 let Predicates = [HasAVX512] in {
6627 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6628 v8i32x_info, i256mem, LdFrag, OpNode>,
6629 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
6633 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
6634 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
6635 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
6636 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
6637 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
6638 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
6640 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
6641 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
6642 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
6643 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
6644 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
6645 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
6647 // EXTLOAD patterns, implemented using vpmovz
6648 multiclass avx512_ext_lowering<string InstrStr, X86VectorVTInfo To,
6649 X86VectorVTInfo From, PatFrag LdFrag> {
6650 def : Pat<(To.VT (LdFrag addr:$src)),
6651 (!cast<Instruction>("VPMOVZX"#InstrStr#"rm") addr:$src)>;
6652 def : Pat<(To.VT (vselect To.KRCWM:$mask, (LdFrag addr:$src), To.RC:$src0)),
6653 (!cast<Instruction>("VPMOVZX"#InstrStr#"rmk") To.RC:$src0,
6654 To.KRC:$mask, addr:$src)>;
6655 def : Pat<(To.VT (vselect To.KRCWM:$mask, (LdFrag addr:$src),
6657 (!cast<Instruction>("VPMOVZX"#InstrStr#"rmkz") To.KRC:$mask,
6661 let Predicates = [HasVLX, HasBWI] in {
6662 defm : avx512_ext_lowering<"BWZ128", v8i16x_info, v16i8x_info, extloadvi8>;
6663 defm : avx512_ext_lowering<"BWZ256", v16i16x_info, v16i8x_info, extloadvi8>;
6665 let Predicates = [HasBWI] in {
6666 defm : avx512_ext_lowering<"BWZ", v32i16_info, v32i8x_info, extloadvi8>;
6668 let Predicates = [HasVLX, HasAVX512] in {
6669 defm : avx512_ext_lowering<"BDZ128", v4i32x_info, v16i8x_info, extloadvi8>;
6670 defm : avx512_ext_lowering<"BDZ256", v8i32x_info, v16i8x_info, extloadvi8>;
6671 defm : avx512_ext_lowering<"BQZ128", v2i64x_info, v16i8x_info, extloadvi8>;
6672 defm : avx512_ext_lowering<"BQZ256", v4i64x_info, v16i8x_info, extloadvi8>;
6673 defm : avx512_ext_lowering<"WDZ128", v4i32x_info, v8i16x_info, extloadvi16>;
6674 defm : avx512_ext_lowering<"WDZ256", v8i32x_info, v8i16x_info, extloadvi16>;
6675 defm : avx512_ext_lowering<"WQZ128", v2i64x_info, v8i16x_info, extloadvi16>;
6676 defm : avx512_ext_lowering<"WQZ256", v4i64x_info, v8i16x_info, extloadvi16>;
6677 defm : avx512_ext_lowering<"DQZ128", v2i64x_info, v4i32x_info, extloadvi32>;
6678 defm : avx512_ext_lowering<"DQZ256", v4i64x_info, v4i32x_info, extloadvi32>;
6680 let Predicates = [HasAVX512] in {
6681 defm : avx512_ext_lowering<"BDZ", v16i32_info, v16i8x_info, extloadvi8>;
6682 defm : avx512_ext_lowering<"BQZ", v8i64_info, v16i8x_info, extloadvi8>;
6683 defm : avx512_ext_lowering<"WDZ", v16i32_info, v16i16x_info, extloadvi16>;
6684 defm : avx512_ext_lowering<"WQZ", v8i64_info, v8i16x_info, extloadvi16>;
6685 defm : avx512_ext_lowering<"DQZ", v8i64_info, v8i32x_info, extloadvi32>;
6688 //===----------------------------------------------------------------------===//
6689 // GATHER - SCATTER Operations
6691 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6692 X86MemOperand memop, PatFrag GatherNode> {
6693 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb",
6694 ExeDomain = _.ExeDomain in
6695 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
6696 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
6697 !strconcat(OpcodeStr#_.Suffix,
6698 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
6699 [(set _.RC:$dst, _.KRCWM:$mask_wb,
6700 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
6701 vectoraddr:$src2))]>, EVEX, EVEX_K,
6702 EVEX_CD8<_.EltSize, CD8VT1>;
6705 multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
6706 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6707 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512,
6708 vy512mem, mgatherv8i32>, EVEX_V512, VEX_W;
6709 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info512,
6710 vz512mem, mgatherv8i64>, EVEX_V512, VEX_W;
6711 let Predicates = [HasVLX] in {
6712 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6713 vx256xmem, mgatherv4i32>, EVEX_V256, VEX_W;
6714 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info256,
6715 vy256xmem, mgatherv4i64>, EVEX_V256, VEX_W;
6716 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6717 vx128xmem, mgatherv4i32>, EVEX_V128, VEX_W;
6718 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6719 vx128xmem, mgatherv2i64>, EVEX_V128, VEX_W;
6723 multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
6724 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6725 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512, vz512mem,
6726 mgatherv16i32>, EVEX_V512;
6727 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info256, vz512mem,
6728 mgatherv8i64>, EVEX_V512;
6729 let Predicates = [HasVLX] in {
6730 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6731 vy256xmem, mgatherv8i32>, EVEX_V256;
6732 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6733 vy128xmem, mgatherv4i64>, EVEX_V256;
6734 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6735 vx128xmem, mgatherv4i32>, EVEX_V128;
6736 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6737 vx64xmem, mgatherv2i64>, EVEX_V128;
6742 defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">,
6743 avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">;
6745 defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">,
6746 avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">;
6748 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6749 X86MemOperand memop, PatFrag ScatterNode> {
6751 let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in
6753 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
6754 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
6755 !strconcat(OpcodeStr#_.Suffix,
6756 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
6757 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
6758 _.KRCWM:$mask, vectoraddr:$dst))]>,
6759 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6762 multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
6763 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6764 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512,
6765 vy512mem, mscatterv8i32>, EVEX_V512, VEX_W;
6766 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info512,
6767 vz512mem, mscatterv8i64>, EVEX_V512, VEX_W;
6768 let Predicates = [HasVLX] in {
6769 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6770 vx256xmem, mscatterv4i32>, EVEX_V256, VEX_W;
6771 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info256,
6772 vy256xmem, mscatterv4i64>, EVEX_V256, VEX_W;
6773 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6774 vx128xmem, mscatterv4i32>, EVEX_V128, VEX_W;
6775 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6776 vx128xmem, mscatterv2i64>, EVEX_V128, VEX_W;
6780 multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
6781 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6782 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512, vz512mem,
6783 mscatterv16i32>, EVEX_V512;
6784 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info256, vz512mem,
6785 mscatterv8i64>, EVEX_V512;
6786 let Predicates = [HasVLX] in {
6787 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6788 vy256xmem, mscatterv8i32>, EVEX_V256;
6789 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6790 vy128xmem, mscatterv4i64>, EVEX_V256;
6791 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6792 vx128xmem, mscatterv4i32>, EVEX_V128;
6793 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6794 vx64xmem, mscatterv2i64>, EVEX_V128;
6798 defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">,
6799 avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">;
6801 defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">,
6802 avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">;
6805 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
6806 RegisterClass KRC, X86MemOperand memop> {
6807 let Predicates = [HasPFI], hasSideEffects = 1 in
6808 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
6809 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
6813 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
6814 VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6816 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
6817 VK8WM, vz512mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6819 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
6820 VK8WM, vy512mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6822 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
6823 VK8WM, vz512mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6825 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
6826 VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6828 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
6829 VK8WM, vz512mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6831 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
6832 VK8WM, vy512mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6834 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
6835 VK8WM, vz512mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6837 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
6838 VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6840 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
6841 VK8WM, vz512mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6843 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
6844 VK8WM, vy512mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6846 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
6847 VK8WM, vz512mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6849 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
6850 VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6852 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
6853 VK8WM, vz512mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6855 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
6856 VK8WM, vy512mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6858 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
6859 VK8WM, vz512mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6861 // Helper fragments to match sext vXi1 to vXiY.
6862 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
6863 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
6865 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
6866 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
6867 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
6868 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
6871 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
6872 string OpcodeStr, Predicate prd> {
6873 let Predicates = [prd] in
6874 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6876 let Predicates = [prd, HasVLX] in {
6877 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6878 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6882 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
6883 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
6885 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
6887 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
6889 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
6893 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
6895 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
6896 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
6897 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6898 [(set _.KRC:$dst, (X86cvt2mask (_.VT _.RC:$src)))]>, EVEX;
6901 // Use 512bit version to implement 128/256 bit in case NoVLX.
6902 multiclass convert_vector_to_mask_lowering<X86VectorVTInfo ExtendInfo,
6903 X86VectorVTInfo _> {
6905 def : Pat<(_.KVT (X86cvt2mask (_.VT _.RC:$src))),
6906 (_.KVT (COPY_TO_REGCLASS
6907 (!cast<Instruction>(NAME#"Zrr")
6908 (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)),
6909 _.RC:$src, _.SubRegIdx)),
6913 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
6914 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6915 let Predicates = [prd] in
6916 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
6919 let Predicates = [prd, HasVLX] in {
6920 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
6922 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
6925 let Predicates = [prd, NoVLX] in {
6926 defm Z256_Alt : convert_vector_to_mask_lowering<VTInfo.info512, VTInfo.info256>;
6927 defm Z128_Alt : convert_vector_to_mask_lowering<VTInfo.info512, VTInfo.info128>;
6931 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
6932 avx512vl_i8_info, HasBWI>;
6933 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
6934 avx512vl_i16_info, HasBWI>, VEX_W;
6935 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
6936 avx512vl_i32_info, HasDQI>;
6937 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
6938 avx512vl_i64_info, HasDQI>, VEX_W;
6940 //===----------------------------------------------------------------------===//
6941 // AVX-512 - COMPRESS and EXPAND
6944 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6946 defm rr : AVX512_maskable<opc, MRMDestReg, _, (outs _.RC:$dst),
6947 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6948 (_.VT (X86compress _.RC:$src1))>, AVX5128IBase;
6950 let mayStore = 1, hasSideEffects = 0 in
6951 def mr : AVX5128I<opc, MRMDestMem, (outs),
6952 (ins _.MemOp:$dst, _.RC:$src),
6953 OpcodeStr # "\t{$src, $dst|$dst, $src}",
6954 []>, EVEX_CD8<_.EltSize, CD8VT1>;
6956 def mrk : AVX5128I<opc, MRMDestMem, (outs),
6957 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
6958 OpcodeStr # "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
6959 [(store (_.VT (vselect _.KRCWM:$mask,
6960 (_.VT (X86compress _.RC:$src)), _.ImmAllZerosV)),
6962 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6965 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
6966 AVX512VLVectorVTInfo VTInfo> {
6967 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6969 let Predicates = [HasVLX] in {
6970 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6971 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6975 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
6977 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
6979 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
6981 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
6985 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6987 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6988 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6989 (_.VT (X86expand _.RC:$src1))>, AVX5128IBase;
6991 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6992 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
6993 (_.VT (X86expand (_.VT (bitconvert
6994 (_.LdFrag addr:$src1)))))>,
6995 AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>;
6998 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
6999 AVX512VLVectorVTInfo VTInfo> {
7000 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
7002 let Predicates = [HasVLX] in {
7003 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
7004 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
7008 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
7010 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
7012 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
7014 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
7017 //handle instruction reg_vec1 = op(reg_vec,imm)
7019 // op(broadcast(eltVt),imm)
7020 //all instruction created with FROUND_CURRENT
7021 multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7023 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7024 (ins _.RC:$src1, i32u8imm:$src2),
7025 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
7026 (OpNode (_.VT _.RC:$src1),
7028 (i32 FROUND_CURRENT))>;
7029 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7030 (ins _.MemOp:$src1, i32u8imm:$src2),
7031 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
7032 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
7034 (i32 FROUND_CURRENT))>;
7035 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7036 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
7037 OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
7038 "${src1}"##_.BroadcastStr##", $src2",
7039 (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
7041 (i32 FROUND_CURRENT))>, EVEX_B;
7044 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
7045 multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
7046 SDNode OpNode, X86VectorVTInfo _>{
7047 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7048 (ins _.RC:$src1, i32u8imm:$src2),
7049 OpcodeStr##_.Suffix, "$src2, {sae}, $src1",
7050 "$src1, {sae}, $src2",
7051 (OpNode (_.VT _.RC:$src1),
7053 (i32 FROUND_NO_EXC))>, EVEX_B;
7056 multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
7057 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
7058 let Predicates = [prd] in {
7059 defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
7060 avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
7063 let Predicates = [prd, HasVLX] in {
7064 defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
7066 defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
7071 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
7072 // op(reg_vec2,mem_vec,imm)
7073 // op(reg_vec2,broadcast(eltVt),imm)
7074 //all instruction created with FROUND_CURRENT
7075 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7077 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7078 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
7079 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
7080 (OpNode (_.VT _.RC:$src1),
7083 (i32 FROUND_CURRENT))>;
7084 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7085 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
7086 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
7087 (OpNode (_.VT _.RC:$src1),
7088 (_.VT (bitconvert (_.LdFrag addr:$src2))),
7090 (i32 FROUND_CURRENT))>;
7091 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7092 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
7093 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
7094 "$src1, ${src2}"##_.BroadcastStr##", $src3",
7095 (OpNode (_.VT _.RC:$src1),
7096 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
7098 (i32 FROUND_CURRENT))>, EVEX_B;
7101 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
7102 // op(reg_vec2,mem_vec,imm)
7103 multiclass avx512_3Op_rm_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
7104 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo>{
7106 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
7107 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
7108 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
7109 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
7110 (SrcInfo.VT SrcInfo.RC:$src2),
7112 defm rmi : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
7113 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
7114 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
7115 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
7116 (SrcInfo.VT (bitconvert
7117 (SrcInfo.LdFrag addr:$src2))),
7121 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
7122 // op(reg_vec2,mem_vec,imm)
7123 // op(reg_vec2,broadcast(eltVt),imm)
7124 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
7126 avx512_3Op_rm_imm8<opc, OpcodeStr, OpNode, _, _>{
7128 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7129 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
7130 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
7131 "$src1, ${src2}"##_.BroadcastStr##", $src3",
7132 (OpNode (_.VT _.RC:$src1),
7133 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
7134 (i8 imm:$src3))>, EVEX_B;
7137 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
7138 // op(reg_vec2,mem_scalar,imm)
7139 //all instruction created with FROUND_CURRENT
7140 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7141 X86VectorVTInfo _> {
7143 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
7144 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
7145 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
7146 (OpNode (_.VT _.RC:$src1),
7149 (i32 FROUND_CURRENT))>;
7150 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
7151 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
7152 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
7153 (OpNode (_.VT _.RC:$src1),
7154 (_.VT (scalar_to_vector
7155 (_.ScalarLdFrag addr:$src2))),
7157 (i32 FROUND_CURRENT))>;
7159 let isAsmParserOnly = 1, mayLoad = 1, hasSideEffects = 0 in {
7160 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
7161 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
7162 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
7167 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
7168 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
7169 SDNode OpNode, X86VectorVTInfo _>{
7170 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7171 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
7172 OpcodeStr, "$src3, {sae}, $src2, $src1",
7173 "$src1, $src2, {sae}, $src3",
7174 (OpNode (_.VT _.RC:$src1),
7177 (i32 FROUND_NO_EXC))>, EVEX_B;
7179 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
7180 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
7181 SDNode OpNode, X86VectorVTInfo _> {
7182 defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
7183 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
7184 OpcodeStr, "$src3, {sae}, $src2, $src1",
7185 "$src1, $src2, {sae}, $src3",
7186 (OpNode (_.VT _.RC:$src1),
7189 (i32 FROUND_NO_EXC))>, EVEX_B;
7192 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
7193 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
7194 let Predicates = [prd] in {
7195 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
7196 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
7200 let Predicates = [prd, HasVLX] in {
7201 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
7203 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
7208 multiclass avx512_common_3Op_rm_imm8<bits<8> opc, SDNode OpNode, string OpStr,
7209 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo>{
7210 let Predicates = [HasBWI] in {
7211 defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info512,
7212 SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX_4V;
7214 let Predicates = [HasBWI, HasVLX] in {
7215 defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info128,
7216 SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX_4V;
7217 defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info256,
7218 SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX_4V;
7222 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
7223 bits<8> opc, SDNode OpNode>{
7224 let Predicates = [HasAVX512] in {
7225 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
7227 let Predicates = [HasAVX512, HasVLX] in {
7228 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
7229 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
7233 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
7234 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
7235 let Predicates = [prd] in {
7236 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
7237 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
7241 multiclass avx512_common_unary_fp_sae_packed_imm_all<string OpcodeStr,
7242 bits<8> opcPs, bits<8> opcPd, SDNode OpNode, Predicate prd>{
7243 defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info,
7244 opcPs, OpNode, prd>, EVEX_CD8<32, CD8VF>;
7245 defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info,
7246 opcPd, OpNode, prd>, EVEX_CD8<64, CD8VF>, VEX_W;
7250 defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56,
7251 X86VReduce, HasDQI>, AVX512AIi8Base, EVEX;
7252 defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09,
7253 X86VRndScale, HasAVX512>, AVX512AIi8Base, EVEX;
7254 defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26,
7255 X86VGetMant, HasAVX512>, AVX512AIi8Base, EVEX;
7258 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
7259 0x50, X86VRange, HasDQI>,
7260 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
7261 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
7262 0x50, X86VRange, HasDQI>,
7263 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
7265 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
7266 0x51, X86VRange, HasDQI>,
7267 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
7268 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
7269 0x51, X86VRange, HasDQI>,
7270 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
7272 defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
7273 0x57, X86Reduces, HasDQI>,
7274 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
7275 defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
7276 0x57, X86Reduces, HasDQI>,
7277 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
7279 defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info,
7280 0x27, X86GetMants, HasAVX512>,
7281 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
7282 defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info,
7283 0x27, X86GetMants, HasAVX512>,
7284 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
7286 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
7287 bits<8> opc, SDNode OpNode = X86Shuf128>{
7288 let Predicates = [HasAVX512] in {
7289 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
7292 let Predicates = [HasAVX512, HasVLX] in {
7293 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
7296 let Predicates = [HasAVX512] in {
7297 def : Pat<(v16f32 (ffloor VR512:$src)),
7298 (VRNDSCALEPSZrri VR512:$src, (i32 0x1))>;
7299 def : Pat<(v16f32 (fnearbyint VR512:$src)),
7300 (VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;
7301 def : Pat<(v16f32 (fceil VR512:$src)),
7302 (VRNDSCALEPSZrri VR512:$src, (i32 0x2))>;
7303 def : Pat<(v16f32 (frint VR512:$src)),
7304 (VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;
7305 def : Pat<(v16f32 (ftrunc VR512:$src)),
7306 (VRNDSCALEPSZrri VR512:$src, (i32 0x3))>;
7308 def : Pat<(v8f64 (ffloor VR512:$src)),
7309 (VRNDSCALEPDZrri VR512:$src, (i32 0x1))>;
7310 def : Pat<(v8f64 (fnearbyint VR512:$src)),
7311 (VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;
7312 def : Pat<(v8f64 (fceil VR512:$src)),
7313 (VRNDSCALEPDZrri VR512:$src, (i32 0x2))>;
7314 def : Pat<(v8f64 (frint VR512:$src)),
7315 (VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;
7316 def : Pat<(v8f64 (ftrunc VR512:$src)),
7317 (VRNDSCALEPDZrri VR512:$src, (i32 0x3))>;
7320 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
7321 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
7322 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
7323 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
7324 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
7325 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
7326 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
7327 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
7329 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I> {
7330 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
7331 AVX512AIi8Base, EVEX_4V;
7334 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info>,
7335 EVEX_CD8<32, CD8VF>;
7336 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info>,
7337 EVEX_CD8<64, CD8VF>, VEX_W;
7339 multiclass avx512_vpalignr_lowering<X86VectorVTInfo _ , list<Predicate> p>{
7340 let Predicates = p in
7341 def NAME#_.VTName#rri:
7342 Pat<(_.VT (X86PAlignr _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
7343 (!cast<Instruction>(NAME#_.ZSuffix#rri)
7344 _.RC:$src1, _.RC:$src2, imm:$imm)>;
7347 multiclass avx512_vpalignr_lowering_common<AVX512VLVectorVTInfo _>:
7348 avx512_vpalignr_lowering<_.info512, [HasBWI]>,
7349 avx512_vpalignr_lowering<_.info128, [HasBWI, HasVLX]>,
7350 avx512_vpalignr_lowering<_.info256, [HasBWI, HasVLX]>;
7352 defm VPALIGNR: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" ,
7353 avx512vl_i8_info, avx512vl_i8_info>,
7354 avx512_vpalignr_lowering_common<avx512vl_i16_info>,
7355 avx512_vpalignr_lowering_common<avx512vl_i32_info>,
7356 avx512_vpalignr_lowering_common<avx512vl_f32_info>,
7357 avx512_vpalignr_lowering_common<avx512vl_i64_info>,
7358 avx512_vpalignr_lowering_common<avx512vl_f64_info>,
7361 defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" ,
7362 avx512vl_i16_info, avx512vl_i8_info>, EVEX_CD8<8, CD8VF>;
7364 multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7365 X86VectorVTInfo _> {
7366 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7367 (ins _.RC:$src1), OpcodeStr,
7369 (_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
7371 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7372 (ins _.MemOp:$src1), OpcodeStr,
7374 (_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
7375 EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
7378 multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
7379 X86VectorVTInfo _> :
7380 avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
7381 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7382 (ins _.ScalarMemOp:$src1), OpcodeStr,
7383 "${src1}"##_.BroadcastStr,
7384 "${src1}"##_.BroadcastStr,
7385 (_.VT (OpNode (X86VBroadcast
7386 (_.ScalarLdFrag addr:$src1))))>,
7387 EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
7390 multiclass avx512_unary_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
7391 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
7392 let Predicates = [prd] in
7393 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
7395 let Predicates = [prd, HasVLX] in {
7396 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
7398 defm Z128 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info128>,
7403 multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
7404 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
7405 let Predicates = [prd] in
7406 defm Z : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
7409 let Predicates = [prd, HasVLX] in {
7410 defm Z256 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
7412 defm Z128 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
7417 multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
7418 SDNode OpNode, Predicate prd> {
7419 defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr#"q", OpNode, avx512vl_i64_info,
7421 defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr#"d", OpNode, avx512vl_i32_info,
7425 multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
7426 SDNode OpNode, Predicate prd> {
7427 defm W : avx512_unary_rm_vl<opc_w, OpcodeStr#"w", OpNode, avx512vl_i16_info, prd>;
7428 defm B : avx512_unary_rm_vl<opc_b, OpcodeStr#"b", OpNode, avx512vl_i8_info, prd>;
7431 multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
7432 bits<8> opc_d, bits<8> opc_q,
7433 string OpcodeStr, SDNode OpNode> {
7434 defm NAME : avx512_unary_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
7436 avx512_unary_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
7440 defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
7443 (bc_v16i32 (v16i1sextv16i32)),
7444 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
7445 (VPABSDZrr VR512:$src)>;
7447 (bc_v8i64 (v8i1sextv8i64)),
7448 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
7449 (VPABSQZrr VR512:$src)>;
7451 multiclass avx512_ctlz<bits<8> opc, string OpcodeStr, Predicate prd>{
7453 defm NAME : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr, ctlz, prd>;
7456 defm VPLZCNT : avx512_ctlz<0x44, "vplzcnt", HasCDI>;
7457 defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, HasCDI>;
7459 //===---------------------------------------------------------------------===//
7460 // Replicate Single FP - MOVSHDUP and MOVSLDUP
7461 //===---------------------------------------------------------------------===//
7462 multiclass avx512_replicate<bits<8> opc, string OpcodeStr, SDNode OpNode>{
7463 defm NAME: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_f32_info,
7467 defm VMOVSHDUP : avx512_replicate<0x16, "vmovshdup", X86Movshdup>;
7468 defm VMOVSLDUP : avx512_replicate<0x12, "vmovsldup", X86Movsldup>;
7470 //===----------------------------------------------------------------------===//
7471 // AVX-512 - MOVDDUP
7472 //===----------------------------------------------------------------------===//
7474 multiclass avx512_movddup_128<bits<8> opc, string OpcodeStr, SDNode OpNode,
7475 X86VectorVTInfo _> {
7476 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7477 (ins _.RC:$src), OpcodeStr, "$src", "$src",
7478 (_.VT (OpNode (_.VT _.RC:$src)))>, EVEX;
7479 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7480 (ins _.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
7481 (_.VT (OpNode (_.VT (scalar_to_vector
7482 (_.ScalarLdFrag addr:$src)))))>,
7483 EVEX, EVEX_CD8<_.EltSize, CD8VH>;
7486 multiclass avx512_movddup_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
7487 AVX512VLVectorVTInfo VTInfo> {
7489 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
7491 let Predicates = [HasAVX512, HasVLX] in {
7492 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
7494 defm Z128 : avx512_movddup_128<opc, OpcodeStr, OpNode, VTInfo.info128>,
7499 multiclass avx512_movddup<bits<8> opc, string OpcodeStr, SDNode OpNode>{
7500 defm NAME: avx512_movddup_common<opc, OpcodeStr, OpNode,
7501 avx512vl_f64_info>, XD, VEX_W;
7504 defm VMOVDDUP : avx512_movddup<0x12, "vmovddup", X86Movddup>;
7506 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
7507 (VMOVDDUPZ128rm addr:$src)>, Requires<[HasAVX512, HasVLX]>;
7508 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
7509 (VMOVDDUPZ128rm addr:$src)>, Requires<[HasAVX512, HasVLX]>;
7511 //===----------------------------------------------------------------------===//
7512 // AVX-512 - Unpack Instructions
7513 //===----------------------------------------------------------------------===//
7514 defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh, HasAVX512>;
7515 defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl, HasAVX512>;
7517 defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl,
7518 SSE_INTALU_ITINS_P, HasBWI>;
7519 defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh,
7520 SSE_INTALU_ITINS_P, HasBWI>;
7521 defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl,
7522 SSE_INTALU_ITINS_P, HasBWI>;
7523 defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh,
7524 SSE_INTALU_ITINS_P, HasBWI>;
7526 defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl,
7527 SSE_INTALU_ITINS_P, HasAVX512>;
7528 defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh,
7529 SSE_INTALU_ITINS_P, HasAVX512>;
7530 defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl,
7531 SSE_INTALU_ITINS_P, HasAVX512>;
7532 defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh,
7533 SSE_INTALU_ITINS_P, HasAVX512>;
7535 //===----------------------------------------------------------------------===//
7536 // AVX-512 - Extract & Insert Integer Instructions
7537 //===----------------------------------------------------------------------===//
7539 multiclass avx512_extract_elt_bw_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7540 X86VectorVTInfo _> {
7541 def mr : AVX512Ii8<opc, MRMDestMem, (outs),
7542 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7543 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7544 [(store (_.EltVT (trunc (assertzext (OpNode (_.VT _.RC:$src1),
7547 EVEX, EVEX_CD8<_.EltSize, CD8VT1>;
7550 multiclass avx512_extract_elt_b<string OpcodeStr, X86VectorVTInfo _> {
7551 let Predicates = [HasBWI] in {
7552 def rr : AVX512Ii8<0x14, MRMDestReg, (outs GR32orGR64:$dst),
7553 (ins _.RC:$src1, u8imm:$src2),
7554 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7555 [(set GR32orGR64:$dst,
7556 (X86pextrb (_.VT _.RC:$src1), imm:$src2))]>,
7559 defm NAME : avx512_extract_elt_bw_m<0x14, OpcodeStr, X86pextrb, _>, TAPD;
7563 multiclass avx512_extract_elt_w<string OpcodeStr, X86VectorVTInfo _> {
7564 let Predicates = [HasBWI] in {
7565 def rr : AVX512Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst),
7566 (ins _.RC:$src1, u8imm:$src2),
7567 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7568 [(set GR32orGR64:$dst,
7569 (X86pextrw (_.VT _.RC:$src1), imm:$src2))]>,
7572 let hasSideEffects = 0 in
7573 def rr_REV : AVX512Ii8<0x15, MRMDestReg, (outs GR32orGR64:$dst),
7574 (ins _.RC:$src1, u8imm:$src2),
7575 OpcodeStr#".s\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7578 defm NAME : avx512_extract_elt_bw_m<0x15, OpcodeStr, X86pextrw, _>, TAPD;
7582 multiclass avx512_extract_elt_dq<string OpcodeStr, X86VectorVTInfo _,
7583 RegisterClass GRC> {
7584 let Predicates = [HasDQI] in {
7585 def rr : AVX512Ii8<0x16, MRMDestReg, (outs GRC:$dst),
7586 (ins _.RC:$src1, u8imm:$src2),
7587 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7589 (extractelt (_.VT _.RC:$src1), imm:$src2))]>,
7592 def mr : AVX512Ii8<0x16, MRMDestMem, (outs),
7593 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7594 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7595 [(store (extractelt (_.VT _.RC:$src1),
7596 imm:$src2),addr:$dst)]>,
7597 EVEX, EVEX_CD8<_.EltSize, CD8VT1>, TAPD;
7601 defm VPEXTRBZ : avx512_extract_elt_b<"vpextrb", v16i8x_info>;
7602 defm VPEXTRWZ : avx512_extract_elt_w<"vpextrw", v8i16x_info>;
7603 defm VPEXTRDZ : avx512_extract_elt_dq<"vpextrd", v4i32x_info, GR32>;
7604 defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, VEX_W;
7606 multiclass avx512_insert_elt_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7607 X86VectorVTInfo _, PatFrag LdFrag> {
7608 def rm : AVX512Ii8<opc, MRMSrcMem, (outs _.RC:$dst),
7609 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
7610 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7612 (_.VT (OpNode _.RC:$src1, (LdFrag addr:$src2), imm:$src3)))]>,
7613 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
7616 multiclass avx512_insert_elt_bw<bits<8> opc, string OpcodeStr, SDNode OpNode,
7617 X86VectorVTInfo _, PatFrag LdFrag> {
7618 let Predicates = [HasBWI] in {
7619 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7620 (ins _.RC:$src1, GR32orGR64:$src2, u8imm:$src3),
7621 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7623 (OpNode _.RC:$src1, GR32orGR64:$src2, imm:$src3))]>, EVEX_4V;
7625 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, OpNode, _, LdFrag>;
7629 multiclass avx512_insert_elt_dq<bits<8> opc, string OpcodeStr,
7630 X86VectorVTInfo _, RegisterClass GRC> {
7631 let Predicates = [HasDQI] in {
7632 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7633 (ins _.RC:$src1, GRC:$src2, u8imm:$src3),
7634 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7636 (_.VT (insertelt _.RC:$src1, GRC:$src2, imm:$src3)))]>,
7639 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, insertelt, _,
7640 _.ScalarLdFrag>, TAPD;
7644 defm VPINSRBZ : avx512_insert_elt_bw<0x20, "vpinsrb", X86pinsrb, v16i8x_info,
7646 defm VPINSRWZ : avx512_insert_elt_bw<0xC4, "vpinsrw", X86pinsrw, v8i16x_info,
7648 defm VPINSRDZ : avx512_insert_elt_dq<0x22, "vpinsrd", v4i32x_info, GR32>;
7649 defm VPINSRQZ : avx512_insert_elt_dq<0x22, "vpinsrq", v2i64x_info, GR64>, VEX_W;
7650 //===----------------------------------------------------------------------===//
7651 // VSHUFPS - VSHUFPD Operations
7652 //===----------------------------------------------------------------------===//
7653 multiclass avx512_shufp<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
7654 AVX512VLVectorVTInfo VTInfo_FP>{
7655 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0xC6, X86Shufp>,
7656 EVEX_CD8<VTInfo_FP.info512.EltSize, CD8VF>,
7657 AVX512AIi8Base, EVEX_4V;
7660 defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_i32_info, avx512vl_f32_info>, PS;
7661 defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD, VEX_W;
7662 //===----------------------------------------------------------------------===//
7663 // AVX-512 - Byte shift Left/Right
7664 //===----------------------------------------------------------------------===//
7666 multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
7667 Format MRMm, string OpcodeStr, X86VectorVTInfo _>{
7668 def rr : AVX512<opc, MRMr,
7669 (outs _.RC:$dst), (ins _.RC:$src1, u8imm:$src2),
7670 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7671 [(set _.RC:$dst,(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>;
7672 def rm : AVX512<opc, MRMm,
7673 (outs _.RC:$dst), (ins _.MemOp:$src1, u8imm:$src2),
7674 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7675 [(set _.RC:$dst,(_.VT (OpNode
7676 (_.VT (bitconvert (_.LdFrag addr:$src1))),
7677 (i8 imm:$src2))))]>;
7680 multiclass avx512_shift_packed_all<bits<8> opc, SDNode OpNode, Format MRMr,
7681 Format MRMm, string OpcodeStr, Predicate prd>{
7682 let Predicates = [prd] in
7683 defm Z512 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7684 OpcodeStr, v64i8_info>, EVEX_V512;
7685 let Predicates = [prd, HasVLX] in {
7686 defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7687 OpcodeStr, v32i8x_info>, EVEX_V256;
7688 defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7689 OpcodeStr, v16i8x_info>, EVEX_V128;
7692 defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq",
7693 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7694 defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq",
7695 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7698 multiclass avx512_psadbw_packed<bits<8> opc, SDNode OpNode,
7699 string OpcodeStr, X86VectorVTInfo _dst,
7700 X86VectorVTInfo _src>{
7701 def rr : AVX512BI<opc, MRMSrcReg,
7702 (outs _dst.RC:$dst), (ins _src.RC:$src1, _src.RC:$src2),
7703 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7704 [(set _dst.RC:$dst,(_dst.VT
7705 (OpNode (_src.VT _src.RC:$src1),
7706 (_src.VT _src.RC:$src2))))]>;
7707 def rm : AVX512BI<opc, MRMSrcMem,
7708 (outs _dst.RC:$dst), (ins _src.RC:$src1, _src.MemOp:$src2),
7709 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7710 [(set _dst.RC:$dst,(_dst.VT
7711 (OpNode (_src.VT _src.RC:$src1),
7712 (_src.VT (bitconvert
7713 (_src.LdFrag addr:$src2))))))]>;
7716 multiclass avx512_psadbw_packed_all<bits<8> opc, SDNode OpNode,
7717 string OpcodeStr, Predicate prd> {
7718 let Predicates = [prd] in
7719 defm Z512 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v8i64_info,
7720 v64i8_info>, EVEX_V512;
7721 let Predicates = [prd, HasVLX] in {
7722 defm Z256 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v4i64x_info,
7723 v32i8x_info>, EVEX_V256;
7724 defm Z128 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v2i64x_info,
7725 v16i8x_info>, EVEX_V128;
7729 defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw",
7732 multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
7734 let Constraints = "$src1 = $dst" in {
7735 defm rri : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
7736 (ins _.RC:$src2, _.RC:$src3, u8imm:$src4),
7737 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src4",
7738 (OpNode (_.VT _.RC:$src1),
7741 (i8 imm:$src4))>, AVX512AIi8Base, EVEX_4V;
7742 defm rmi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7743 (ins _.RC:$src2, _.MemOp:$src3, u8imm:$src4),
7744 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src4",
7745 (OpNode (_.VT _.RC:$src1),
7747 (_.VT (bitconvert (_.LdFrag addr:$src3))),
7749 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7750 defm rmbi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7751 (ins _.RC:$src2, _.ScalarMemOp:$src3, u8imm:$src4),
7752 OpcodeStr, "$src4, ${src3}"##_.BroadcastStr##", $src2",
7753 "$src2, ${src3}"##_.BroadcastStr##", $src4",
7754 (OpNode (_.VT _.RC:$src1),
7756 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
7757 (i8 imm:$src4))>, EVEX_B,
7758 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7759 }// Constraints = "$src1 = $dst"
7762 multiclass avx512_common_ternlog<string OpcodeStr, AVX512VLVectorVTInfo _>{
7763 let Predicates = [HasAVX512] in
7764 defm Z : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info512>, EVEX_V512;
7765 let Predicates = [HasAVX512, HasVLX] in {
7766 defm Z128 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info128>, EVEX_V128;
7767 defm Z256 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info256>, EVEX_V256;
7771 defm VPTERNLOGD : avx512_common_ternlog<"vpternlogd", avx512vl_i32_info>;
7772 defm VPTERNLOGQ : avx512_common_ternlog<"vpternlogq", avx512vl_i64_info>, VEX_W;
7774 //===----------------------------------------------------------------------===//
7775 // AVX-512 - FixupImm
7776 //===----------------------------------------------------------------------===//
7778 multiclass avx512_fixupimm_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
7780 let Constraints = "$src1 = $dst" in {
7781 defm rri : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
7782 (ins _.RC:$src2, _.RC:$src3, i32u8imm:$src4),
7783 OpcodeStr##_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
7784 (OpNode (_.VT _.RC:$src1),
7786 (_.IntVT _.RC:$src3),
7788 (i32 FROUND_CURRENT))>;
7789 defm rmi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7790 (ins _.RC:$src2, _.MemOp:$src3, i32u8imm:$src4),
7791 OpcodeStr##_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
7792 (OpNode (_.VT _.RC:$src1),
7794 (_.IntVT (bitconvert (_.LdFrag addr:$src3))),
7796 (i32 FROUND_CURRENT))>;
7797 defm rmbi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7798 (ins _.RC:$src2, _.ScalarMemOp:$src3, i32u8imm:$src4),
7799 OpcodeStr##_.Suffix, "$src4, ${src3}"##_.BroadcastStr##", $src2",
7800 "$src2, ${src3}"##_.BroadcastStr##", $src4",
7801 (OpNode (_.VT _.RC:$src1),
7803 (_.IntVT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
7805 (i32 FROUND_CURRENT))>, EVEX_B;
7806 } // Constraints = "$src1 = $dst"
7809 multiclass avx512_fixupimm_packed_sae<bits<8> opc, string OpcodeStr,
7810 SDNode OpNode, X86VectorVTInfo _>{
7811 let Constraints = "$src1 = $dst" in {
7812 defm rrib : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
7813 (ins _.RC:$src2, _.RC:$src3, i32u8imm:$src4),
7814 OpcodeStr##_.Suffix, "$src4, {sae}, $src3, $src2",
7815 "$src2, $src3, {sae}, $src4",
7816 (OpNode (_.VT _.RC:$src1),
7818 (_.IntVT _.RC:$src3),
7820 (i32 FROUND_NO_EXC))>, EVEX_B;
7824 multiclass avx512_fixupimm_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
7825 X86VectorVTInfo _, X86VectorVTInfo _src3VT> {
7826 let Constraints = "$src1 = $dst" , Predicates = [HasAVX512] in {
7827 defm rri : AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
7828 (ins _.RC:$src2, _.RC:$src3, i32u8imm:$src4),
7829 OpcodeStr##_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
7830 (OpNode (_.VT _.RC:$src1),
7832 (_src3VT.VT _src3VT.RC:$src3),
7834 (i32 FROUND_CURRENT))>;
7836 defm rrib : AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
7837 (ins _.RC:$src2, _.RC:$src3, i32u8imm:$src4),
7838 OpcodeStr##_.Suffix, "$src4, {sae}, $src3, $src2",
7839 "$src2, $src3, {sae}, $src4",
7840 (OpNode (_.VT _.RC:$src1),
7842 (_src3VT.VT _src3VT.RC:$src3),
7844 (i32 FROUND_NO_EXC))>, EVEX_B;
7845 defm rmi : AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
7846 (ins _.RC:$src2, _.ScalarMemOp:$src3, i32u8imm:$src4),
7847 OpcodeStr##_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
7848 (OpNode (_.VT _.RC:$src1),
7850 (_src3VT.VT (scalar_to_vector
7851 (_src3VT.ScalarLdFrag addr:$src3))),
7853 (i32 FROUND_CURRENT))>;
7857 multiclass avx512_fixupimm_packed_all<AVX512VLVectorVTInfo _Vec>{
7858 let Predicates = [HasAVX512] in
7859 defm Z : avx512_fixupimm_packed<0x54, "vfixupimm", X86VFixupimm, _Vec.info512>,
7860 avx512_fixupimm_packed_sae<0x54, "vfixupimm", X86VFixupimm, _Vec.info512>,
7861 AVX512AIi8Base, EVEX_4V, EVEX_V512;
7862 let Predicates = [HasAVX512, HasVLX] in {
7863 defm Z128 : avx512_fixupimm_packed<0x54, "vfixupimm", X86VFixupimm, _Vec.info128>,
7864 AVX512AIi8Base, EVEX_4V, EVEX_V128;
7865 defm Z256 : avx512_fixupimm_packed<0x54, "vfixupimm", X86VFixupimm, _Vec.info256>,
7866 AVX512AIi8Base, EVEX_4V, EVEX_V256;
7870 defm VFIXUPIMMSS : avx512_fixupimm_scalar<0x55, "vfixupimm", X86VFixupimmScalar,
7871 f32x_info, v4i32x_info>,
7872 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
7873 defm VFIXUPIMMSD : avx512_fixupimm_scalar<0x55, "vfixupimm", X86VFixupimmScalar,
7874 f64x_info, v2i64x_info>,
7875 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
7876 defm VFIXUPIMMPS : avx512_fixupimm_packed_all<avx512vl_f32_info>,
7877 EVEX_CD8<32, CD8VF>;
7878 defm VFIXUPIMMPD : avx512_fixupimm_packed_all<avx512vl_f64_info>,
7879 EVEX_CD8<64, CD8VF>, VEX_W;