1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue());
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue());
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
48 [(X86callseq_start timm:$amt)]>,
49 Requires<[In32BitMode]>;
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
53 Requires<[In32BitMode]>;
56 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
57 // a stack adjustment and the codegen must know that they may modify the stack
58 // pointer before prolog-epilog rewriting occurs.
59 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
60 // sub / add which can clobber EFLAGS.
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
64 [(X86callseq_start timm:$amt)]>,
65 Requires<[In64BitMode]>;
66 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
68 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
69 Requires<[In64BitMode]>;
74 // x86-64 va_start lowering magic.
75 let usesCustomInserter = 1, Defs = [EFLAGS] in {
76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
79 i64imm:$regsavefi, i64imm:$offset,
81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
82 [(X86vastart_save_xmm_regs GR8:$al,
87 // The VAARG_64 pseudo-instruction takes the address of the va_list,
88 // and places the address of the next argument into a register.
89 let Defs = [EFLAGS] in
90 def VAARG_64 : I<0, Pseudo,
92 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
93 "#VAARG_64 $dst, $ap, $size, $mode, $align",
95 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
98 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
99 // targets. These calls are needed to probe the stack when allocating more than
100 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
101 // ensure that the guard pages used by the OS virtual memory manager are
102 // allocated in correct sequence.
103 // The main point of having separate instruction are extra unmodelled effects
104 // (compared to ordinary calls) like stack pointer change.
106 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
107 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
108 "# dynamic stack allocation",
111 // When using segmented stacks these are lowered into instructions which first
112 // check if the current stacklet has enough free memory. If it does, memory is
113 // allocated by bumping the stack pointer. Otherwise memory is allocated from
116 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
117 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
118 "# variable sized alloca for segmented stacks",
120 (X86SegAlloca GR32:$size))]>,
121 Requires<[In32BitMode]>;
123 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
124 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
125 "# variable sized alloca for segmented stacks",
127 (X86SegAlloca GR64:$size))]>,
128 Requires<[In64BitMode]>;
131 // The MSVC runtime contains an _ftol2 routine for converting floating-point
132 // to integer values. It has a strange calling convention: the input is
133 // popped from the x87 stack, and the return value is given in EDX:EAX. ECX is
134 // used as a temporary register. No other registers (aside from flags) are
136 // Microsoft toolchains do not support 80-bit precision, so a WIN_FTOL_80
137 // variant is unnecessary.
139 let Defs = [EAX, EDX, ECX, EFLAGS], FPForm = SpecialFP in {
140 def WIN_FTOL_32 : I<0, Pseudo, (outs), (ins RFP32:$src),
142 [(X86WinFTOL RFP32:$src)]>,
143 Requires<[In32BitMode]>;
145 def WIN_FTOL_64 : I<0, Pseudo, (outs), (ins RFP64:$src),
147 [(X86WinFTOL RFP64:$src)]>,
148 Requires<[In32BitMode]>;
151 //===----------------------------------------------------------------------===//
152 // EH Pseudo Instructions
154 let SchedRW = [WriteSystem] in {
155 let isTerminator = 1, isReturn = 1, isBarrier = 1,
156 hasCtrlDep = 1, isCodeGenOnly = 1 in {
157 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
158 "ret\t#eh_return, addr: $addr",
159 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
163 let isTerminator = 1, isReturn = 1, isBarrier = 1,
164 hasCtrlDep = 1, isCodeGenOnly = 1 in {
165 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
166 "ret\t#eh_return, addr: $addr",
167 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
171 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
172 usesCustomInserter = 1 in {
173 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
175 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
176 Requires<[In32BitMode]>;
177 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
179 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
180 Requires<[In64BitMode]>;
181 let isTerminator = 1 in {
182 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
183 "#EH_SJLJ_LONGJMP32",
184 [(X86eh_sjlj_longjmp addr:$buf)]>,
185 Requires<[In32BitMode]>;
186 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
187 "#EH_SJLJ_LONGJMP64",
188 [(X86eh_sjlj_longjmp addr:$buf)]>,
189 Requires<[In64BitMode]>;
194 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
195 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
196 "#EH_SjLj_Setup\t$dst", []>;
199 //===----------------------------------------------------------------------===//
200 // Pseudo instructions used by segmented stacks.
203 // This is lowered into a RET instruction by MCInstLower. We need
204 // this so that we don't have to have a MachineBasicBlock which ends
205 // with a RET and also has successors.
206 let isPseudo = 1 in {
207 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
210 // This instruction is lowered to a RET followed by a MOV. The two
211 // instructions are not generated on a higher level since then the
212 // verifier sees a MachineBasicBlock ending with a non-terminator.
213 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
217 //===----------------------------------------------------------------------===//
218 // Alias Instructions
219 //===----------------------------------------------------------------------===//
221 // Alias instruction mapping movr0 to xor.
222 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
223 // FIXME: Set encoding to pseudo.
224 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
226 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
227 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
229 // Other widths can also make use of the 32-bit xor, which may have a smaller
230 // encoding and avoid partial register updates.
231 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
232 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
233 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
234 let AddedComplexity = 20;
237 // Materialize i64 constant where top 32-bits are zero. This could theoretically
238 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
239 // that would make it more difficult to rematerialize.
240 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
241 isCodeGenOnly = 1, neverHasSideEffects = 1 in
242 def MOV32ri64 : Ii32<0xb8, AddRegFrm, (outs GR32:$dst), (ins i64i32imm:$src),
243 "", [], IIC_ALU_NONMEM>, Sched<[WriteALU]>;
245 // This 64-bit pseudo-move can be used for both a 64-bit constant that is
246 // actually the zero-extension of a 32-bit constant, and for labels in the
247 // x86-64 small code model.
248 def mov64imm32 : ComplexPattern<i64, 1, "SelectMOV64Imm32", [imm, X86Wrapper]>;
250 let AddedComplexity = 1 in
251 def : Pat<(i64 mov64imm32:$src),
252 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
254 // Use sbb to materialize carry bit.
255 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
256 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
257 // However, Pat<> can't replicate the destination reg into the inputs of the
259 def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "",
260 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
261 def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "",
262 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
263 def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "",
264 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
265 def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "",
266 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
270 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
272 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
274 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
277 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
279 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
281 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
284 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
285 // will be eliminated and that the sbb can be extended up to a wider type. When
286 // this happens, it is great. However, if we are left with an 8-bit sbb and an
287 // and, we might as well just match it as a setb.
288 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
291 // (add OP, SETB) -> (adc OP, 0)
292 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
293 (ADC8ri GR8:$op, 0)>;
294 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
295 (ADC32ri8 GR32:$op, 0)>;
296 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
297 (ADC64ri8 GR64:$op, 0)>;
299 // (sub OP, SETB) -> (sbb OP, 0)
300 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
301 (SBB8ri GR8:$op, 0)>;
302 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
303 (SBB32ri8 GR32:$op, 0)>;
304 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
305 (SBB64ri8 GR64:$op, 0)>;
307 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
308 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
309 (ADC8ri GR8:$op, 0)>;
310 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
311 (ADC32ri8 GR32:$op, 0)>;
312 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
313 (ADC64ri8 GR64:$op, 0)>;
315 //===----------------------------------------------------------------------===//
316 // String Pseudo Instructions
318 let SchedRW = [WriteMicrocoded] in {
319 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
320 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
321 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
322 Requires<[In32BitMode]>;
323 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
324 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
325 Requires<[In32BitMode]>;
326 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
327 [(X86rep_movs i32)], IIC_REP_MOVS>, REP,
328 Requires<[In32BitMode]>;
331 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
332 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
333 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
334 Requires<[In64BitMode]>;
335 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
336 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
337 Requires<[In64BitMode]>;
338 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
339 [(X86rep_movs i32)], IIC_REP_MOVS>, REP,
340 Requires<[In64BitMode]>;
341 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
342 [(X86rep_movs i64)], IIC_REP_MOVS>, REP,
343 Requires<[In64BitMode]>;
346 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
347 let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
348 let Uses = [AL,ECX,EDI] in
349 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
350 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
351 Requires<[In32BitMode]>;
352 let Uses = [AX,ECX,EDI] in
353 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
354 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
355 Requires<[In32BitMode]>;
356 let Uses = [EAX,ECX,EDI] in
357 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
358 [(X86rep_stos i32)], IIC_REP_STOS>, REP,
359 Requires<[In32BitMode]>;
362 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
363 let Uses = [AL,RCX,RDI] in
364 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
365 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
366 Requires<[In64BitMode]>;
367 let Uses = [AX,RCX,RDI] in
368 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
369 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
370 Requires<[In64BitMode]>;
371 let Uses = [RAX,RCX,RDI] in
372 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
373 [(X86rep_stos i32)], IIC_REP_STOS>, REP,
374 Requires<[In64BitMode]>;
376 let Uses = [RAX,RCX,RDI] in
377 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
378 [(X86rep_stos i64)], IIC_REP_STOS>, REP,
379 Requires<[In64BitMode]>;
383 //===----------------------------------------------------------------------===//
384 // Thread Local Storage Instructions
388 // All calls clobber the non-callee saved registers. ESP is marked as
389 // a use to prevent stack-pointer assignments that appear immediately
390 // before calls from potentially appearing dead.
391 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
392 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
393 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
394 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
396 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
398 [(X86tlsaddr tls32addr:$sym)]>,
399 Requires<[In32BitMode]>;
400 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
402 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
403 Requires<[In32BitMode]>;
406 // All calls clobber the non-callee saved registers. RSP is marked as
407 // a use to prevent stack-pointer assignments that appear immediately
408 // before calls from potentially appearing dead.
409 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
410 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
411 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
412 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
413 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
415 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
417 [(X86tlsaddr tls64addr:$sym)]>,
418 Requires<[In64BitMode]>;
419 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
421 [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
422 Requires<[In64BitMode]>;
425 // Darwin TLS Support
426 // For i386, the address of the thunk is passed on the stack, on return the
427 // address of the variable is in %eax. %ecx is trashed during the function
428 // call. All other registers are preserved.
429 let Defs = [EAX, ECX, EFLAGS],
431 usesCustomInserter = 1 in
432 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
434 [(X86TLSCall addr:$sym)]>,
435 Requires<[In32BitMode]>;
437 // For x86_64, the address of the thunk is passed in %rdi, on return
438 // the address of the variable is in %rax. All other registers are preserved.
439 let Defs = [RAX, EFLAGS],
441 usesCustomInserter = 1 in
442 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
444 [(X86TLSCall addr:$sym)]>,
445 Requires<[In64BitMode]>;
448 //===----------------------------------------------------------------------===//
449 // Conditional Move Pseudo Instructions
451 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
452 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
453 // however that requires promoting the operands, and can induce additional
454 // i8 register pressure.
455 let usesCustomInserter = 1, Uses = [EFLAGS] in {
456 def CMOV_GR8 : I<0, Pseudo,
457 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
459 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
460 imm:$cond, EFLAGS))]>;
462 let Predicates = [NoCMov] in {
463 def CMOV_GR32 : I<0, Pseudo,
464 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
465 "#CMOV_GR32* PSEUDO!",
467 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
468 def CMOV_GR16 : I<0, Pseudo,
469 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
470 "#CMOV_GR16* PSEUDO!",
472 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
473 } // Predicates = [NoCMov]
475 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
477 let Predicates = [FPStackf32] in
478 def CMOV_RFP32 : I<0, Pseudo,
480 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
481 "#CMOV_RFP32 PSEUDO!",
483 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
485 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
487 let Predicates = [FPStackf64] in
488 def CMOV_RFP64 : I<0, Pseudo,
490 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
491 "#CMOV_RFP64 PSEUDO!",
493 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
495 def CMOV_RFP80 : I<0, Pseudo,
497 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
498 "#CMOV_RFP80 PSEUDO!",
500 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
502 } // UsesCustomInserter = 1, Uses = [EFLAGS]
505 //===----------------------------------------------------------------------===//
506 // Atomic Instruction Pseudo Instructions
507 //===----------------------------------------------------------------------===//
509 // Pseudo atomic instructions
511 multiclass PSEUDO_ATOMIC_LOAD_BINOP<string mnemonic> {
512 let usesCustomInserter = 1, mayLoad = 1, mayStore = 1 in {
513 let Defs = [EFLAGS, AL] in
514 def NAME#8 : I<0, Pseudo, (outs GR8:$dst),
515 (ins i8mem:$ptr, GR8:$val),
516 !strconcat(mnemonic, "8 PSEUDO!"), []>;
517 let Defs = [EFLAGS, AX] in
518 def NAME#16 : I<0, Pseudo,(outs GR16:$dst),
519 (ins i16mem:$ptr, GR16:$val),
520 !strconcat(mnemonic, "16 PSEUDO!"), []>;
521 let Defs = [EFLAGS, EAX] in
522 def NAME#32 : I<0, Pseudo, (outs GR32:$dst),
523 (ins i32mem:$ptr, GR32:$val),
524 !strconcat(mnemonic, "32 PSEUDO!"), []>;
525 let Defs = [EFLAGS, RAX] in
526 def NAME#64 : I<0, Pseudo, (outs GR64:$dst),
527 (ins i64mem:$ptr, GR64:$val),
528 !strconcat(mnemonic, "64 PSEUDO!"), []>;
532 multiclass PSEUDO_ATOMIC_LOAD_BINOP_PATS<string name, string frag> {
533 def : Pat<(!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val),
534 (!cast<Instruction>(name # "8") addr:$ptr, GR8:$val)>;
535 def : Pat<(!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val),
536 (!cast<Instruction>(name # "16") addr:$ptr, GR16:$val)>;
537 def : Pat<(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val),
538 (!cast<Instruction>(name # "32") addr:$ptr, GR32:$val)>;
539 def : Pat<(!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val),
540 (!cast<Instruction>(name # "64") addr:$ptr, GR64:$val)>;
543 // Atomic exchange, and, or, xor
544 defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMAND">;
545 defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMOR">;
546 defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMXOR">;
547 defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMNAND">;
548 defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMAX">;
549 defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMIN">;
550 defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMAX">;
551 defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMIN">;
553 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMAND", "atomic_load_and">;
554 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMOR", "atomic_load_or">;
555 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMXOR", "atomic_load_xor">;
556 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMNAND", "atomic_load_nand">;
557 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMAX", "atomic_load_max">;
558 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMIN", "atomic_load_min">;
559 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMAX", "atomic_load_umax">;
560 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMIN", "atomic_load_umin">;
562 multiclass PSEUDO_ATOMIC_LOAD_BINOP6432<string mnemonic> {
563 let usesCustomInserter = 1, Defs = [EFLAGS, EAX, EDX],
564 mayLoad = 1, mayStore = 1, hasSideEffects = 0 in
565 def NAME#6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
566 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
567 !strconcat(mnemonic, "6432 PSEUDO!"), []>;
570 defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMAND">;
571 defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMOR">;
572 defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMXOR">;
573 defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMNAND">;
574 defm ATOMADD : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMADD">;
575 defm ATOMSUB : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMSUB">;
576 defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMMAX">;
577 defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMMIN">;
578 defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMUMAX">;
579 defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMUMIN">;
580 defm ATOMSWAP : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMSWAP">;
582 //===----------------------------------------------------------------------===//
583 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
584 //===----------------------------------------------------------------------===//
586 // FIXME: Use normal instructions and add lock prefix dynamically.
590 // TODO: Get this to fold the constant into the instruction.
591 let isCodeGenOnly = 1, Defs = [EFLAGS] in
592 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
593 "or{l}\t{$zero, $dst|$dst, $zero}",
594 [], IIC_ALU_MEM>, Requires<[In32BitMode]>, LOCK,
595 Sched<[WriteALULd, WriteRMW]>;
597 let hasSideEffects = 1 in
598 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
600 [(X86MemBarrier)]>, Sched<[WriteLoad]>;
602 // RegOpc corresponds to the mr version of the instruction
603 // ImmOpc corresponds to the mi version of the instruction
604 // ImmOpc8 corresponds to the mi8 version of the instruction
605 // ImmMod corresponds to the instruction format of the mi and mi8 versions
606 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
607 Format ImmMod, string mnemonic> {
608 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
609 SchedRW = [WriteALULd, WriteRMW] in {
611 def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
612 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
613 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
614 !strconcat(mnemonic, "{b}\t",
615 "{$src2, $dst|$dst, $src2}"),
616 [], IIC_ALU_NONMEM>, LOCK;
617 def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
618 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
619 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
620 !strconcat(mnemonic, "{w}\t",
621 "{$src2, $dst|$dst, $src2}"),
622 [], IIC_ALU_NONMEM>, OpSize, LOCK;
623 def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
624 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
625 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
626 !strconcat(mnemonic, "{l}\t",
627 "{$src2, $dst|$dst, $src2}"),
628 [], IIC_ALU_NONMEM>, LOCK;
629 def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
630 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
631 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
632 !strconcat(mnemonic, "{q}\t",
633 "{$src2, $dst|$dst, $src2}"),
634 [], IIC_ALU_NONMEM>, LOCK;
636 def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
637 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
638 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
639 !strconcat(mnemonic, "{b}\t",
640 "{$src2, $dst|$dst, $src2}"),
641 [], IIC_ALU_MEM>, LOCK;
643 def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
644 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
645 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
646 !strconcat(mnemonic, "{w}\t",
647 "{$src2, $dst|$dst, $src2}"),
648 [], IIC_ALU_MEM>, OpSize, LOCK;
650 def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
651 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
652 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
653 !strconcat(mnemonic, "{l}\t",
654 "{$src2, $dst|$dst, $src2}"),
655 [], IIC_ALU_MEM>, LOCK;
657 def NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
658 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
659 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
660 !strconcat(mnemonic, "{q}\t",
661 "{$src2, $dst|$dst, $src2}"),
662 [], IIC_ALU_MEM>, LOCK;
664 def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
665 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
666 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
667 !strconcat(mnemonic, "{w}\t",
668 "{$src2, $dst|$dst, $src2}"),
669 [], IIC_ALU_MEM>, OpSize, LOCK;
670 def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
671 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
672 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
673 !strconcat(mnemonic, "{l}\t",
674 "{$src2, $dst|$dst, $src2}"),
675 [], IIC_ALU_MEM>, LOCK;
676 def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
677 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
678 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
679 !strconcat(mnemonic, "{q}\t",
680 "{$src2, $dst|$dst, $src2}"),
681 [], IIC_ALU_MEM>, LOCK;
687 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
688 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
689 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
690 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
691 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
693 // Optimized codegen when the non-memory output is not used.
694 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
696 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
697 SchedRW = [WriteALULd, WriteRMW] in {
699 def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
700 !strconcat(mnemonic, "{b}\t$dst"),
701 [], IIC_UNARY_MEM>, LOCK;
702 def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
703 !strconcat(mnemonic, "{w}\t$dst"),
704 [], IIC_UNARY_MEM>, OpSize, LOCK;
705 def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
706 !strconcat(mnemonic, "{l}\t$dst"),
707 [], IIC_UNARY_MEM>, LOCK;
708 def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
709 !strconcat(mnemonic, "{q}\t$dst"),
710 [], IIC_UNARY_MEM>, LOCK;
714 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;
715 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;
717 // Atomic compare and swap.
718 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
719 SDPatternOperator frag, X86MemOperand x86memop,
720 InstrItinClass itin> {
721 let isCodeGenOnly = 1 in {
722 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr),
723 !strconcat(mnemonic, "\t$ptr"),
724 [(frag addr:$ptr)], itin>, TB, LOCK;
728 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
729 string mnemonic, SDPatternOperator frag,
730 InstrItinClass itin8, InstrItinClass itin> {
731 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
732 let Defs = [AL, EFLAGS], Uses = [AL] in
733 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
734 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
735 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
736 let Defs = [AX, EFLAGS], Uses = [AX] in
737 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
738 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
739 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize, LOCK;
740 let Defs = [EAX, EFLAGS], Uses = [EAX] in
741 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
742 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
743 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, LOCK;
744 let Defs = [RAX, EFLAGS], Uses = [RAX] in
745 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
746 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
747 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
751 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
752 SchedRW = [WriteALULd, WriteRMW] in {
753 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
758 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
759 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
760 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
762 IIC_CMPX_LOCK_16B>, REX_W;
765 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
766 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
768 // Atomic exchange and add
769 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
771 InstrItinClass itin8, InstrItinClass itin> {
772 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1,
773 SchedRW = [WriteALULd, WriteRMW] in {
774 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
775 (ins GR8:$val, i8mem:$ptr),
776 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
778 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
780 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
781 (ins GR16:$val, i16mem:$ptr),
782 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
785 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
787 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
788 (ins GR32:$val, i32mem:$ptr),
789 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
792 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
794 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
795 (ins GR64:$val, i64mem:$ptr),
796 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
799 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
804 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
805 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
808 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
809 "#ACQUIRE_MOV PSEUDO!",
810 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
811 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
812 "#ACQUIRE_MOV PSEUDO!",
813 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
814 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
815 "#ACQUIRE_MOV PSEUDO!",
816 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
817 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
818 "#ACQUIRE_MOV PSEUDO!",
819 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
821 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
822 "#RELEASE_MOV PSEUDO!",
823 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
824 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
825 "#RELEASE_MOV PSEUDO!",
826 [(atomic_store_16 addr:$dst, GR16:$src)]>;
827 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
828 "#RELEASE_MOV PSEUDO!",
829 [(atomic_store_32 addr:$dst, GR32:$src)]>;
830 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
831 "#RELEASE_MOV PSEUDO!",
832 [(atomic_store_64 addr:$dst, GR64:$src)]>;
834 //===----------------------------------------------------------------------===//
835 // Conditional Move Pseudo Instructions.
836 //===----------------------------------------------------------------------===//
839 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
840 // instruction selection into a branch sequence.
841 let Uses = [EFLAGS], usesCustomInserter = 1 in {
842 def CMOV_FR32 : I<0, Pseudo,
843 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
844 "#CMOV_FR32 PSEUDO!",
845 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
847 def CMOV_FR64 : I<0, Pseudo,
848 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
849 "#CMOV_FR64 PSEUDO!",
850 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
852 def CMOV_V4F32 : I<0, Pseudo,
853 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
854 "#CMOV_V4F32 PSEUDO!",
856 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
858 def CMOV_V2F64 : I<0, Pseudo,
859 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
860 "#CMOV_V2F64 PSEUDO!",
862 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
864 def CMOV_V2I64 : I<0, Pseudo,
865 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
866 "#CMOV_V2I64 PSEUDO!",
868 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
870 def CMOV_V8F32 : I<0, Pseudo,
871 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
872 "#CMOV_V8F32 PSEUDO!",
874 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond,
876 def CMOV_V4F64 : I<0, Pseudo,
877 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
878 "#CMOV_V4F64 PSEUDO!",
880 (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
882 def CMOV_V4I64 : I<0, Pseudo,
883 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
884 "#CMOV_V4I64 PSEUDO!",
886 (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
888 def CMOV_V8I64 : I<0, Pseudo,
889 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
890 "#CMOV_V8I64 PSEUDO!",
892 (v8i64 (X86cmov VR512:$t, VR512:$f, imm:$cond,
894 def CMOV_V8F64 : I<0, Pseudo,
895 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
896 "#CMOV_V8F64 PSEUDO!",
898 (v8f64 (X86cmov VR512:$t, VR512:$f, imm:$cond,
900 def CMOV_V16F32 : I<0, Pseudo,
901 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
902 "#CMOV_V16F32 PSEUDO!",
904 (v16f32 (X86cmov VR512:$t, VR512:$f, imm:$cond,
909 //===----------------------------------------------------------------------===//
910 // DAG Pattern Matching Rules
911 //===----------------------------------------------------------------------===//
913 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
914 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
915 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
916 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
917 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
918 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
919 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
921 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
922 (ADD32ri GR32:$src1, tconstpool:$src2)>;
923 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
924 (ADD32ri GR32:$src1, tjumptable:$src2)>;
925 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
926 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
927 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
928 (ADD32ri GR32:$src1, texternalsym:$src2)>;
929 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
930 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
932 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
933 (MOV32mi addr:$dst, tglobaladdr:$src)>;
934 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
935 (MOV32mi addr:$dst, texternalsym:$src)>;
936 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
937 (MOV32mi addr:$dst, tblockaddress:$src)>;
939 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
940 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
941 // 'movabs' predicate should handle this sort of thing.
942 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
943 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
944 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
945 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
946 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
947 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
948 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
949 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
950 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
951 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
953 // In kernel code model, we can get the address of a label
954 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
955 // the MOV64ri32 should accept these.
956 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
957 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
958 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
959 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
960 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
961 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
962 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
963 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
964 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
965 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
967 // If we have small model and -static mode, it is safe to store global addresses
968 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
969 // for MOV64mi32 should handle this sort of thing.
970 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
971 (MOV64mi32 addr:$dst, tconstpool:$src)>,
972 Requires<[NearData, IsStatic]>;
973 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
974 (MOV64mi32 addr:$dst, tjumptable:$src)>,
975 Requires<[NearData, IsStatic]>;
976 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
977 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
978 Requires<[NearData, IsStatic]>;
979 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
980 (MOV64mi32 addr:$dst, texternalsym:$src)>,
981 Requires<[NearData, IsStatic]>;
982 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
983 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
984 Requires<[NearData, IsStatic]>;
988 // tls has some funny stuff here...
989 // This corresponds to movabs $foo@tpoff, %rax
990 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
991 (MOV64ri32 tglobaltlsaddr :$dst)>;
992 // This corresponds to add $foo@tpoff, %rax
993 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
994 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
997 // Direct PC relative function call for small code model. 32-bit displacement
998 // sign extended to 64-bit.
999 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1000 (CALL64pcrel32 tglobaladdr:$dst)>;
1001 def : Pat<(X86call (i64 texternalsym:$dst)),
1002 (CALL64pcrel32 texternalsym:$dst)>;
1004 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
1005 // can never use callee-saved registers. That is the purpose of the GR64_TC
1006 // register classes.
1008 // The only volatile register that is never used by the calling convention is
1009 // %r11. This happens when calling a vararg function with 6 arguments.
1011 // Match an X86tcret that uses less than 7 volatile registers.
1012 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
1013 (X86tcret node:$ptr, node:$off), [{
1014 // X86tcret args: (*chain, ptr, imm, regs..., glue)
1015 unsigned NumRegs = 0;
1016 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
1017 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
1022 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1023 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
1024 Requires<[In32BitMode]>;
1026 // FIXME: This is disabled for 32-bit PIC mode because the global base
1027 // register which is part of the address mode may be assigned a
1028 // callee-saved register.
1029 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1030 (TCRETURNmi addr:$dst, imm:$off)>,
1031 Requires<[In32BitMode, IsNotPIC]>;
1033 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
1034 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1035 Requires<[In32BitMode]>;
1037 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
1038 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1039 Requires<[In32BitMode]>;
1041 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1042 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
1043 Requires<[In64BitMode]>;
1045 // Don't fold loads into X86tcret requiring more than 6 regs.
1046 // There wouldn't be enough scratch registers for base+index.
1047 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
1048 (TCRETURNmi64 addr:$dst, imm:$off)>,
1049 Requires<[In64BitMode]>;
1051 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1052 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1053 Requires<[In64BitMode]>;
1055 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1056 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1057 Requires<[In64BitMode]>;
1059 // Normal calls, with various flavors of addresses.
1060 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1061 (CALLpcrel32 tglobaladdr:$dst)>;
1062 def : Pat<(X86call (i32 texternalsym:$dst)),
1063 (CALLpcrel32 texternalsym:$dst)>;
1064 def : Pat<(X86call (i32 imm:$dst)),
1065 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1069 // TEST R,R is smaller than CMP R,0
1070 def : Pat<(X86cmp GR8:$src1, 0),
1071 (TEST8rr GR8:$src1, GR8:$src1)>;
1072 def : Pat<(X86cmp GR16:$src1, 0),
1073 (TEST16rr GR16:$src1, GR16:$src1)>;
1074 def : Pat<(X86cmp GR32:$src1, 0),
1075 (TEST32rr GR32:$src1, GR32:$src1)>;
1076 def : Pat<(X86cmp GR64:$src1, 0),
1077 (TEST64rr GR64:$src1, GR64:$src1)>;
1079 // Conditional moves with folded loads with operands swapped and conditions
1081 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1082 Instruction Inst64> {
1083 let Predicates = [HasCMov] in {
1084 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1085 (Inst16 GR16:$src2, addr:$src1)>;
1086 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1087 (Inst32 GR32:$src2, addr:$src1)>;
1088 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1089 (Inst64 GR64:$src2, addr:$src1)>;
1093 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1094 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1095 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1096 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1097 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1098 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1099 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1100 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1101 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1102 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1103 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1104 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1105 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1106 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1107 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1108 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1110 // zextload bool -> zextload byte
1111 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1112 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1113 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1114 def : Pat<(zextloadi64i1 addr:$src),
1115 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1117 // extload bool -> extload byte
1118 // When extloading from 16-bit and smaller memory locations into 64-bit
1119 // registers, use zero-extending loads so that the entire 64-bit register is
1120 // defined, avoiding partial-register updates.
1122 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1123 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1124 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1125 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1126 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1127 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1129 // For other extloads, use subregs, since the high contents of the register are
1130 // defined after an extload.
1131 def : Pat<(extloadi64i1 addr:$src),
1132 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1133 def : Pat<(extloadi64i8 addr:$src),
1134 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1135 def : Pat<(extloadi64i16 addr:$src),
1136 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1137 def : Pat<(extloadi64i32 addr:$src),
1138 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1140 // anyext. Define these to do an explicit zero-extend to
1141 // avoid partial-register updates.
1142 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1143 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1144 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1146 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1147 def : Pat<(i32 (anyext GR16:$src)),
1148 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1150 def : Pat<(i64 (anyext GR8 :$src)),
1151 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1152 def : Pat<(i64 (anyext GR16:$src)),
1153 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
1154 def : Pat<(i64 (anyext GR32:$src)),
1155 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1158 // Any instruction that defines a 32-bit result leaves the high half of the
1159 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1160 // be copying from a truncate. And x86's cmov doesn't do anything if the
1161 // condition is false. But any other 32-bit operation will zero-extend
1163 def def32 : PatLeaf<(i32 GR32:$src), [{
1164 return N->getOpcode() != ISD::TRUNCATE &&
1165 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1166 N->getOpcode() != ISD::CopyFromReg &&
1167 N->getOpcode() != X86ISD::CMOV;
1170 // In the case of a 32-bit def that is known to implicitly zero-extend,
1171 // we can use a SUBREG_TO_REG.
1172 def : Pat<(i64 (zext def32:$src)),
1173 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1175 //===----------------------------------------------------------------------===//
1176 // Pattern match OR as ADD
1177 //===----------------------------------------------------------------------===//
1179 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1180 // 3-addressified into an LEA instruction to avoid copies. However, we also
1181 // want to finally emit these instructions as an or at the end of the code
1182 // generator to make the generated code easier to read. To do this, we select
1183 // into "disjoint bits" pseudo ops.
1185 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1186 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1187 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1188 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1190 APInt KnownZero0, KnownOne0;
1191 CurDAG->ComputeMaskedBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
1192 APInt KnownZero1, KnownOne1;
1193 CurDAG->ComputeMaskedBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
1194 return (~KnownZero0 & ~KnownZero1) == 0;
1198 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1199 // Try this before the selecting to OR.
1200 let AddedComplexity = 5, SchedRW = [WriteALU] in {
1202 let isConvertibleToThreeAddress = 1,
1203 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1204 let isCommutable = 1 in {
1205 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1206 "", // orw/addw REG, REG
1207 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1208 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1209 "", // orl/addl REG, REG
1210 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1211 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1212 "", // orq/addq REG, REG
1213 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1216 // NOTE: These are order specific, we want the ri8 forms to be listed
1217 // first so that they are slightly preferred to the ri forms.
1219 def ADD16ri8_DB : I<0, Pseudo,
1220 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1221 "", // orw/addw REG, imm8
1222 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1223 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1224 "", // orw/addw REG, imm
1225 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1227 def ADD32ri8_DB : I<0, Pseudo,
1228 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1229 "", // orl/addl REG, imm8
1230 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1231 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1232 "", // orl/addl REG, imm
1233 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1236 def ADD64ri8_DB : I<0, Pseudo,
1237 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1238 "", // orq/addq REG, imm8
1239 [(set GR64:$dst, (or_is_add GR64:$src1,
1240 i64immSExt8:$src2))]>;
1241 def ADD64ri32_DB : I<0, Pseudo,
1242 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1243 "", // orq/addq REG, imm
1244 [(set GR64:$dst, (or_is_add GR64:$src1,
1245 i64immSExt32:$src2))]>;
1247 } // AddedComplexity, SchedRW
1250 //===----------------------------------------------------------------------===//
1252 //===----------------------------------------------------------------------===//
1254 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1255 // +128 doesn't, so in this special case use a sub instead of an add.
1256 def : Pat<(add GR16:$src1, 128),
1257 (SUB16ri8 GR16:$src1, -128)>;
1258 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1259 (SUB16mi8 addr:$dst, -128)>;
1261 def : Pat<(add GR32:$src1, 128),
1262 (SUB32ri8 GR32:$src1, -128)>;
1263 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1264 (SUB32mi8 addr:$dst, -128)>;
1266 def : Pat<(add GR64:$src1, 128),
1267 (SUB64ri8 GR64:$src1, -128)>;
1268 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1269 (SUB64mi8 addr:$dst, -128)>;
1271 // The same trick applies for 32-bit immediate fields in 64-bit
1273 def : Pat<(add GR64:$src1, 0x0000000080000000),
1274 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1275 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1276 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1278 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1279 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1280 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1281 // represented with a sign extension of a 8 bit constant, use that.
1283 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1287 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1288 (i32 (GetLo8XForm imm:$imm))),
1291 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1295 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1296 (i32 (GetLo32XForm imm:$imm))),
1300 // r & (2^16-1) ==> movz
1301 def : Pat<(and GR32:$src1, 0xffff),
1302 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1303 // r & (2^8-1) ==> movz
1304 def : Pat<(and GR32:$src1, 0xff),
1305 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1308 Requires<[In32BitMode]>;
1309 // r & (2^8-1) ==> movz
1310 def : Pat<(and GR16:$src1, 0xff),
1311 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1312 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1314 Requires<[In32BitMode]>;
1316 // r & (2^32-1) ==> movz
1317 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1318 (SUBREG_TO_REG (i64 0),
1319 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)),
1321 // r & (2^16-1) ==> movz
1322 def : Pat<(and GR64:$src, 0xffff),
1323 (SUBREG_TO_REG (i64 0),
1324 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))),
1326 // r & (2^8-1) ==> movz
1327 def : Pat<(and GR64:$src, 0xff),
1328 (SUBREG_TO_REG (i64 0),
1329 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))),
1331 // r & (2^8-1) ==> movz
1332 def : Pat<(and GR32:$src1, 0xff),
1333 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1334 Requires<[In64BitMode]>;
1335 // r & (2^8-1) ==> movz
1336 def : Pat<(and GR16:$src1, 0xff),
1337 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1338 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1339 Requires<[In64BitMode]>;
1342 // sext_inreg patterns
1343 def : Pat<(sext_inreg GR32:$src, i16),
1344 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1345 def : Pat<(sext_inreg GR32:$src, i8),
1346 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1349 Requires<[In32BitMode]>;
1351 def : Pat<(sext_inreg GR16:$src, i8),
1352 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1353 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1355 Requires<[In32BitMode]>;
1357 def : Pat<(sext_inreg GR64:$src, i32),
1358 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1359 def : Pat<(sext_inreg GR64:$src, i16),
1360 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1361 def : Pat<(sext_inreg GR64:$src, i8),
1362 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1363 def : Pat<(sext_inreg GR32:$src, i8),
1364 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1365 Requires<[In64BitMode]>;
1366 def : Pat<(sext_inreg GR16:$src, i8),
1367 (EXTRACT_SUBREG (MOVSX32rr8
1368 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1369 Requires<[In64BitMode]>;
1371 // sext, sext_load, zext, zext_load
1372 def: Pat<(i16 (sext GR8:$src)),
1373 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1374 def: Pat<(sextloadi16i8 addr:$src),
1375 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1376 def: Pat<(i16 (zext GR8:$src)),
1377 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1378 def: Pat<(zextloadi16i8 addr:$src),
1379 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1382 def : Pat<(i16 (trunc GR32:$src)),
1383 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1384 def : Pat<(i8 (trunc GR32:$src)),
1385 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1387 Requires<[In32BitMode]>;
1388 def : Pat<(i8 (trunc GR16:$src)),
1389 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1391 Requires<[In32BitMode]>;
1392 def : Pat<(i32 (trunc GR64:$src)),
1393 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1394 def : Pat<(i16 (trunc GR64:$src)),
1395 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1396 def : Pat<(i8 (trunc GR64:$src)),
1397 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1398 def : Pat<(i8 (trunc GR32:$src)),
1399 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1400 Requires<[In64BitMode]>;
1401 def : Pat<(i8 (trunc GR16:$src)),
1402 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1403 Requires<[In64BitMode]>;
1405 // h-register tricks
1406 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1407 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1409 Requires<[In32BitMode]>;
1410 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1411 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1413 Requires<[In32BitMode]>;
1414 def : Pat<(srl GR16:$src, (i8 8)),
1417 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1420 Requires<[In32BitMode]>;
1421 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1422 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1425 Requires<[In32BitMode]>;
1426 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1427 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1430 Requires<[In32BitMode]>;
1431 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1432 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1435 Requires<[In32BitMode]>;
1436 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1437 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1440 Requires<[In32BitMode]>;
1442 // h-register tricks.
1443 // For now, be conservative on x86-64 and use an h-register extract only if the
1444 // value is immediately zero-extended or stored, which are somewhat common
1445 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1446 // from being allocated in the same instruction as the h register, as there's
1447 // currently no way to describe this requirement to the register allocator.
1449 // h-register extract and zero-extend.
1450 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1454 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1457 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1459 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1461 Requires<[In64BitMode]>;
1462 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1463 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1466 Requires<[In64BitMode]>;
1467 def : Pat<(srl GR16:$src, (i8 8)),
1470 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1473 Requires<[In64BitMode]>;
1474 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1476 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1478 Requires<[In64BitMode]>;
1479 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1481 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1483 Requires<[In64BitMode]>;
1484 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1488 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1491 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1495 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1499 // h-register extract and store.
1500 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1503 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1505 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1508 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1510 Requires<[In64BitMode]>;
1511 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1514 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1516 Requires<[In64BitMode]>;
1519 // (shl x, 1) ==> (add x, x)
1520 // Note that if x is undef (immediate or otherwise), we could theoretically
1521 // end up with the two uses of x getting different values, producing a result
1522 // where the least significant bit is not 0. However, the probability of this
1523 // happening is considered low enough that this is officially not a
1525 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1526 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1527 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1528 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1530 // Helper imms that check if a mask doesn't change significant shift bits.
1531 def immShift32 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 5; }]>;
1532 def immShift64 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 6; }]>;
1534 // (shl x (and y, 31)) ==> (shl x, y)
1535 def : Pat<(shl GR8:$src1, (and CL, immShift32)),
1536 (SHL8rCL GR8:$src1)>;
1537 def : Pat<(shl GR16:$src1, (and CL, immShift32)),
1538 (SHL16rCL GR16:$src1)>;
1539 def : Pat<(shl GR32:$src1, (and CL, immShift32)),
1540 (SHL32rCL GR32:$src1)>;
1541 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1542 (SHL8mCL addr:$dst)>;
1543 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1544 (SHL16mCL addr:$dst)>;
1545 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1546 (SHL32mCL addr:$dst)>;
1548 def : Pat<(srl GR8:$src1, (and CL, immShift32)),
1549 (SHR8rCL GR8:$src1)>;
1550 def : Pat<(srl GR16:$src1, (and CL, immShift32)),
1551 (SHR16rCL GR16:$src1)>;
1552 def : Pat<(srl GR32:$src1, (and CL, immShift32)),
1553 (SHR32rCL GR32:$src1)>;
1554 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1555 (SHR8mCL addr:$dst)>;
1556 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1557 (SHR16mCL addr:$dst)>;
1558 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1559 (SHR32mCL addr:$dst)>;
1561 def : Pat<(sra GR8:$src1, (and CL, immShift32)),
1562 (SAR8rCL GR8:$src1)>;
1563 def : Pat<(sra GR16:$src1, (and CL, immShift32)),
1564 (SAR16rCL GR16:$src1)>;
1565 def : Pat<(sra GR32:$src1, (and CL, immShift32)),
1566 (SAR32rCL GR32:$src1)>;
1567 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1568 (SAR8mCL addr:$dst)>;
1569 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1570 (SAR16mCL addr:$dst)>;
1571 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1572 (SAR32mCL addr:$dst)>;
1574 // (shl x (and y, 63)) ==> (shl x, y)
1575 def : Pat<(shl GR64:$src1, (and CL, immShift64)),
1576 (SHL64rCL GR64:$src1)>;
1577 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1578 (SHL64mCL addr:$dst)>;
1580 def : Pat<(srl GR64:$src1, (and CL, immShift64)),
1581 (SHR64rCL GR64:$src1)>;
1582 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1583 (SHR64mCL addr:$dst)>;
1585 def : Pat<(sra GR64:$src1, (and CL, immShift64)),
1586 (SAR64rCL GR64:$src1)>;
1587 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1588 (SAR64mCL addr:$dst)>;
1591 // (anyext (setcc_carry)) -> (setcc_carry)
1592 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1594 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1596 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1602 //===----------------------------------------------------------------------===//
1603 // EFLAGS-defining Patterns
1604 //===----------------------------------------------------------------------===//
1607 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1608 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1609 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1612 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1613 (ADD8rm GR8:$src1, addr:$src2)>;
1614 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1615 (ADD16rm GR16:$src1, addr:$src2)>;
1616 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1617 (ADD32rm GR32:$src1, addr:$src2)>;
1620 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1621 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1622 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1623 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1624 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1625 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1626 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1629 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1630 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1631 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1634 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1635 (SUB8rm GR8:$src1, addr:$src2)>;
1636 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1637 (SUB16rm GR16:$src1, addr:$src2)>;
1638 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1639 (SUB32rm GR32:$src1, addr:$src2)>;
1642 def : Pat<(sub GR8:$src1, imm:$src2),
1643 (SUB8ri GR8:$src1, imm:$src2)>;
1644 def : Pat<(sub GR16:$src1, imm:$src2),
1645 (SUB16ri GR16:$src1, imm:$src2)>;
1646 def : Pat<(sub GR32:$src1, imm:$src2),
1647 (SUB32ri GR32:$src1, imm:$src2)>;
1648 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1649 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1650 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1651 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1654 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>;
1655 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
1656 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
1657 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
1660 def : Pat<(mul GR16:$src1, GR16:$src2),
1661 (IMUL16rr GR16:$src1, GR16:$src2)>;
1662 def : Pat<(mul GR32:$src1, GR32:$src2),
1663 (IMUL32rr GR32:$src1, GR32:$src2)>;
1666 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1667 (IMUL16rm GR16:$src1, addr:$src2)>;
1668 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1669 (IMUL32rm GR32:$src1, addr:$src2)>;
1672 def : Pat<(mul GR16:$src1, imm:$src2),
1673 (IMUL16rri GR16:$src1, imm:$src2)>;
1674 def : Pat<(mul GR32:$src1, imm:$src2),
1675 (IMUL32rri GR32:$src1, imm:$src2)>;
1676 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1677 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1678 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1679 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1681 // reg = mul mem, imm
1682 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1683 (IMUL16rmi addr:$src1, imm:$src2)>;
1684 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1685 (IMUL32rmi addr:$src1, imm:$src2)>;
1686 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1687 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1688 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1689 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1691 // Patterns for nodes that do not produce flags, for instructions that do.
1694 def : Pat<(add GR64:$src1, GR64:$src2),
1695 (ADD64rr GR64:$src1, GR64:$src2)>;
1696 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1697 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1698 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1699 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1700 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1701 (ADD64rm GR64:$src1, addr:$src2)>;
1704 def : Pat<(sub GR64:$src1, GR64:$src2),
1705 (SUB64rr GR64:$src1, GR64:$src2)>;
1706 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1707 (SUB64rm GR64:$src1, addr:$src2)>;
1708 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1709 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1710 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1711 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1714 def : Pat<(mul GR64:$src1, GR64:$src2),
1715 (IMUL64rr GR64:$src1, GR64:$src2)>;
1716 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1717 (IMUL64rm GR64:$src1, addr:$src2)>;
1718 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1719 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1720 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1721 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1722 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1723 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1724 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1725 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1728 def : Pat<(add GR8 :$src, 1), (INC8r GR8 :$src)>;
1729 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
1730 def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1731 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
1732 def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1733 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1736 def : Pat<(add GR8 :$src, -1), (DEC8r GR8 :$src)>;
1737 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
1738 def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1739 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
1740 def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1741 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1744 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1745 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1746 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1747 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1750 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1751 (OR8rm GR8:$src1, addr:$src2)>;
1752 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1753 (OR16rm GR16:$src1, addr:$src2)>;
1754 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1755 (OR32rm GR32:$src1, addr:$src2)>;
1756 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1757 (OR64rm GR64:$src1, addr:$src2)>;
1760 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1761 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1762 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1763 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1764 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1765 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1766 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1767 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1768 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1769 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1770 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1773 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1774 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1775 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1776 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1779 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1780 (XOR8rm GR8:$src1, addr:$src2)>;
1781 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1782 (XOR16rm GR16:$src1, addr:$src2)>;
1783 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1784 (XOR32rm GR32:$src1, addr:$src2)>;
1785 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1786 (XOR64rm GR64:$src1, addr:$src2)>;
1789 def : Pat<(xor GR8:$src1, imm:$src2),
1790 (XOR8ri GR8:$src1, imm:$src2)>;
1791 def : Pat<(xor GR16:$src1, imm:$src2),
1792 (XOR16ri GR16:$src1, imm:$src2)>;
1793 def : Pat<(xor GR32:$src1, imm:$src2),
1794 (XOR32ri GR32:$src1, imm:$src2)>;
1795 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1796 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1797 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1798 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1799 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1800 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1801 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1802 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1805 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1806 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1807 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1808 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1811 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1812 (AND8rm GR8:$src1, addr:$src2)>;
1813 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1814 (AND16rm GR16:$src1, addr:$src2)>;
1815 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1816 (AND32rm GR32:$src1, addr:$src2)>;
1817 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1818 (AND64rm GR64:$src1, addr:$src2)>;
1821 def : Pat<(and GR8:$src1, imm:$src2),
1822 (AND8ri GR8:$src1, imm:$src2)>;
1823 def : Pat<(and GR16:$src1, imm:$src2),
1824 (AND16ri GR16:$src1, imm:$src2)>;
1825 def : Pat<(and GR32:$src1, imm:$src2),
1826 (AND32ri GR32:$src1, imm:$src2)>;
1827 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1828 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1829 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1830 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1831 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1832 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1833 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1834 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1836 // Bit scan instruction patterns to match explicit zero-undef behavior.
1837 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
1838 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
1839 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
1840 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
1841 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
1842 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;