1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((uint32_t)N->getZExtValue(), SDLoc(N));
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP, SSP],
36 SchedRW = [WriteJump] in
37 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // 64-bit large code model PIC base construction.
41 let hasSideEffects = 0, mayLoad = 1, isNotDuplicable = 1, SchedRW = [WriteJump] in
42 def MOVGOT64r : PseudoI<(outs GR64:$reg),
43 (ins GR64:$scratch, i64i32imm_pcrel:$got), []>;
45 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
46 // a stack adjustment and the codegen must know that they may modify the stack
47 // pointer before prolog-epilog rewriting occurs.
48 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
49 // sub / add which can clobber EFLAGS.
50 let Defs = [ESP, EFLAGS, SSP], Uses = [ESP, SSP], SchedRW = [WriteALU] in {
51 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs),
52 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3),
53 "#ADJCALLSTACKDOWN", []>, Requires<[NotLP64]>;
54 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
56 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
59 def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
60 (ADJCALLSTACKDOWN32 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[NotLP64]>;
63 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
64 // a stack adjustment and the codegen must know that they may modify the stack
65 // pointer before prolog-epilog rewriting occurs.
66 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
67 // sub / add which can clobber EFLAGS.
68 let Defs = [RSP, EFLAGS, SSP], Uses = [RSP, SSP], SchedRW = [WriteALU] in {
69 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs),
70 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3),
71 "#ADJCALLSTACKDOWN", []>, Requires<[IsLP64]>;
72 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
74 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
77 def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
78 (ADJCALLSTACKDOWN64 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[IsLP64]>;
80 let SchedRW = [WriteSystem] in {
82 // x86-64 va_start lowering magic.
83 let usesCustomInserter = 1, Defs = [EFLAGS] in {
84 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
87 i64imm:$regsavefi, i64imm:$offset,
89 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
90 [(X86vastart_save_xmm_regs GR8:$al,
95 // The VAARG_64 pseudo-instruction takes the address of the va_list,
96 // and places the address of the next argument into a register.
97 let Defs = [EFLAGS] in
98 def VAARG_64 : I<0, Pseudo,
100 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
101 "#VAARG_64 $dst, $ap, $size, $mode, $align",
103 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
107 // When using segmented stacks these are lowered into instructions which first
108 // check if the current stacklet has enough free memory. If it does, memory is
109 // allocated by bumping the stack pointer. Otherwise memory is allocated from
112 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
113 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
114 "# variable sized alloca for segmented stacks",
116 (X86SegAlloca GR32:$size))]>,
119 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
120 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
121 "# variable sized alloca for segmented stacks",
123 (X86SegAlloca GR64:$size))]>,
124 Requires<[In64BitMode]>;
127 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
128 // targets. These calls are needed to probe the stack when allocating more than
129 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
130 // ensure that the guard pages used by the OS virtual memory manager are
131 // allocated in correct sequence.
132 // The main point of having separate instruction are extra unmodelled effects
133 // (compared to ordinary calls) like stack pointer change.
135 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
136 def WIN_ALLOCA_32 : I<0, Pseudo, (outs), (ins GR32:$size),
137 "# dynamic stack allocation",
138 [(X86WinAlloca GR32:$size)]>,
141 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
142 def WIN_ALLOCA_64 : I<0, Pseudo, (outs), (ins GR64:$size),
143 "# dynamic stack allocation",
144 [(X86WinAlloca GR64:$size)]>,
145 Requires<[In64BitMode]>;
148 // These instructions XOR the frame pointer into a GPR. They are used in some
149 // stack protection schemes. These are post-RA pseudos because we only know the
150 // frame register after register allocation.
151 let Constraints = "$src = $dst", isPseudo = 1, Defs = [EFLAGS] in {
152 def XOR32_FP : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
153 "xorl\t$$FP, $src", []>,
154 Requires<[NotLP64]>, Sched<[WriteALU]>;
155 def XOR64_FP : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src),
156 "xorq\t$$FP $src", []>,
157 Requires<[In64BitMode]>, Sched<[WriteALU]>;
160 //===----------------------------------------------------------------------===//
161 // EH Pseudo Instructions
163 let SchedRW = [WriteSystem] in {
164 let isTerminator = 1, isReturn = 1, isBarrier = 1,
165 hasCtrlDep = 1, isCodeGenOnly = 1 in {
166 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
167 "ret\t#eh_return, addr: $addr",
168 [(X86ehret GR32:$addr)]>, Sched<[WriteJumpLd]>;
172 let isTerminator = 1, isReturn = 1, isBarrier = 1,
173 hasCtrlDep = 1, isCodeGenOnly = 1 in {
174 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
175 "ret\t#eh_return, addr: $addr",
176 [(X86ehret GR64:$addr)]>, Sched<[WriteJumpLd]>;
180 let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1,
181 isCodeGenOnly = 1, isReturn = 1 in {
182 def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET", [(cleanupret)]>;
184 // CATCHRET needs a custom inserter for SEH.
185 let usesCustomInserter = 1 in
186 def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from),
188 [(catchret bb:$dst, bb:$from)]>;
191 let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1,
192 usesCustomInserter = 1 in
193 def CATCHPAD : I<0, Pseudo, (outs), (ins), "# CATCHPAD", [(catchpad)]>;
195 // This instruction is responsible for re-establishing stack pointers after an
196 // exception has been caught and we are rejoining normal control flow in the
197 // parent function or funclet. It generally sets ESP and EBP, and optionally
198 // ESI. It is only needed for 32-bit WinEH, as the runtime restores CSRs for us
200 let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1 in
201 def EH_RESTORE : I<0, Pseudo, (outs), (ins), "# EH_RESTORE", []>;
203 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
204 usesCustomInserter = 1 in {
205 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
207 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
208 Requires<[Not64BitMode]>;
209 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
211 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
212 Requires<[In64BitMode]>;
213 let isTerminator = 1 in {
214 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
215 "#EH_SJLJ_LONGJMP32",
216 [(X86eh_sjlj_longjmp addr:$buf)]>,
217 Requires<[Not64BitMode]>;
218 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
219 "#EH_SJLJ_LONGJMP64",
220 [(X86eh_sjlj_longjmp addr:$buf)]>,
221 Requires<[In64BitMode]>;
225 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
226 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
227 "#EH_SjLj_Setup\t$dst", []>;
231 //===----------------------------------------------------------------------===//
232 // Pseudo instructions used by unwind info.
234 let isPseudo = 1, SchedRW = [WriteSystem] in {
235 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg),
236 "#SEH_PushReg $reg", []>;
237 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
238 "#SEH_SaveReg $reg, $dst", []>;
239 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
240 "#SEH_SaveXMM $reg, $dst", []>;
241 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size),
242 "#SEH_StackAlloc $size", []>;
243 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset),
244 "#SEH_SetFrame $reg, $offset", []>;
245 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode),
246 "#SEH_PushFrame $mode", []>;
247 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins),
248 "#SEH_EndPrologue", []>;
249 def SEH_Epilogue : I<0, Pseudo, (outs), (ins),
250 "#SEH_Epilogue", []>;
253 //===----------------------------------------------------------------------===//
254 // Pseudo instructions used by segmented stacks.
257 // This is lowered into a RET instruction by MCInstLower. We need
258 // this so that we don't have to have a MachineBasicBlock which ends
259 // with a RET and also has successors.
260 let isPseudo = 1, SchedRW = [WriteJumpLd] in {
261 def MORESTACK_RET: I<0, Pseudo, (outs), (ins), "", []>;
263 // This instruction is lowered to a RET followed by a MOV. The two
264 // instructions are not generated on a higher level since then the
265 // verifier sees a MachineBasicBlock ending with a non-terminator.
266 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), "", []>;
269 //===----------------------------------------------------------------------===//
270 // Alias Instructions
271 //===----------------------------------------------------------------------===//
273 // Alias instruction mapping movr0 to xor.
274 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
275 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
276 isPseudo = 1, AddedComplexity = 10 in
277 def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
278 [(set GR32:$dst, 0)]>, Sched<[WriteZero]>;
280 // Other widths can also make use of the 32-bit xor, which may have a smaller
281 // encoding and avoid partial register updates.
282 let AddedComplexity = 10 in {
283 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
284 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
285 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)>;
288 let Predicates = [OptForSize, Not64BitMode],
289 AddedComplexity = 10 in {
290 let SchedRW = [WriteALU] in {
291 // Pseudo instructions for materializing 1 and -1 using XOR+INC/DEC,
292 // which only require 3 bytes compared to MOV32ri which requires 5.
293 let Defs = [EFLAGS], isReMaterializable = 1, isPseudo = 1 in {
294 def MOV32r1 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
295 [(set GR32:$dst, 1)]>;
296 def MOV32r_1 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
297 [(set GR32:$dst, -1)]>;
301 // MOV16ri is 4 bytes, so the instructions above are smaller.
302 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>;
303 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>;
306 let isReMaterializable = 1, isPseudo = 1, AddedComplexity = 5,
307 SchedRW = [WriteALU] in {
308 // AddedComplexity higher than MOV64ri but lower than MOV32r0 and MOV32r1.
309 def MOV32ImmSExti8 : I<0, Pseudo, (outs GR32:$dst), (ins i32i8imm:$src), "",
310 [(set GR32:$dst, i32immSExt8:$src)]>,
311 Requires<[OptForMinSize, NotWin64WithoutFP]>;
312 def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "",
313 [(set GR64:$dst, i64immSExt8:$src)]>,
314 Requires<[OptForMinSize, NotWin64WithoutFP]>;
317 // Materialize i64 constant where top 32-bits are zero. This could theoretically
318 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
319 // that would make it more difficult to rematerialize.
320 let isReMaterializable = 1, isAsCheapAsAMove = 1,
321 isPseudo = 1, hasSideEffects = 0, SchedRW = [WriteMove] in
322 def MOV32ri64 : I<0, Pseudo, (outs GR32:$dst), (ins i64i32imm:$src), "", []>;
324 // This 64-bit pseudo-move can be used for both a 64-bit constant that is
325 // actually the zero-extension of a 32-bit constant and for labels in the
326 // x86-64 small code model.
327 def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [imm, X86Wrapper]>;
329 let AddedComplexity = 1 in
330 def : Pat<(i64 mov64imm32:$src),
331 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
333 // Use sbb to materialize carry bit.
334 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
335 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
336 // However, Pat<> can't replicate the destination reg into the inputs of the
338 def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "",
339 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
340 def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "",
341 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
342 def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "",
343 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
344 def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "",
345 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
349 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
351 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
353 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
356 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
358 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
360 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
363 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
364 // will be eliminated and that the sbb can be extended up to a wider type. When
365 // this happens, it is great. However, if we are left with an 8-bit sbb and an
366 // and, we might as well just match it as a setb.
367 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
370 // (add OP, SETB) -> (adc OP, 0)
371 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
372 (ADC8ri GR8:$op, 0)>;
373 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
374 (ADC32ri8 GR32:$op, 0)>;
375 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
376 (ADC64ri8 GR64:$op, 0)>;
378 // (sub OP, SETB) -> (sbb OP, 0)
379 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
380 (SBB8ri GR8:$op, 0)>;
381 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
382 (SBB32ri8 GR32:$op, 0)>;
383 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
384 (SBB64ri8 GR64:$op, 0)>;
386 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
387 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
388 (ADC8ri GR8:$op, 0)>;
389 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
390 (ADC32ri8 GR32:$op, 0)>;
391 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
392 (ADC64ri8 GR64:$op, 0)>;
394 //===----------------------------------------------------------------------===//
395 // String Pseudo Instructions
397 let SchedRW = [WriteMicrocoded] in {
398 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
399 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
400 [(X86rep_movs i8)]>, REP,
401 Requires<[Not64BitMode]>;
402 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
403 [(X86rep_movs i16)]>, REP, OpSize16,
404 Requires<[Not64BitMode]>;
405 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
406 [(X86rep_movs i32)]>, REP, OpSize32,
407 Requires<[Not64BitMode]>;
410 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
411 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
412 [(X86rep_movs i8)]>, REP,
413 Requires<[In64BitMode]>;
414 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
415 [(X86rep_movs i16)]>, REP, OpSize16,
416 Requires<[In64BitMode]>;
417 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
418 [(X86rep_movs i32)]>, REP, OpSize32,
419 Requires<[In64BitMode]>;
420 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
421 [(X86rep_movs i64)]>, REP,
422 Requires<[In64BitMode]>;
425 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
426 let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
427 let Uses = [AL,ECX,EDI] in
428 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
429 [(X86rep_stos i8)]>, REP,
430 Requires<[Not64BitMode]>;
431 let Uses = [AX,ECX,EDI] in
432 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
433 [(X86rep_stos i16)]>, REP, OpSize16,
434 Requires<[Not64BitMode]>;
435 let Uses = [EAX,ECX,EDI] in
436 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
437 [(X86rep_stos i32)]>, REP, OpSize32,
438 Requires<[Not64BitMode]>;
441 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
442 let Uses = [AL,RCX,RDI] in
443 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
444 [(X86rep_stos i8)]>, REP,
445 Requires<[In64BitMode]>;
446 let Uses = [AX,RCX,RDI] in
447 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
448 [(X86rep_stos i16)]>, REP, OpSize16,
449 Requires<[In64BitMode]>;
450 let Uses = [RAX,RCX,RDI] in
451 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
452 [(X86rep_stos i32)]>, REP, OpSize32,
453 Requires<[In64BitMode]>;
455 let Uses = [RAX,RCX,RDI] in
456 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
457 [(X86rep_stos i64)]>, REP,
458 Requires<[In64BitMode]>;
462 //===----------------------------------------------------------------------===//
463 // Thread Local Storage Instructions
465 let SchedRW = [WriteSystem] in {
468 // All calls clobber the non-callee saved registers. ESP is marked as
469 // a use to prevent stack-pointer assignments that appear immediately
470 // before calls from potentially appearing dead.
471 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
472 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
473 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
474 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
475 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF],
476 usesCustomInserter = 1, Uses = [ESP, SSP] in {
477 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
479 [(X86tlsaddr tls32addr:$sym)]>,
480 Requires<[Not64BitMode]>;
481 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
483 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
484 Requires<[Not64BitMode]>;
487 // All calls clobber the non-callee saved registers. RSP is marked as
488 // a use to prevent stack-pointer assignments that appear immediately
489 // before calls from potentially appearing dead.
490 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
491 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
492 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
493 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
494 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
495 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF],
496 usesCustomInserter = 1, Uses = [RSP, SSP] in {
497 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
499 [(X86tlsaddr tls64addr:$sym)]>,
500 Requires<[In64BitMode]>;
501 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
503 [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
504 Requires<[In64BitMode]>;
507 // Darwin TLS Support
508 // For i386, the address of the thunk is passed on the stack, on return the
509 // address of the variable is in %eax. %ecx is trashed during the function
510 // call. All other registers are preserved.
511 let Defs = [EAX, ECX, EFLAGS, DF],
513 usesCustomInserter = 1 in
514 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
516 [(X86TLSCall addr:$sym)]>,
517 Requires<[Not64BitMode]>;
519 // For x86_64, the address of the thunk is passed in %rdi, but the
520 // pseudo directly use the symbol, so do not add an implicit use of
521 // %rdi. The lowering will do the right thing with RDI.
522 // On return the address of the variable is in %rax. All other
523 // registers are preserved.
524 let Defs = [RAX, EFLAGS, DF],
526 usesCustomInserter = 1 in
527 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
529 [(X86TLSCall addr:$sym)]>,
530 Requires<[In64BitMode]>;
533 //===----------------------------------------------------------------------===//
534 // Conditional Move Pseudo Instructions
536 // CMOV* - Used to implement the SELECT DAG operation. Expanded after
537 // instruction selection into a branch sequence.
538 multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> {
539 def CMOV#NAME : I<0, Pseudo,
540 (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond),
541 "#CMOV_"#NAME#" PSEUDO!",
542 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, imm:$cond,
546 let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] in {
547 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
548 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
549 // however that requires promoting the operands, and can induce additional
550 // i8 register pressure.
551 defm _GR8 : CMOVrr_PSEUDO<GR8, i8>;
553 let Predicates = [NoCMov] in {
554 defm _GR32 : CMOVrr_PSEUDO<GR32, i32>;
555 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>;
556 } // Predicates = [NoCMov]
558 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
560 let Predicates = [FPStackf32] in
561 defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>;
563 let Predicates = [FPStackf64] in
564 defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>;
566 defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>;
568 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>;
569 defm _FR64 : CMOVrr_PSEUDO<FR64, f64>;
570 defm _F128 : CMOVrr_PSEUDO<VR128, f128>;
571 defm _V4F32 : CMOVrr_PSEUDO<VR128, v4f32>;
572 defm _V2F64 : CMOVrr_PSEUDO<VR128, v2f64>;
573 defm _V2I64 : CMOVrr_PSEUDO<VR128, v2i64>;
574 defm _V8F32 : CMOVrr_PSEUDO<VR256, v8f32>;
575 defm _V4F64 : CMOVrr_PSEUDO<VR256, v4f64>;
576 defm _V4I64 : CMOVrr_PSEUDO<VR256, v4i64>;
577 defm _V8I64 : CMOVrr_PSEUDO<VR512, v8i64>;
578 defm _V8F64 : CMOVrr_PSEUDO<VR512, v8f64>;
579 defm _V16F32 : CMOVrr_PSEUDO<VR512, v16f32>;
580 defm _V8I1 : CMOVrr_PSEUDO<VK8, v8i1>;
581 defm _V16I1 : CMOVrr_PSEUDO<VK16, v16i1>;
582 defm _V32I1 : CMOVrr_PSEUDO<VK32, v32i1>;
583 defm _V64I1 : CMOVrr_PSEUDO<VK64, v64i1>;
584 } // usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS]
586 //===----------------------------------------------------------------------===//
587 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
588 //===----------------------------------------------------------------------===//
590 // FIXME: Use normal instructions and add lock prefix dynamically.
594 // TODO: Get this to fold the constant into the instruction.
595 let isCodeGenOnly = 1, Defs = [EFLAGS] in
596 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
597 "or{l}\t{$zero, $dst|$dst, $zero}", []>,
598 Requires<[Not64BitMode]>, OpSize32, LOCK,
599 Sched<[WriteALULd, WriteRMW]>;
601 let hasSideEffects = 1 in
602 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
604 [(X86MemBarrier)]>, Sched<[WriteLoad]>;
606 // RegOpc corresponds to the mr version of the instruction
607 // ImmOpc corresponds to the mi version of the instruction
608 // ImmOpc8 corresponds to the mi8 version of the instruction
609 // ImmMod corresponds to the instruction format of the mi and mi8 versions
610 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
611 Format ImmMod, SDNode Op, string mnemonic> {
612 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
613 SchedRW = [WriteALULd, WriteRMW] in {
615 def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
616 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
617 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
618 !strconcat(mnemonic, "{b}\t",
619 "{$src2, $dst|$dst, $src2}"),
620 [(set EFLAGS, (Op addr:$dst, GR8:$src2))]>, LOCK;
622 def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
623 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
624 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
625 !strconcat(mnemonic, "{w}\t",
626 "{$src2, $dst|$dst, $src2}"),
627 [(set EFLAGS, (Op addr:$dst, GR16:$src2))]>,
630 def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
631 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
632 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
633 !strconcat(mnemonic, "{l}\t",
634 "{$src2, $dst|$dst, $src2}"),
635 [(set EFLAGS, (Op addr:$dst, GR32:$src2))]>,
638 def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
639 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
640 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
641 !strconcat(mnemonic, "{q}\t",
642 "{$src2, $dst|$dst, $src2}"),
643 [(set EFLAGS, (Op addr:$dst, GR64:$src2))]>, LOCK;
645 def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
646 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
647 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
648 !strconcat(mnemonic, "{b}\t",
649 "{$src2, $dst|$dst, $src2}"),
650 [(set EFLAGS, (Op addr:$dst, (i8 imm:$src2)))]>, LOCK;
652 def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
653 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
654 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
655 !strconcat(mnemonic, "{w}\t",
656 "{$src2, $dst|$dst, $src2}"),
657 [(set EFLAGS, (Op addr:$dst, (i16 imm:$src2)))]>,
660 def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
661 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
662 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
663 !strconcat(mnemonic, "{l}\t",
664 "{$src2, $dst|$dst, $src2}"),
665 [(set EFLAGS, (Op addr:$dst, (i32 imm:$src2)))]>,
668 def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
669 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
670 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
671 !strconcat(mnemonic, "{q}\t",
672 "{$src2, $dst|$dst, $src2}"),
673 [(set EFLAGS, (Op addr:$dst, i64immSExt32:$src2))]>,
676 def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
677 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
678 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
679 !strconcat(mnemonic, "{w}\t",
680 "{$src2, $dst|$dst, $src2}"),
681 [(set EFLAGS, (Op addr:$dst, i16immSExt8:$src2))]>,
684 def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
685 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
686 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
687 !strconcat(mnemonic, "{l}\t",
688 "{$src2, $dst|$dst, $src2}"),
689 [(set EFLAGS, (Op addr:$dst, i32immSExt8:$src2))]>,
692 def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
693 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
694 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
695 !strconcat(mnemonic, "{q}\t",
696 "{$src2, $dst|$dst, $src2}"),
697 [(set EFLAGS, (Op addr:$dst, i64immSExt8:$src2))]>,
703 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, X86lock_add, "add">;
704 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, X86lock_sub, "sub">;
705 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, X86lock_or , "or">;
706 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, X86lock_and, "and">;
707 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, X86lock_xor, "xor">;
709 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
710 string frag, string mnemonic> {
711 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
712 SchedRW = [WriteALULd, WriteRMW] in {
713 def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
714 !strconcat(mnemonic, "{b}\t$dst"),
715 [(set EFLAGS, (!cast<PatFrag>(frag # "_8") addr:$dst))]>,
717 def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
718 !strconcat(mnemonic, "{w}\t$dst"),
719 [(set EFLAGS, (!cast<PatFrag>(frag # "_16") addr:$dst))]>,
721 def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
722 !strconcat(mnemonic, "{l}\t$dst"),
723 [(set EFLAGS, (!cast<PatFrag>(frag # "_32") addr:$dst))]>,
725 def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
726 !strconcat(mnemonic, "{q}\t$dst"),
727 [(set EFLAGS, (!cast<PatFrag>(frag # "_64") addr:$dst))]>,
732 multiclass unary_atomic_intrin<SDNode atomic_op> {
733 def _8 : PatFrag<(ops node:$ptr),
734 (atomic_op node:$ptr), [{
735 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
737 def _16 : PatFrag<(ops node:$ptr),
738 (atomic_op node:$ptr), [{
739 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
741 def _32 : PatFrag<(ops node:$ptr),
742 (atomic_op node:$ptr), [{
743 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
745 def _64 : PatFrag<(ops node:$ptr),
746 (atomic_op node:$ptr), [{
747 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
751 defm X86lock_inc : unary_atomic_intrin<X86lock_inc>;
752 defm X86lock_dec : unary_atomic_intrin<X86lock_dec>;
754 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "X86lock_inc", "inc">;
755 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "X86lock_dec", "dec">;
757 // Atomic compare and swap.
758 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
759 SDPatternOperator frag, X86MemOperand x86memop> {
760 let isCodeGenOnly = 1, usesCustomInserter = 1 in {
761 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr),
762 !strconcat(mnemonic, "\t$ptr"),
763 [(frag addr:$ptr)]>, TB, LOCK;
767 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
768 string mnemonic, SDPatternOperator frag> {
769 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
770 let Defs = [AL, EFLAGS], Uses = [AL] in
771 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
772 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
773 [(frag addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
774 let Defs = [AX, EFLAGS], Uses = [AX] in
775 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
776 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
777 [(frag addr:$ptr, GR16:$swap, 2)]>, TB, OpSize16, LOCK;
778 let Defs = [EAX, EFLAGS], Uses = [EAX] in
779 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
780 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
781 [(frag addr:$ptr, GR32:$swap, 4)]>, TB, OpSize32, LOCK;
782 let Defs = [RAX, EFLAGS], Uses = [RAX] in
783 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
784 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
785 [(frag addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
789 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
790 SchedRW = [WriteALULd, WriteRMW] in {
791 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", X86cas8, i64mem>;
794 // This pseudo must be used when the frame uses RBX as
795 // the base pointer. Indeed, in such situation RBX is a reserved
796 // register and the register allocator will ignore any use/def of
797 // it. In other words, the register will not fix the clobbering of
798 // RBX that will happen when setting the arguments for the instrucion.
800 // Unlike the actual related instuction, we mark that this one
801 // defines EBX (instead of using EBX).
802 // The rationale is that we will define RBX during the expansion of
803 // the pseudo. The argument feeding EBX is ebx_input.
805 // The additional argument, $ebx_save, is a temporary register used to
806 // save the value of RBX across the actual instruction.
808 // To make sure the register assigned to $ebx_save does not interfere with
809 // the definition of the actual instruction, we use a definition $dst which
810 // is tied to $rbx_save. That way, the live-range of $rbx_save spans across
811 // the instruction and we are sure we will have a valid register to restore
813 let Defs = [EAX, EDX, EBX, EFLAGS], Uses = [EAX, ECX, EDX],
814 SchedRW = [WriteALULd, WriteRMW], isCodeGenOnly = 1, isPseudo = 1,
815 Constraints = "$ebx_save = $dst", usesCustomInserter = 1 in {
816 def LCMPXCHG8B_SAVE_EBX :
817 I<0, Pseudo, (outs GR32:$dst),
818 (ins i64mem:$ptr, GR32:$ebx_input, GR32:$ebx_save),
819 !strconcat("cmpxchg8b", "\t$ptr"),
820 [(set GR32:$dst, (X86cas8save_ebx addr:$ptr, GR32:$ebx_input,
825 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
826 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
827 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
828 X86cas16, i128mem>, REX_W;
831 // Same as LCMPXCHG8B_SAVE_RBX but for the 16 Bytes variant.
832 let Defs = [RAX, RDX, RBX, EFLAGS], Uses = [RAX, RCX, RDX],
833 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW],
834 isCodeGenOnly = 1, isPseudo = 1, Constraints = "$rbx_save = $dst",
835 usesCustomInserter = 1 in {
836 def LCMPXCHG16B_SAVE_RBX :
837 I<0, Pseudo, (outs GR64:$dst),
838 (ins i128mem:$ptr, GR64:$rbx_input, GR64:$rbx_save),
839 !strconcat("cmpxchg16b", "\t$ptr"),
840 [(set GR64:$dst, (X86cas16save_rbx addr:$ptr, GR64:$rbx_input,
844 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", X86cas>;
846 // Atomic exchange and add
847 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
849 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1,
850 SchedRW = [WriteALULd, WriteRMW] in {
851 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
852 (ins GR8:$val, i8mem:$ptr),
853 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
855 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))]>;
856 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
857 (ins GR16:$val, i16mem:$ptr),
858 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
861 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))]>,
863 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
864 (ins GR32:$val, i32mem:$ptr),
865 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
868 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))]>,
870 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
871 (ins GR64:$val, i64mem:$ptr),
872 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
875 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))]>;
879 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add">, TB, LOCK;
881 /* The following multiclass tries to make sure that in code like
882 * x.store (immediate op x.load(acquire), release)
884 * x.store (register op x.load(acquire), release)
885 * an operation directly on memory is generated instead of wasting a register.
886 * It is not automatic as atomic_store/load are only lowered to MOV instructions
887 * extremely late to prevent them from being accidentally reordered in the backend
888 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions)
890 multiclass RELEASE_BINOP_MI<SDNode op> {
891 def NAME#8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
892 "#BINOP "#NAME#"8mi PSEUDO!",
893 [(atomic_store_8 addr:$dst, (op
894 (atomic_load_8 addr:$dst), (i8 imm:$src)))]>;
895 def NAME#8mr : I<0, Pseudo, (outs), (ins i8mem:$dst, GR8:$src),
896 "#BINOP "#NAME#"8mr PSEUDO!",
897 [(atomic_store_8 addr:$dst, (op
898 (atomic_load_8 addr:$dst), GR8:$src))]>;
899 // NAME#16 is not generated as 16-bit arithmetic instructions are considered
900 // costly and avoided as far as possible by this backend anyway
901 def NAME#32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
902 "#BINOP "#NAME#"32mi PSEUDO!",
903 [(atomic_store_32 addr:$dst, (op
904 (atomic_load_32 addr:$dst), (i32 imm:$src)))]>;
905 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
906 "#BINOP "#NAME#"32mr PSEUDO!",
907 [(atomic_store_32 addr:$dst, (op
908 (atomic_load_32 addr:$dst), GR32:$src))]>;
909 def NAME#64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
910 "#BINOP "#NAME#"64mi32 PSEUDO!",
911 [(atomic_store_64 addr:$dst, (op
912 (atomic_load_64 addr:$dst), (i64immSExt32:$src)))]>;
913 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
914 "#BINOP "#NAME#"64mr PSEUDO!",
915 [(atomic_store_64 addr:$dst, (op
916 (atomic_load_64 addr:$dst), GR64:$src))]>;
918 let Defs = [EFLAGS], SchedRW = [WriteMicrocoded] in {
919 defm RELEASE_ADD : RELEASE_BINOP_MI<add>;
920 defm RELEASE_AND : RELEASE_BINOP_MI<and>;
921 defm RELEASE_OR : RELEASE_BINOP_MI<or>;
922 defm RELEASE_XOR : RELEASE_BINOP_MI<xor>;
923 // Note: we don't deal with sub, because substractions of constants are
924 // optimized into additions before this code can run.
927 // Same as above, but for floating-point.
928 // FIXME: imm version.
929 // FIXME: Version that doesn't clobber $src, using AVX's VADDSS.
930 // FIXME: This could also handle SIMD operations with *ps and *pd instructions.
931 let usesCustomInserter = 1, SchedRW = [WriteMicrocoded] in {
932 multiclass RELEASE_FP_BINOP_MI<SDNode op> {
933 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, FR32:$src),
934 "#BINOP "#NAME#"32mr PSEUDO!",
935 [(atomic_store_32 addr:$dst,
937 (f32 (bitconvert (i32 (atomic_load_32 addr:$dst)))),
938 FR32:$src))))]>, Requires<[HasSSE1]>;
939 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, FR64:$src),
940 "#BINOP "#NAME#"64mr PSEUDO!",
941 [(atomic_store_64 addr:$dst,
943 (f64 (bitconvert (i64 (atomic_load_64 addr:$dst)))),
944 FR64:$src))))]>, Requires<[HasSSE2]>;
946 defm RELEASE_FADD : RELEASE_FP_BINOP_MI<fadd>;
947 // FIXME: Add fsub, fmul, fdiv, ...
950 multiclass RELEASE_UNOP<dag dag8, dag dag16, dag dag32, dag dag64> {
951 def NAME#8m : I<0, Pseudo, (outs), (ins i8mem:$dst),
952 "#UNOP "#NAME#"8m PSEUDO!",
953 [(atomic_store_8 addr:$dst, dag8)]>;
954 def NAME#16m : I<0, Pseudo, (outs), (ins i16mem:$dst),
955 "#UNOP "#NAME#"16m PSEUDO!",
956 [(atomic_store_16 addr:$dst, dag16)]>;
957 def NAME#32m : I<0, Pseudo, (outs), (ins i32mem:$dst),
958 "#UNOP "#NAME#"32m PSEUDO!",
959 [(atomic_store_32 addr:$dst, dag32)]>;
960 def NAME#64m : I<0, Pseudo, (outs), (ins i64mem:$dst),
961 "#UNOP "#NAME#"64m PSEUDO!",
962 [(atomic_store_64 addr:$dst, dag64)]>;
965 let Defs = [EFLAGS], Predicates = [UseIncDec], SchedRW = [WriteMicrocoded] in {
966 defm RELEASE_INC : RELEASE_UNOP<
967 (add (atomic_load_8 addr:$dst), (i8 1)),
968 (add (atomic_load_16 addr:$dst), (i16 1)),
969 (add (atomic_load_32 addr:$dst), (i32 1)),
970 (add (atomic_load_64 addr:$dst), (i64 1))>;
971 defm RELEASE_DEC : RELEASE_UNOP<
972 (add (atomic_load_8 addr:$dst), (i8 -1)),
973 (add (atomic_load_16 addr:$dst), (i16 -1)),
974 (add (atomic_load_32 addr:$dst), (i32 -1)),
975 (add (atomic_load_64 addr:$dst), (i64 -1))>;
978 TODO: These don't work because the type inference of TableGen fails.
979 TODO: find a way to fix it.
980 let Defs = [EFLAGS] in {
981 defm RELEASE_NEG : RELEASE_UNOP<
982 (ineg (atomic_load_8 addr:$dst)),
983 (ineg (atomic_load_16 addr:$dst)),
984 (ineg (atomic_load_32 addr:$dst)),
985 (ineg (atomic_load_64 addr:$dst))>;
987 // NOT doesn't set flags.
988 defm RELEASE_NOT : RELEASE_UNOP<
989 (not (atomic_load_8 addr:$dst)),
990 (not (atomic_load_16 addr:$dst)),
991 (not (atomic_load_32 addr:$dst)),
992 (not (atomic_load_64 addr:$dst))>;
995 let SchedRW = [WriteMicrocoded] in {
996 def RELEASE_MOV8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
997 "#RELEASE_MOV8mi PSEUDO!",
998 [(atomic_store_8 addr:$dst, (i8 imm:$src))]>;
999 def RELEASE_MOV16mi : I<0, Pseudo, (outs), (ins i16mem:$dst, i16imm:$src),
1000 "#RELEASE_MOV16mi PSEUDO!",
1001 [(atomic_store_16 addr:$dst, (i16 imm:$src))]>;
1002 def RELEASE_MOV32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
1003 "#RELEASE_MOV32mi PSEUDO!",
1004 [(atomic_store_32 addr:$dst, (i32 imm:$src))]>;
1005 def RELEASE_MOV64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
1006 "#RELEASE_MOV64mi32 PSEUDO!",
1007 [(atomic_store_64 addr:$dst, i64immSExt32:$src)]>;
1009 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
1010 "#RELEASE_MOV8mr PSEUDO!",
1011 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
1012 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
1013 "#RELEASE_MOV16mr PSEUDO!",
1014 [(atomic_store_16 addr:$dst, GR16:$src)]>;
1015 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
1016 "#RELEASE_MOV32mr PSEUDO!",
1017 [(atomic_store_32 addr:$dst, GR32:$src)]>;
1018 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
1019 "#RELEASE_MOV64mr PSEUDO!",
1020 [(atomic_store_64 addr:$dst, GR64:$src)]>;
1022 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
1023 "#ACQUIRE_MOV8rm PSEUDO!",
1024 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
1025 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
1026 "#ACQUIRE_MOV16rm PSEUDO!",
1027 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
1028 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
1029 "#ACQUIRE_MOV32rm PSEUDO!",
1030 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
1031 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
1032 "#ACQUIRE_MOV64rm PSEUDO!",
1033 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
1036 //===----------------------------------------------------------------------===//
1037 // DAG Pattern Matching Rules
1038 //===----------------------------------------------------------------------===//
1040 // Use AND/OR to store 0/-1 in memory when optimizing for minsize. This saves
1041 // binary size compared to a regular MOV, but it introduces an unnecessary
1042 // load, so is not suitable for regular or optsize functions.
1043 let Predicates = [OptForMinSize] in {
1044 def : Pat<(store (i16 0), addr:$dst), (AND16mi8 addr:$dst, 0)>;
1045 def : Pat<(store (i32 0), addr:$dst), (AND32mi8 addr:$dst, 0)>;
1046 def : Pat<(store (i64 0), addr:$dst), (AND64mi8 addr:$dst, 0)>;
1047 def : Pat<(store (i16 -1), addr:$dst), (OR16mi8 addr:$dst, -1)>;
1048 def : Pat<(store (i32 -1), addr:$dst), (OR32mi8 addr:$dst, -1)>;
1049 def : Pat<(store (i64 -1), addr:$dst), (OR64mi8 addr:$dst, -1)>;
1052 // In kernel code model, we can get the address of a label
1053 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
1054 // the MOV64ri32 should accept these.
1055 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1056 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
1057 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1058 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
1059 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1060 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1061 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1062 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1063 def : Pat<(i64 (X86Wrapper mcsym:$dst)),
1064 (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>;
1065 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1066 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
1068 // If we have small model and -static mode, it is safe to store global addresses
1069 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1070 // for MOV64mi32 should handle this sort of thing.
1071 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1072 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1073 Requires<[NearData, IsNotPIC]>;
1074 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1075 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1076 Requires<[NearData, IsNotPIC]>;
1077 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1078 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1079 Requires<[NearData, IsNotPIC]>;
1080 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1081 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1082 Requires<[NearData, IsNotPIC]>;
1083 def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst),
1084 (MOV64mi32 addr:$dst, mcsym:$src)>,
1085 Requires<[NearData, IsNotPIC]>;
1086 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
1087 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
1088 Requires<[NearData, IsNotPIC]>;
1090 def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>;
1091 def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>;
1095 // tls has some funny stuff here...
1096 // This corresponds to movabs $foo@tpoff, %rax
1097 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
1098 (MOV64ri32 tglobaltlsaddr :$dst)>;
1099 // This corresponds to add $foo@tpoff, %rax
1100 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
1101 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
1104 // Direct PC relative function call for small code model. 32-bit displacement
1105 // sign extended to 64-bit.
1106 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1107 (CALL64pcrel32 tglobaladdr:$dst)>;
1108 def : Pat<(X86call (i64 texternalsym:$dst)),
1109 (CALL64pcrel32 texternalsym:$dst)>;
1111 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
1112 // can never use callee-saved registers. That is the purpose of the GR64_TC
1113 // register classes.
1115 // The only volatile register that is never used by the calling convention is
1116 // %r11. This happens when calling a vararg function with 6 arguments.
1118 // Match an X86tcret that uses less than 7 volatile registers.
1119 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
1120 (X86tcret node:$ptr, node:$off), [{
1121 // X86tcret args: (*chain, ptr, imm, regs..., glue)
1122 unsigned NumRegs = 0;
1123 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
1124 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
1129 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1130 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
1131 Requires<[Not64BitMode, NotUseRetpoline]>;
1133 // FIXME: This is disabled for 32-bit PIC mode because the global base
1134 // register which is part of the address mode may be assigned a
1135 // callee-saved register.
1136 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1137 (TCRETURNmi addr:$dst, imm:$off)>,
1138 Requires<[Not64BitMode, IsNotPIC, NotUseRetpoline]>;
1140 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
1141 (TCRETURNdi tglobaladdr:$dst, imm:$off)>,
1142 Requires<[NotLP64]>;
1144 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
1145 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1146 Requires<[NotLP64]>;
1148 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1149 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
1150 Requires<[In64BitMode, NotUseRetpoline]>;
1152 // Don't fold loads into X86tcret requiring more than 6 regs.
1153 // There wouldn't be enough scratch registers for base+index.
1154 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
1155 (TCRETURNmi64 addr:$dst, imm:$off)>,
1156 Requires<[In64BitMode, NotUseRetpoline]>;
1158 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1159 (RETPOLINE_TCRETURN64 ptr_rc_tailcall:$dst, imm:$off)>,
1160 Requires<[In64BitMode, UseRetpoline]>;
1162 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1163 (RETPOLINE_TCRETURN32 ptr_rc_tailcall:$dst, imm:$off)>,
1164 Requires<[Not64BitMode, UseRetpoline]>;
1166 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1167 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1170 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1171 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1174 // Normal calls, with various flavors of addresses.
1175 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1176 (CALLpcrel32 tglobaladdr:$dst)>;
1177 def : Pat<(X86call (i32 texternalsym:$dst)),
1178 (CALLpcrel32 texternalsym:$dst)>;
1179 def : Pat<(X86call (i32 imm:$dst)),
1180 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1184 // TEST R,R is smaller than CMP R,0
1185 def : Pat<(X86cmp GR8:$src1, 0),
1186 (TEST8rr GR8:$src1, GR8:$src1)>;
1187 def : Pat<(X86cmp GR16:$src1, 0),
1188 (TEST16rr GR16:$src1, GR16:$src1)>;
1189 def : Pat<(X86cmp GR32:$src1, 0),
1190 (TEST32rr GR32:$src1, GR32:$src1)>;
1191 def : Pat<(X86cmp GR64:$src1, 0),
1192 (TEST64rr GR64:$src1, GR64:$src1)>;
1194 // Conditional moves with folded loads with operands swapped and conditions
1196 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1197 Instruction Inst64> {
1198 let Predicates = [HasCMov] in {
1199 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1200 (Inst16 GR16:$src2, addr:$src1)>;
1201 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1202 (Inst32 GR32:$src2, addr:$src1)>;
1203 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1204 (Inst64 GR64:$src2, addr:$src1)>;
1208 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1209 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1210 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1211 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1212 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1213 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1214 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1215 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1216 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1217 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1218 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1219 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1220 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1221 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1222 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1223 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1225 // zextload bool -> zextload byte
1226 // i1 stored in one byte in zero-extended form.
1227 // Upper bits cleanup should be executed before Store.
1228 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1229 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1230 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1231 def : Pat<(zextloadi64i1 addr:$src),
1232 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1234 // extload bool -> extload byte
1235 // When extloading from 16-bit and smaller memory locations into 64-bit
1236 // registers, use zero-extending loads so that the entire 64-bit register is
1237 // defined, avoiding partial-register updates.
1239 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1240 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1241 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1242 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1243 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1244 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1246 // For other extloads, use subregs, since the high contents of the register are
1247 // defined after an extload.
1248 def : Pat<(extloadi64i1 addr:$src),
1249 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1250 def : Pat<(extloadi64i8 addr:$src),
1251 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1252 def : Pat<(extloadi64i16 addr:$src),
1253 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1254 def : Pat<(extloadi64i32 addr:$src),
1255 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1257 // anyext. Define these to do an explicit zero-extend to
1258 // avoid partial-register updates.
1259 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1260 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1261 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1263 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1264 def : Pat<(i32 (anyext GR16:$src)),
1265 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1267 def : Pat<(i64 (anyext GR8 :$src)),
1268 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1269 def : Pat<(i64 (anyext GR16:$src)),
1270 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
1271 def : Pat<(i64 (anyext GR32:$src)),
1272 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, sub_32bit)>;
1275 // Any instruction that defines a 32-bit result leaves the high half of the
1276 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1277 // be copying from a truncate. Any other 32-bit operation will zero-extend
1278 // up to 64 bits. AssertSext/AssertZext aren't saying anything about the upper
1279 // 32 bits, they're probably just qualifying a CopyFromReg.
1280 def def32 : PatLeaf<(i32 GR32:$src), [{
1281 return N->getOpcode() != ISD::TRUNCATE &&
1282 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1283 N->getOpcode() != ISD::CopyFromReg &&
1284 N->getOpcode() != ISD::AssertSext &&
1285 N->getOpcode() != ISD::AssertZext;
1288 // In the case of a 32-bit def that is known to implicitly zero-extend,
1289 // we can use a SUBREG_TO_REG.
1290 def : Pat<(i64 (zext def32:$src)),
1291 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1293 //===----------------------------------------------------------------------===//
1294 // Pattern match OR as ADD
1295 //===----------------------------------------------------------------------===//
1297 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1298 // 3-addressified into an LEA instruction to avoid copies. However, we also
1299 // want to finally emit these instructions as an or at the end of the code
1300 // generator to make the generated code easier to read. To do this, we select
1301 // into "disjoint bits" pseudo ops.
1303 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1304 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1305 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1306 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1309 CurDAG->computeKnownBits(N->getOperand(0), Known0, 0);
1311 CurDAG->computeKnownBits(N->getOperand(1), Known1, 0);
1312 return (~Known0.Zero & ~Known1.Zero) == 0;
1316 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1317 // Try this before the selecting to OR.
1318 let AddedComplexity = 5, SchedRW = [WriteALU] in {
1320 let isConvertibleToThreeAddress = 1,
1321 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1322 let isCommutable = 1 in {
1323 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1324 "", // orw/addw REG, REG
1325 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1326 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1327 "", // orl/addl REG, REG
1328 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1329 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1330 "", // orq/addq REG, REG
1331 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1334 // NOTE: These are order specific, we want the ri8 forms to be listed
1335 // first so that they are slightly preferred to the ri forms.
1337 def ADD16ri8_DB : I<0, Pseudo,
1338 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1339 "", // orw/addw REG, imm8
1340 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1341 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1342 "", // orw/addw REG, imm
1343 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1345 def ADD32ri8_DB : I<0, Pseudo,
1346 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1347 "", // orl/addl REG, imm8
1348 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1349 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1350 "", // orl/addl REG, imm
1351 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1354 def ADD64ri8_DB : I<0, Pseudo,
1355 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1356 "", // orq/addq REG, imm8
1357 [(set GR64:$dst, (or_is_add GR64:$src1,
1358 i64immSExt8:$src2))]>;
1359 def ADD64ri32_DB : I<0, Pseudo,
1360 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1361 "", // orq/addq REG, imm
1362 [(set GR64:$dst, (or_is_add GR64:$src1,
1363 i64immSExt32:$src2))]>;
1365 } // AddedComplexity, SchedRW
1367 //===----------------------------------------------------------------------===//
1368 // Pattern match SUB as XOR
1369 //===----------------------------------------------------------------------===//
1371 // An immediate in the LHS of a subtract can't be encoded in the instruction.
1372 // If there is no possibility of a borrow we can use an XOR instead of a SUB
1373 // to enable the immediate to be folded.
1374 // TODO: Move this to a DAG combine?
1376 def sub_is_xor : PatFrag<(ops node:$lhs, node:$rhs), (sub node:$lhs, node:$rhs),[{
1377 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
1379 CurDAG->computeKnownBits(N->getOperand(1), Known);
1381 // If all possible ones in the RHS are set in the LHS then there can't be
1382 // a borrow and we can use xor.
1383 return (~Known.Zero).isSubsetOf(CN->getAPIntValue());
1389 let AddedComplexity = 5 in {
1390 def : Pat<(sub_is_xor imm:$src2, GR8:$src1),
1391 (XOR8ri GR8:$src1, imm:$src2)>;
1392 def : Pat<(sub_is_xor i16immSExt8:$src2, GR16:$src1),
1393 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1394 def : Pat<(sub_is_xor imm:$src2, GR16:$src1),
1395 (XOR16ri GR16:$src1, imm:$src2)>;
1396 def : Pat<(sub_is_xor i32immSExt8:$src2, GR32:$src1),
1397 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1398 def : Pat<(sub_is_xor imm:$src2, GR32:$src1),
1399 (XOR32ri GR32:$src1, imm:$src2)>;
1400 def : Pat<(sub_is_xor i64immSExt8:$src2, GR64:$src1),
1401 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1402 def : Pat<(sub_is_xor i64immSExt32:$src2, GR64:$src1),
1403 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1406 //===----------------------------------------------------------------------===//
1408 //===----------------------------------------------------------------------===//
1410 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1411 // +128 doesn't, so in this special case use a sub instead of an add.
1412 def : Pat<(add GR16:$src1, 128),
1413 (SUB16ri8 GR16:$src1, -128)>;
1414 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1415 (SUB16mi8 addr:$dst, -128)>;
1417 def : Pat<(add GR32:$src1, 128),
1418 (SUB32ri8 GR32:$src1, -128)>;
1419 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1420 (SUB32mi8 addr:$dst, -128)>;
1422 def : Pat<(add GR64:$src1, 128),
1423 (SUB64ri8 GR64:$src1, -128)>;
1424 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1425 (SUB64mi8 addr:$dst, -128)>;
1427 // The same trick applies for 32-bit immediate fields in 64-bit
1429 def : Pat<(add GR64:$src1, 0x0000000080000000),
1430 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1431 def : Pat<(store (add (loadi64 addr:$dst), 0x0000000080000000), addr:$dst),
1432 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1434 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1435 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1436 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1437 // represented with a sign extension of a 8 bit constant, use that.
1438 // This can also reduce instruction size by eliminating the need for the REX
1441 // AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32.
1442 let AddedComplexity = 1 in {
1443 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1447 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1448 (i32 (GetLo8XForm imm:$imm))),
1451 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1455 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1456 (i32 (GetLo32XForm imm:$imm))),
1458 } // AddedComplexity = 1
1461 // AddedComplexity is needed due to the increased complexity on the
1462 // i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all
1463 // the MOVZX patterns keeps thems together in DAGIsel tables.
1464 let AddedComplexity = 1 in {
1465 // r & (2^16-1) ==> movz
1466 def : Pat<(and GR32:$src1, 0xffff),
1467 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1468 // r & (2^8-1) ==> movz
1469 def : Pat<(and GR32:$src1, 0xff),
1470 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>;
1471 // r & (2^8-1) ==> movz
1472 def : Pat<(and GR16:$src1, 0xff),
1473 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)),
1476 // r & (2^32-1) ==> movz
1477 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1478 (SUBREG_TO_REG (i64 0),
1479 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)),
1481 // r & (2^16-1) ==> movz
1482 def : Pat<(and GR64:$src, 0xffff),
1483 (SUBREG_TO_REG (i64 0),
1484 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))),
1486 // r & (2^8-1) ==> movz
1487 def : Pat<(and GR64:$src, 0xff),
1488 (SUBREG_TO_REG (i64 0),
1489 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))),
1491 } // AddedComplexity = 1
1494 // Try to use BTS/BTR/BTC for single bit operations on the upper 32-bits.
1496 def BTRXForm : SDNodeXForm<imm, [{
1497 // Transformation function: Find the lowest 0.
1498 return getI64Imm((uint8_t)N->getAPIntValue().countTrailingOnes(), SDLoc(N));
1501 def BTCBTSXForm : SDNodeXForm<imm, [{
1502 // Transformation function: Find the lowest 1.
1503 return getI64Imm((uint8_t)N->getAPIntValue().countTrailingZeros(), SDLoc(N));
1506 def BTRMask64 : ImmLeaf<i64, [{
1507 return !isUInt<32>(Imm) && !isInt<32>(Imm) && isPowerOf2_64(~Imm);
1510 def BTCBTSMask64 : ImmLeaf<i64, [{
1511 return !isInt<32>(Imm) && isPowerOf2_64(Imm);
1514 // For now only do this for optsize.
1515 let AddedComplexity = 1, Predicates=[OptForSize] in {
1516 def : Pat<(and GR64:$src1, BTRMask64:$mask),
1517 (BTR64ri8 GR64:$src1, (BTRXForm imm:$mask))>;
1518 def : Pat<(or GR64:$src1, BTCBTSMask64:$mask),
1519 (BTS64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>;
1520 def : Pat<(xor GR64:$src1, BTCBTSMask64:$mask),
1521 (BTC64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>;
1525 // sext_inreg patterns
1526 def : Pat<(sext_inreg GR32:$src, i16),
1527 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1528 def : Pat<(sext_inreg GR32:$src, i8),
1529 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>;
1531 def : Pat<(sext_inreg GR16:$src, i8),
1532 (EXTRACT_SUBREG (MOVSX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit)),
1535 def : Pat<(sext_inreg GR64:$src, i32),
1536 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1537 def : Pat<(sext_inreg GR64:$src, i16),
1538 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1539 def : Pat<(sext_inreg GR64:$src, i8),
1540 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1542 // sext, sext_load, zext, zext_load
1543 def: Pat<(i16 (sext GR8:$src)),
1544 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1545 def: Pat<(sextloadi16i8 addr:$src),
1546 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1547 def: Pat<(i16 (zext GR8:$src)),
1548 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1549 def: Pat<(zextloadi16i8 addr:$src),
1550 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1553 def : Pat<(i16 (trunc GR32:$src)),
1554 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1555 def : Pat<(i8 (trunc GR32:$src)),
1556 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1558 Requires<[Not64BitMode]>;
1559 def : Pat<(i8 (trunc GR16:$src)),
1560 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1562 Requires<[Not64BitMode]>;
1563 def : Pat<(i32 (trunc GR64:$src)),
1564 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1565 def : Pat<(i16 (trunc GR64:$src)),
1566 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1567 def : Pat<(i8 (trunc GR64:$src)),
1568 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1569 def : Pat<(i8 (trunc GR32:$src)),
1570 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1571 Requires<[In64BitMode]>;
1572 def : Pat<(i8 (trunc GR16:$src)),
1573 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1574 Requires<[In64BitMode]>;
1576 def immff00_ffff : ImmLeaf<i32, [{
1577 return Imm >= 0xff00 && Imm <= 0xffff;
1580 // h-register tricks
1581 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1582 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>,
1583 Requires<[Not64BitMode]>;
1584 def : Pat<(i8 (trunc (srl_su (i32 (anyext GR16:$src)), (i8 8)))),
1585 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>,
1586 Requires<[Not64BitMode]>;
1587 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1588 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi)>,
1589 Requires<[Not64BitMode]>;
1590 def : Pat<(srl GR16:$src, (i8 8)),
1592 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)),
1594 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1595 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>;
1596 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1597 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>;
1598 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1599 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>;
1600 def : Pat<(srl (and_su GR32:$src, immff00_ffff), (i8 8)),
1601 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>;
1603 // h-register tricks.
1604 // For now, be conservative on x86-64 and use an h-register extract only if the
1605 // value is immediately zero-extended or stored, which are somewhat common
1606 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1607 // from being allocated in the same instruction as the h register, as there's
1608 // currently no way to describe this requirement to the register allocator.
1610 // h-register extract and zero-extend.
1611 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1615 (EXTRACT_SUBREG GR64:$src, sub_8bit_hi)),
1617 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1621 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)),
1623 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1627 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)),
1630 // h-register extract and store.
1631 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1634 (EXTRACT_SUBREG GR64:$src, sub_8bit_hi))>;
1635 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1638 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>,
1639 Requires<[In64BitMode]>;
1640 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1643 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>,
1644 Requires<[In64BitMode]>;
1647 // (shl x, 1) ==> (add x, x)
1648 // Note that if x is undef (immediate or otherwise), we could theoretically
1649 // end up with the two uses of x getting different values, producing a result
1650 // where the least significant bit is not 0. However, the probability of this
1651 // happening is considered low enough that this is officially not a
1653 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1654 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1655 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1656 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1658 // Helper imms to check if a mask doesn't change significant shift/rotate bits.
1659 def immShift8 : ImmLeaf<i8, [{
1660 return countTrailingOnes<uint64_t>(Imm) >= 3;
1662 def immShift16 : ImmLeaf<i8, [{
1663 return countTrailingOnes<uint64_t>(Imm) >= 4;
1665 def immShift32 : ImmLeaf<i8, [{
1666 return countTrailingOnes<uint64_t>(Imm) >= 5;
1668 def immShift64 : ImmLeaf<i8, [{
1669 return countTrailingOnes<uint64_t>(Imm) >= 6;
1672 // Shift amount is implicitly masked.
1673 multiclass MaskedShiftAmountPats<SDNode frag, string name> {
1674 // (shift x (and y, 31)) ==> (shift x, y)
1675 def : Pat<(frag GR8:$src1, (and CL, immShift32)),
1676 (!cast<Instruction>(name # "8rCL") GR8:$src1)>;
1677 def : Pat<(frag GR16:$src1, (and CL, immShift32)),
1678 (!cast<Instruction>(name # "16rCL") GR16:$src1)>;
1679 def : Pat<(frag GR32:$src1, (and CL, immShift32)),
1680 (!cast<Instruction>(name # "32rCL") GR32:$src1)>;
1681 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1682 (!cast<Instruction>(name # "8mCL") addr:$dst)>;
1683 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1684 (!cast<Instruction>(name # "16mCL") addr:$dst)>;
1685 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1686 (!cast<Instruction>(name # "32mCL") addr:$dst)>;
1688 // (shift x (and y, 63)) ==> (shift x, y)
1689 def : Pat<(frag GR64:$src1, (and CL, immShift64)),
1690 (!cast<Instruction>(name # "64rCL") GR64:$src1)>;
1691 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, immShift64)), addr:$dst),
1692 (!cast<Instruction>(name # "64mCL") addr:$dst)>;
1695 defm : MaskedShiftAmountPats<shl, "SHL">;
1696 defm : MaskedShiftAmountPats<srl, "SHR">;
1697 defm : MaskedShiftAmountPats<sra, "SAR">;
1699 // ROL/ROR instructions allow a stronger mask optimization than shift for 8- and
1700 // 16-bit. We can remove a mask of any (bitwidth - 1) on the rotation amount
1701 // because over-rotating produces the same result. This is noted in the Intel
1702 // docs with: "tempCOUNT <- (COUNT & COUNTMASK) MOD SIZE". Masking the rotation
1703 // amount could affect EFLAGS results, but that does not matter because we are
1704 // not tracking flags for these nodes.
1705 multiclass MaskedRotateAmountPats<SDNode frag, string name> {
1706 // (rot x (and y, BitWidth - 1)) ==> (rot x, y)
1707 def : Pat<(frag GR8:$src1, (and CL, immShift8)),
1708 (!cast<Instruction>(name # "8rCL") GR8:$src1)>;
1709 def : Pat<(frag GR16:$src1, (and CL, immShift16)),
1710 (!cast<Instruction>(name # "16rCL") GR16:$src1)>;
1711 def : Pat<(frag GR32:$src1, (and CL, immShift32)),
1712 (!cast<Instruction>(name # "32rCL") GR32:$src1)>;
1713 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift8)), addr:$dst),
1714 (!cast<Instruction>(name # "8mCL") addr:$dst)>;
1715 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift16)), addr:$dst),
1716 (!cast<Instruction>(name # "16mCL") addr:$dst)>;
1717 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1718 (!cast<Instruction>(name # "32mCL") addr:$dst)>;
1720 // (rot x (and y, 63)) ==> (rot x, y)
1721 def : Pat<(frag GR64:$src1, (and CL, immShift64)),
1722 (!cast<Instruction>(name # "64rCL") GR64:$src1)>;
1723 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, immShift64)), addr:$dst),
1724 (!cast<Instruction>(name # "64mCL") addr:$dst)>;
1728 defm : MaskedRotateAmountPats<rotl, "ROL">;
1729 defm : MaskedRotateAmountPats<rotr, "ROR">;
1731 // Double shift amount is implicitly masked.
1732 multiclass MaskedDoubleShiftAmountPats<SDNode frag, string name> {
1733 // (shift x (and y, 31)) ==> (shift x, y)
1734 def : Pat<(frag GR16:$src1, GR16:$src2, (and CL, immShift32)),
1735 (!cast<Instruction>(name # "16rrCL") GR16:$src1, GR16:$src2)>;
1736 def : Pat<(frag GR32:$src1, GR32:$src2, (and CL, immShift32)),
1737 (!cast<Instruction>(name # "32rrCL") GR32:$src1, GR32:$src2)>;
1739 // (shift x (and y, 63)) ==> (shift x, y)
1740 def : Pat<(frag GR64:$src1, GR64:$src2, (and CL, immShift64)),
1741 (!cast<Instruction>(name # "64rrCL") GR64:$src1, GR64:$src2)>;
1744 defm : MaskedDoubleShiftAmountPats<X86shld, "SHLD">;
1745 defm : MaskedDoubleShiftAmountPats<X86shrd, "SHRD">;
1747 let Predicates = [HasBMI2] in {
1748 let AddedComplexity = 1 in {
1749 def : Pat<(sra GR32:$src1, (and GR8:$src2, immShift32)),
1750 (SARX32rr GR32:$src1,
1752 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1753 def : Pat<(sra GR64:$src1, (and GR8:$src2, immShift64)),
1754 (SARX64rr GR64:$src1,
1756 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1758 def : Pat<(srl GR32:$src1, (and GR8:$src2, immShift32)),
1759 (SHRX32rr GR32:$src1,
1761 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1762 def : Pat<(srl GR64:$src1, (and GR8:$src2, immShift64)),
1763 (SHRX64rr GR64:$src1,
1765 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1767 def : Pat<(shl GR32:$src1, (and GR8:$src2, immShift32)),
1768 (SHLX32rr GR32:$src1,
1770 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1771 def : Pat<(shl GR64:$src1, (and GR8:$src2, immShift64)),
1772 (SHLX64rr GR64:$src1,
1774 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1777 def : Pat<(sra (loadi32 addr:$src1), (and GR8:$src2, immShift32)),
1778 (SARX32rm addr:$src1,
1780 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1781 def : Pat<(sra (loadi64 addr:$src1), (and GR8:$src2, immShift64)),
1782 (SARX64rm addr:$src1,
1784 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1786 def : Pat<(srl (loadi32 addr:$src1), (and GR8:$src2, immShift32)),
1787 (SHRX32rm addr:$src1,
1789 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1790 def : Pat<(srl (loadi64 addr:$src1), (and GR8:$src2, immShift64)),
1791 (SHRX64rm addr:$src1,
1793 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1795 def : Pat<(shl (loadi32 addr:$src1), (and GR8:$src2, immShift32)),
1796 (SHLX32rm addr:$src1,
1798 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1799 def : Pat<(shl (loadi64 addr:$src1), (and GR8:$src2, immShift64)),
1800 (SHLX64rm addr:$src1,
1802 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1805 // Use BTR/BTS/BTC for clearing/setting/toggling a bit in a variable location.
1806 multiclass one_bit_patterns<RegisterClass RC, ValueType VT, Instruction BTR,
1807 Instruction BTS, Instruction BTC,
1809 def : Pat<(and RC:$src1, (rotl -2, GR8:$src2)),
1811 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1812 def : Pat<(or RC:$src1, (shl 1, GR8:$src2)),
1814 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1815 def : Pat<(xor RC:$src1, (shl 1, GR8:$src2)),
1817 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1819 // Similar to above, but removing unneeded masking of the shift amount.
1820 def : Pat<(and RC:$src1, (rotl -2, (and GR8:$src2, ImmShift))),
1822 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1823 def : Pat<(or RC:$src1, (shl 1, (and GR8:$src2, ImmShift))),
1825 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1826 def : Pat<(xor RC:$src1, (shl 1, (and GR8:$src2, ImmShift))),
1828 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1831 defm : one_bit_patterns<GR16, i16, BTR16rr, BTS16rr, BTC16rr, immShift16>;
1832 defm : one_bit_patterns<GR32, i32, BTR32rr, BTS32rr, BTC32rr, immShift32>;
1833 defm : one_bit_patterns<GR64, i64, BTR64rr, BTS64rr, BTC64rr, immShift64>;
1836 // (anyext (setcc_carry)) -> (setcc_carry)
1837 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1839 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1841 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1844 //===----------------------------------------------------------------------===//
1845 // EFLAGS-defining Patterns
1846 //===----------------------------------------------------------------------===//
1849 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1850 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1851 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1852 def : Pat<(add GR64:$src1, GR64:$src2), (ADD64rr GR64:$src1, GR64:$src2)>;
1855 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1856 (ADD8rm GR8:$src1, addr:$src2)>;
1857 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1858 (ADD16rm GR16:$src1, addr:$src2)>;
1859 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1860 (ADD32rm GR32:$src1, addr:$src2)>;
1861 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1862 (ADD64rm GR64:$src1, addr:$src2)>;
1865 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1866 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1867 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1868 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1869 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1870 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1871 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1872 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1873 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1874 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1875 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1878 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1879 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1880 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1881 def : Pat<(sub GR64:$src1, GR64:$src2), (SUB64rr GR64:$src1, GR64:$src2)>;
1884 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1885 (SUB8rm GR8:$src1, addr:$src2)>;
1886 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1887 (SUB16rm GR16:$src1, addr:$src2)>;
1888 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1889 (SUB32rm GR32:$src1, addr:$src2)>;
1890 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1891 (SUB64rm GR64:$src1, addr:$src2)>;
1894 def : Pat<(sub GR8:$src1, imm:$src2),
1895 (SUB8ri GR8:$src1, imm:$src2)>;
1896 def : Pat<(sub GR16:$src1, imm:$src2),
1897 (SUB16ri GR16:$src1, imm:$src2)>;
1898 def : Pat<(sub GR32:$src1, imm:$src2),
1899 (SUB32ri GR32:$src1, imm:$src2)>;
1900 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1901 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1902 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1903 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1904 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1905 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1906 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1907 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1910 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>;
1911 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
1912 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
1913 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
1915 // sub reg, relocImm
1916 def : Pat<(X86sub_flag GR64:$src1, i64relocImmSExt8_su:$src2),
1917 (SUB64ri8 GR64:$src1, i64relocImmSExt8_su:$src2)>;
1918 def : Pat<(X86sub_flag GR64:$src1, i64relocImmSExt32_su:$src2),
1919 (SUB64ri32 GR64:$src1, i64relocImmSExt32_su:$src2)>;
1922 def : Pat<(mul GR16:$src1, GR16:$src2),
1923 (IMUL16rr GR16:$src1, GR16:$src2)>;
1924 def : Pat<(mul GR32:$src1, GR32:$src2),
1925 (IMUL32rr GR32:$src1, GR32:$src2)>;
1926 def : Pat<(mul GR64:$src1, GR64:$src2),
1927 (IMUL64rr GR64:$src1, GR64:$src2)>;
1930 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1931 (IMUL16rm GR16:$src1, addr:$src2)>;
1932 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1933 (IMUL32rm GR32:$src1, addr:$src2)>;
1934 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1935 (IMUL64rm GR64:$src1, addr:$src2)>;
1938 def : Pat<(mul GR16:$src1, imm:$src2),
1939 (IMUL16rri GR16:$src1, imm:$src2)>;
1940 def : Pat<(mul GR32:$src1, imm:$src2),
1941 (IMUL32rri GR32:$src1, imm:$src2)>;
1942 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1943 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1944 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1945 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1946 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1947 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1948 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1949 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1951 // reg = mul mem, imm
1952 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1953 (IMUL16rmi addr:$src1, imm:$src2)>;
1954 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1955 (IMUL32rmi addr:$src1, imm:$src2)>;
1956 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1957 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1958 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1959 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1960 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1961 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1962 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1963 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1965 // Increment/Decrement reg.
1966 // Do not make INC/DEC if it is slow
1967 let Predicates = [UseIncDec] in {
1968 def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>;
1969 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>;
1970 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>;
1971 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1972 def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>;
1973 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>;
1974 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>;
1975 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1979 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1980 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1981 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1982 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1985 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1986 (OR8rm GR8:$src1, addr:$src2)>;
1987 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1988 (OR16rm GR16:$src1, addr:$src2)>;
1989 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1990 (OR32rm GR32:$src1, addr:$src2)>;
1991 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1992 (OR64rm GR64:$src1, addr:$src2)>;
1995 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1996 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1997 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1998 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1999 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
2000 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
2001 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
2002 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
2003 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2004 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
2005 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2008 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
2009 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
2010 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
2011 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
2014 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
2015 (XOR8rm GR8:$src1, addr:$src2)>;
2016 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
2017 (XOR16rm GR16:$src1, addr:$src2)>;
2018 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
2019 (XOR32rm GR32:$src1, addr:$src2)>;
2020 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
2021 (XOR64rm GR64:$src1, addr:$src2)>;
2024 def : Pat<(xor GR8:$src1, imm:$src2),
2025 (XOR8ri GR8:$src1, imm:$src2)>;
2026 def : Pat<(xor GR16:$src1, imm:$src2),
2027 (XOR16ri GR16:$src1, imm:$src2)>;
2028 def : Pat<(xor GR32:$src1, imm:$src2),
2029 (XOR32ri GR32:$src1, imm:$src2)>;
2030 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
2031 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
2032 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
2033 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
2034 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
2035 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2036 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
2037 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2040 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
2041 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
2042 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
2043 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
2046 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
2047 (AND8rm GR8:$src1, addr:$src2)>;
2048 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
2049 (AND16rm GR16:$src1, addr:$src2)>;
2050 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
2051 (AND32rm GR32:$src1, addr:$src2)>;
2052 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
2053 (AND64rm GR64:$src1, addr:$src2)>;
2056 def : Pat<(and GR8:$src1, imm:$src2),
2057 (AND8ri GR8:$src1, imm:$src2)>;
2058 def : Pat<(and GR16:$src1, imm:$src2),
2059 (AND16ri GR16:$src1, imm:$src2)>;
2060 def : Pat<(and GR32:$src1, imm:$src2),
2061 (AND32ri GR32:$src1, imm:$src2)>;
2062 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
2063 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
2064 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
2065 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
2066 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
2067 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
2068 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
2069 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
2071 // Bit scan instruction patterns to match explicit zero-undef behavior.
2072 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
2073 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
2074 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
2075 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
2076 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
2077 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;
2079 // When HasMOVBE is enabled it is possible to get a non-legalized
2080 // register-register 16 bit bswap. This maps it to a ROL instruction.
2081 let Predicates = [HasMOVBE] in {
2082 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>;
2085 // These patterns are selected by some custom code in X86ISelDAGToDAG.cpp that
2086 // custom combines and+srl into BEXTR. We use these patterns to avoid a bunch
2087 // of manual code for folding loads.
2088 let Predicates = [HasBMI, NoTBM] in {
2089 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
2090 (BEXTR32rr GR32:$src1, (MOV32ri imm:$src2))>;
2091 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
2092 (BEXTR32rm addr:$src1, (MOV32ri imm:$src2))>;
2093 def : Pat<(X86bextr GR64:$src1, mov64imm32:$src2),
2094 (BEXTR64rr GR64:$src1,
2095 (SUBREG_TO_REG (i64 0),
2096 (MOV32ri64 mov64imm32:$src2),
2098 def : Pat<(X86bextr (loadi64 addr:$src1), mov64imm32:$src2),
2099 (BEXTR64rm addr:$src1,
2100 (SUBREG_TO_REG (i64 0),
2101 (MOV32ri64 mov64imm32:$src2),